diff options
Diffstat (limited to 'fpga/hp_lcd_driver')
| -rw-r--r-- | fpga/hp_lcd_driver/Makefile | 2 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/artix7_ip/blk_mem_gen_0.tcl | 8 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/common.vhdl | 41 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/hp_lcd_driver.vhdl | 5 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/output_stage.vhdl | 4 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/vram_artix7.vhdl | 10 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7.mk | 6 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl | 4 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl | 8 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_wrapper.vhdl | 167 |
10 files changed, 199 insertions, 56 deletions
diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile index f61517d..0558bdd 100644 --- a/fpga/hp_lcd_driver/Makefile +++ b/fpga/hp_lcd_driver/Makefile @@ -1,4 +1,4 @@ -DIP=10.16.66.113 +DIP=10.16.66.234 #TARGETS=rando_a7 TARGETS=ebaz4205 #TARGETS= ebaz4205 #rando_a7 #smh-ac415b #spartan6 #ep4ce6 smh-ac415 diff --git a/fpga/hp_lcd_driver/artix7_ip/blk_mem_gen_0.tcl b/fpga/hp_lcd_driver/artix7_ip/blk_mem_gen_0.tcl index 84626aa..3c6a7f7 100644 --- a/fpga/hp_lcd_driver/artix7_ip/blk_mem_gen_0.tcl +++ b/fpga/hp_lcd_driver/artix7_ip/blk_mem_gen_0.tcl @@ -11,12 +11,12 @@ set_property -dict [list \ CONFIG.Enable_32bit_Address {false} \ CONFIG.Use_Byte_Write_Enable {false} \ CONFIG.Byte_Size {9} \ - CONFIG.Write_Width_A {6} \ + CONFIG.Write_Width_A {4} \ CONFIG.Write_Depth_A {245760} \ - CONFIG.Read_Width_A {6} \ + CONFIG.Read_Width_A {4} \ CONFIG.Operating_Mode_A {NO_CHANGE} \ - CONFIG.Write_Width_B {6} \ - CONFIG.Read_Width_B {6} \ + CONFIG.Write_Width_B {4} \ + CONFIG.Read_Width_B {4} \ CONFIG.Enable_B {Use_ENB_Pin} \ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \ diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl index 7275184..08895d8 100644 --- a/fpga/hp_lcd_driver/common.vhdl +++ b/fpga/hp_lcd_driver/common.vhdl @@ -43,7 +43,10 @@ entity common is video_out_data : out std_logic_vector(video_width-1 downto 0); video_out_valid : out std_logic; video_out_clk : out std_logic; - video_out_index : out std_logic + video_out_index : out std_logic; + video_in_addr : out std_logic_vector(addr_width-1 downto 0); + video_in_clk : out std_logic; + video_in_data : in std_logic_vector(1 downto 0) ); end common; @@ -62,6 +65,9 @@ architecture Behavioral of common is signal r : std_logic_vector(7 downto 0); signal g : std_logic_vector(7 downto 0); signal b : std_logic_vector(7 downto 0); + signal r_s : std_logic_vector(7 downto 0); + signal g_s : std_logic_vector(7 downto 0); + signal b_s : std_logic_vector(7 downto 0); signal clk_locked : std_logic; @@ -242,34 +248,35 @@ begin rd_data => rd_data ); + video_in_addr <= rd_addr; + video_in_clk <= o_clk; --- r<=x"00"; --- b<=x"00"; - - - - r <= x"ff" when rd_data(0) = '1' else + r_s <= x"ff" when rd_data(0) = '1' else x"00"; - --- r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else --- x"80" when rd_data(0)='1' else --- x"00"; - - g <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else + g_s <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else x"80" when rd_data(1) = '1' else x"00"; - b <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else + b_s <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else x"80" when rd_data(2) = '1' else x"00"; ---"ff" when rd_data(1) = '1' else --- x"80" when rd_data(0) = '1' else --- ix"00"; +-- r <= r_s when video_in_data(1) = '0' else +-- x"00" when video_in_data(0)='0' else +-- x"ff"; +-- g <= g_s when video_in_data(1) = '0' else +-- x"00" when video_in_data(0)='0' else +-- x"ff"; +-- b <= b_s when video_in_data(1) = '0' else +-- x"00" when video_in_data(0)='0' else +-- x"ff"; +r<=r_s; +g<=g_s; +b<=b_s; diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl index 15fe76f..d68afa5 100644 --- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl @@ -74,7 +74,10 @@ begin video_out_clk => open, video_out_index => open, video_out_data => open, - video_out_valid => open + video_out_valid => open, + video_in_clk => open, + video_in_addr => open, + video_in_data => x"00" ); end Behavioral; diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl index 9808a42..234d16d 100644 --- a/fpga/hp_lcd_driver/output_stage.vhdl +++ b/fpga/hp_lcd_driver/output_stage.vhdl @@ -35,7 +35,6 @@ entity output_stage is g_in : in std_logic_vector(7 downto 0); b_in : in std_logic_vector(7 downto 0); - r_out : out std_logic; g_out : out std_logic; b_out : out std_logic; @@ -138,11 +137,10 @@ begin o => grid_d ); - r <= r_in; + r <= r_in when grid_d='0' else x"ff"; g <= g_in; b <= b_in; - dh : entity work.delay generic map(stages => 2) port map ( diff --git a/fpga/hp_lcd_driver/vram_artix7.vhdl b/fpga/hp_lcd_driver/vram_artix7.vhdl index 96733da..6fdc3b1 100644 --- a/fpga/hp_lcd_driver/vram_artix7.vhdl +++ b/fpga/hp_lcd_driver/vram_artix7.vhdl @@ -19,14 +19,8 @@ end vram; architecture beh of vram is signal wr_en_v : std_logic_vector(0 downto 0); - signal wr_data_6 : std_logic_vector(5 downto 0); - signal rd_data_6 : std_logic_vector(5 downto 0); begin - wr_data_6 <= "00" & wr_data; - rd_data <= rd_data_6(3 downto 0); - - wr_en_v(0) <= wr_en; bmg0 : entity work.blk_mem_gen_0 @@ -36,9 +30,9 @@ begin clka => wr_clk, wea => wr_en_v, addra => wr_addr, - dina => wr_data_6, + dina => wr_data, clkb => rd_clk, - doutb => rd_data_6, + doutb => rd_data, addrb => rd_addr ); end beh; diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk index e6acad8..1426f38 100644 --- a/fpga/hp_lcd_driver/zynq7.mk +++ b/fpga/hp_lcd_driver/zynq7.mk @@ -4,6 +4,8 @@ IP= \ zynq7_ip/mmcm_0.tcl \ zynq7_ip/mmcm_1.tcl \ zynq7_ip/blk_mem_gen_0.tcl \ + zynq7_ip/blk_mem_gen_1.tcl \ + zynq7_ip/axi_bram_ctrl_0.tcl \ zynq7_ip/processing_system7_0.tcl \ zynq7_ip/fifo_generator_0.tcl @@ -33,9 +35,11 @@ SRCS= ${IP} \ tmds_output_artix7.vhdl \ tmds_phy_artix7.vhdl \ vram_artix7.vhdl \ + overlay_vram_artix7.vhdl \ zynq7_wrapper.vhdl \ fifo_to_axi.vhdl \ - vnc_serializer.vhdl + vnc_serializer.vhdl + diff --git a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl index 1af332f..babcc70 100644 --- a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl +++ b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl @@ -20,7 +20,7 @@ if {[llength $files] != 0} { #read_verilog [ glob ../source/*.v ] #read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ] -read_vhdl -vhdl2008 -library work { ../zynq7_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../common.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl ../vnc_serializer.vhdl } +read_vhdl -vhdl2008 -library work { ../zynq7_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../common.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl ../vnc_serializer.vhdl ../overlay_vram_artix7.vhdl } set generics {} append generics { } "video_width=$video_width" @@ -34,6 +34,8 @@ puts $generics read_ip $ip_dir/mmcm_0/mmcm_0.xci read_ip $ip_dir/mmcm_1/mmcm_1.xci read_ip $ip_dir/blk_mem_gen_0/blk_mem_gen_0.xci +read_ip $ip_dir/blk_mem_gen_1/blk_mem_gen_1.xci +read_ip $ip_dir/axi_bram_ctrl_0/axi_bram_ctrl_0.xci read_ip $ip_dir/processing_system7_0/processing_system7_0.xci read_ip $ip_dir/fifo_generator_0/fifo_generator_0.xci diff --git a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl index b3e3dce..47aa829 100644 --- a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl +++ b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl @@ -11,12 +11,12 @@ set_property -dict [list \ CONFIG.Enable_32bit_Address {false} \ CONFIG.Use_Byte_Write_Enable {false} \ CONFIG.Byte_Size {9} \ - CONFIG.Write_Width_A {6} \ + CONFIG.Write_Width_A {4} \ CONFIG.Write_Depth_A {245760} \ - CONFIG.Read_Width_A {6} \ + CONFIG.Read_Width_A {4} \ CONFIG.Operating_Mode_A {NO_CHANGE} \ - CONFIG.Write_Width_B {6} \ - CONFIG.Read_Width_B {6} \ + CONFIG.Write_Width_B {4} \ + CONFIG.Read_Width_B {4} \ CONFIG.Enable_B {Use_ENB_Pin} \ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \ diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl index 2c732a0..00d56a8 100644 --- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl +++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl @@ -110,6 +110,38 @@ architecture arch of zynq7_wrapper is signal gp0_aclk : std_logic; signal gp0_nrst : std_logic; + signal gp0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal gp0_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal gp0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal gp0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal gp0_awlock : STD_LOGIC_VECTOR ( 1 downto 0); + signal gp0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal gp0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal gp0_awvalid : STD_LOGIC; + signal gp0_awready : STD_LOGIC; + signal gp0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal gp0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal gp0_wlast : STD_LOGIC; + signal gp0_wvalid : STD_LOGIC; + signal gp0_wready : STD_LOGIC; + signal gp0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal gp0_bvalid : STD_LOGIC; + signal gp0_bready : STD_LOGIC; + signal gp0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal gp0_arlen : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal gp0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal gp0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal gp0_arlock : STD_LOGIC_VECTOR( 1 downto 0); + signal gp0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal gp0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal gp0_arvalid : STD_LOGIC; + signal gp0_arready : STD_LOGIC; + signal gp0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal gp0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal gp0_rlast : STD_LOGIC; + signal gp0_rvalid : STD_LOGIC; + signal gp0_rready : STD_LOGIC; + signal hp0_aclk : std_logic; signal hp0_nrst : std_logic; signal hp0_arvalid : std_logic; @@ -150,7 +182,22 @@ architecture arch of zynq7_wrapper is signal vnc_data : std_logic_vector(video_width-1 downto 0); signal vnc_index : std_logic; + signal clk_50m_ps : std_logic; + signal overlay_r_addr : std_logic_vector(addr_width-1 downto 0); + signal overlay_r_clk : std_logic; + signal overlay_r_data : std_logic_vector(1 downto 0); + + signal overlay_w_clk : std_logic; + signal overlay_w_en : std_logic; + signal overlay_w_data : std_logic_vector(1 downto 0); + signal overlay_w_addr : std_logic_vector(addr_width-1 downto 0); + + signal mem_ctl_addr : std_logic_vector (19 downto 0); + signal mem_ctl_data : std_logic_vector (31 downto 0); + signal mem_ctl_we_a : std_logic_vector (3 downto 0); + + begin @@ -164,7 +211,7 @@ begin i_clk_multiple => i_clk_multiple, use_pclk => use_pclk, target => target) - port map (clk_50m => clk_50m, + port map (clk_50m => clk_50m_ps, sys_rst_n => sys_rst_n, video => video, hsync_in => hsync_in, @@ -189,7 +236,10 @@ begin video_out_clk => vnc_clk, video_out_valid => vnc_valid, video_out_data => vnc_data, - video_out_index => vnc_index + video_out_index => vnc_index, + video_in_clk => overlay_r_clk, + video_in_addr => overlay_r_addr, + video_in_data => overlay_r_data ); processing_system7_0_i : entity work.processing_system7_0 @@ -212,7 +262,7 @@ begin FCLK_CLK0 => eth0_clk_o, FCLK_CLK1 => gp0_aclk, FCLK_CLK2 => hp0_aclk, - FCLK_CLK2 => open, + FCLK_CLK3 => clk_50m_ps, FCLK_RESET1_N => gp0_nrst, FCLK_RESET2_N => hp0_nrst, FCLK_RESET3_N => sys_rst_n, @@ -244,18 +294,38 @@ begin GPIO_T => emio_t, M_AXI_GP0_ACLK => gp0_aclk, - M_AXI_GP0_ARREADY => '0', - M_AXI_GP0_AWREADY => '0', - M_AXI_GP0_BID => (others => '0'), - M_AXI_GP0_BRESP => (others => '0'), - M_AXI_GP0_BVALID => '0', - M_AXI_GP0_RDATA => (others => '0'), - M_AXI_GP0_RID => (others => '0'), - M_AXI_GP0_RLAST => '1', - M_AXI_GP0_RRESP => (others => '0'), - M_AXI_GP0_RVALID => '0', - M_AXI_GP0_WREADY => '0', + M_AXI_GP0_AWADDR => gp0_awaddr , + M_AXI_GP0_AWLEN => gp0_awlen , + M_AXI_GP0_AWSIZE => gp0_awsize , + M_AXI_GP0_AWBURST => gp0_awburst , + M_AXI_GP0_AWLOCK => gp0_awlock , + M_AXI_GP0_AWCACHE => gp0_awcache , + M_AXI_GP0_AWPROT => gp0_awprot , + M_AXI_GP0_AWVALID => gp0_awvalid , + M_AXI_GP0_AWREADY => gp0_awready , + M_AXI_GP0_WDATA => gp0_wdata , + M_AXI_GP0_WSTRB => gp0_wstrb , + M_AXI_GP0_WLAST => gp0_wlast , + M_AXI_GP0_WVALID => gp0_wvalid , + M_AXI_GP0_WREADY => gp0_wready , + M_AXI_GP0_BRESP => gp0_bresp , + M_AXI_GP0_BVALID => gp0_bvalid , + M_AXI_GP0_BREADY => gp0_bready , + M_AXI_GP0_ARADDR => gp0_araddr , + M_AXI_GP0_ARLEN => gp0_arlen , + M_AXI_GP0_ARSIZE => gp0_arsize , + M_AXI_GP0_ARBURST => gp0_arburst , + M_AXI_GP0_ARLOCK => gp0_arlock , + M_AXI_GP0_ARCACHE => gp0_arcache , + M_AXI_GP0_ARPROT => gp0_arprot , + M_AXI_GP0_ARVALID => gp0_arvalid , + M_AXI_GP0_ARREADY => gp0_arready , + M_AXI_GP0_RDATA => gp0_rdata , + M_AXI_GP0_RRESP => gp0_rresp , + M_AXI_GP0_RLAST => gp0_rlast , + M_AXI_GP0_RVALID => gp0_rvalid , + M_AXI_GP0_RREADY => gp0_rready , S_AXI_HP0_ACLK => hp0_aclk, S_AXI_HP0_ARADDR => hp0_araddr, @@ -321,9 +391,9 @@ begin fifo_wren => fifo_wr_en); - process (clk_50m) + process (clk_50m_ps) begin - if rising_edge(clk_50m) then + if rising_edge(clk_50m_ps) then if sys_rst_n = '0' then fifo_rst_cnt <= 20; fifo_rst <= '1'; @@ -371,6 +441,71 @@ begin ); + overlay_vram0 : entity work.overlay_vram + generic map ( + addr_width => addr_width + ) + port map ( + wr_clk => overlay_w_clk, + wr_en => overlay_w_en, + wr_addr => overlay_w_addr, + wr_data => overlay_w_data, + rd_clk => overlay_r_clk, + rd_addr => overlay_r_addr, + rd_data => overlay_r_data + ); + + axi_bram_ctrl_0_i : entity work.axi_bram_ctrl_0 + port map ( + s_axi_aclk => gp0_aclk, + s_axi_aresetn => gp0_nrst, + + s_axi_awaddr => gp0_awaddr(19 downto 0) , + s_axi_awlen => gp0_awlen , + s_axi_awsize => gp0_awsize , + s_axi_awburst => gp0_awburst , + s_axi_awlock => gp0_awlock(0) , + s_axi_awcache => gp0_awcache , + s_axi_awprot => gp0_awprot , + s_axi_awvalid => gp0_awvalid , + s_axi_awready => gp0_awready , + s_axi_wdata => gp0_wdata , + s_axi_wstrb => gp0_wstrb , + s_axi_wlast => gp0_wlast , + s_axi_wvalid => gp0_wvalid , + s_axi_wready => gp0_wready , + s_axi_bresp => gp0_bresp , + s_axi_bvalid => gp0_bvalid , + s_axi_bready => gp0_bready , + s_axi_araddr => gp0_araddr (19 downto 0) , + s_axi_arlen => gp0_arlen , + s_axi_arsize => gp0_arsize , + s_axi_arburst => gp0_arburst , + s_axi_arlock => gp0_arlock(0) , + s_axi_arcache => gp0_arcache , + s_axi_arprot => gp0_arprot , + s_axi_arvalid => gp0_arvalid , + s_axi_arready => gp0_arready , + s_axi_rdata => gp0_rdata , + s_axi_rresp => gp0_rresp , + s_axi_rlast => gp0_rlast , + s_axi_rvalid => gp0_rvalid , + s_axi_rready => gp0_rready , + + bram_rst_a => open, + bram_clk_a => overlay_w_clk, + bram_en_a =>open, + bram_we_a => mem_ctl_we_a, + bram_addr_a => mem_ctl_addr, + bram_wrdata_a => mem_ctl_data, + bram_rddata_a => x"12345678" + ); + + + overlay_w_addr <= mem_ctl_addr(addr_width -1 downto 0); + overlay_w_data <= mem_ctl_data(1 downto 0); + overlay_w_en <=mem_ctl_we_a(0); + hp0_araddr <= (others => '0'); hp0_arvalid <= '0'; hp0_rready <= '0'; |