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Diffstat (limited to 'fpga/hp_lcd_driver/tmds_phy_artix7.vhdl')
-rw-r--r--fpga/hp_lcd_driver/tmds_phy_artix7.vhdl9
1 files changed, 5 insertions, 4 deletions
diff --git a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
index 26f29c0..604ec23 100644
--- a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
+++ b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
@@ -22,6 +22,7 @@ end tmds_phy_artix7;
architecture beh of tmds_phy_artix7 is
signal ld : std_logic_vector(9 downto 0);
+ signal ld2 : std_logic_vector(9 downto 0);
signal sr : std_logic_vector(9 downto 0);
signal s : std_logic;
@@ -32,7 +33,7 @@ begin
process(pix_clk)
begin
if rising_edge(pix_clk) then
- ld <= din;
+ ld2 <= din;
end if;
end process;
@@ -69,9 +70,9 @@ begin
process(phy_clk)
begin
if rising_edge(phy_clk) then
--- if b=5 then
--- ld2<=ld;
--- end if;
+ if b=5 then
+ ld<=ld2;
+ end if;
if b = 0 then
sr <= ld;
else