diff options
Diffstat (limited to 'fpga/hp_lcd_driver/tmds_encoder_c.vhdl')
| -rw-r--r-- | fpga/hp_lcd_driver/tmds_encoder_c.vhdl | 162 |
1 files changed, 0 insertions, 162 deletions
diff --git a/fpga/hp_lcd_driver/tmds_encoder_c.vhdl b/fpga/hp_lcd_driver/tmds_encoder_c.vhdl deleted file mode 100644 index 03415aa..0000000 --- a/fpga/hp_lcd_driver/tmds_encoder_c.vhdl +++ /dev/null @@ -1,162 +0,0 @@ ---------------------------------------------------------------------------------
---
--- FileName: tmds_encoder.vhd
--- Dependencies: none
--- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Full Version
---
--- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
--- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
--- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
--- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
--- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
--- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
--- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
--- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
--- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
---
--- Version History
--- Version 1.0 8/7/2014 Scott Larson
--- Initial Public Release
--- Version 2.0 2/24/2014 Scott Larson
--- Corrected bug in the control signals
---
---------------------------------------------------------------------------------
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY tmds_encoder IS
- PORT(
- clk : in std_logic;
- sys_rst_n : in std_logic;
- blank : in std_logic;
- ctrl : in std_logic_vector(1 downto 0);
- din : in std_logic_vector(7 downto 0);
- dout : out std_logic_vector(9 downto 0)
- );
-END tmds_encoder;
-
-ARCHITECTURE logic OF tmds_encoder IS
- SIGNAL dind : std_logic_vector(7 downto 0);
- SIGNAL q_m : STD_LOGIC_VECTOR(8 DOWNTO 0); --internal data
- SIGNAL q_md : STD_LOGIC_VECTOR(8 DOWNTO 0); --internal data
- SIGNAL ones_din : INTEGER RANGE 0 TO 8; --number of ones in the input data
- SIGNAL ones_dind : INTEGER RANGE 0 TO 8; --number of ones in the input data
- SIGNAL ones_q_md : INTEGER RANGE 0 TO 8; --number of ones in the internal data
- SIGNAL diff_q_md : INTEGER RANGE -8 TO 8; --number of ones minus the number of zeros in the internal data
- SIGNAL disparity : INTEGER RANGE -16 TO 15; --disparity
-BEGIN
-
- --count the ones in the input data byte
- PROCESS(din)
- VARIABLE ones: INTEGER RANGE 0 TO 8;
- BEGIN
- ones := 0;
- FOR i IN 0 TO 7 LOOP
- IF(din(i) = '1') THEN
- ones := ones + 1;
- END IF;
- END LOOP;
- ones_din <= ones;
- END PROCESS;
-
- process(clk) begin
- if rising_edge(clk) then
- dind<=din;
- ones_dind<=ones_din;
- end if;
- end process;
-
-
- --process interval data to minimize transitions
- PROCESS(dind, q_m, ones_dind)
- BEGIN
- IF(ones_dind > 4 OR (ones_dind = 4 AND dind(0) = '0')) THEN
- q_m(0) <= dind(0);
- q_m(1) <= q_m(0) XNOR dind(1);
- q_m(2) <= q_m(1) XNOR dind(2);
- q_m(3) <= q_m(2) XNOR dind(3);
- q_m(4) <= q_m(3) XNOR dind(4);
- q_m(5) <= q_m(4) XNOR dind(5);
- q_m(6) <= q_m(5) XNOR dind(6);
- q_m(7) <= q_m(6) XNOR dind(7);
- q_m(8) <= '0';
- ELSE
- q_m(0) <= dind(0);
- q_m(1) <= q_m(0) XOR dind(1);
- q_m(2) <= q_m(1) XOR dind(2);
- q_m(3) <= q_m(2) XOR dind(3);
- q_m(4) <= q_m(3) XOR dind(4);
- q_m(5) <= q_m(4) XOR dind(5);
- q_m(6) <= q_m(5) XOR dind(6);
- q_m(7) <= q_m(6) XOR dind(7);
- q_m(8) <= '1';
- END IF;
- END PROCESS;
-
- process(clk) begin
- if rising_edge(clk) then
- q_md<=q_m;
- end if;
- end process;
-
-
-
- --count the ones in the internal data
- PROCESS(q_md)
- VARIABLE ones: INTEGER RANGE 0 TO 8;
- BEGIN
- ones := 0;
- FOR i IN 0 TO 7 LOOP
- IF(q_md(i) = '1') THEN
- ones := ones + 1;
- END IF;
- END LOOP;
- ones_q_md <= ones;
- diff_q_md <= ones + ones - 8; --determine the difference between the number of ones and zeros
- END PROCESS;
-
- --determine output and new disparity
- PROCESS(clk)
- BEGIN
- IF(clk'EVENT AND clk = '1') THEN
- IF(blank = '0') THEN
- IF(disparity = 0 OR ones_q_md = 4) THEN
- IF(q_md(8) = '0') THEN
- dout <= NOT q_md(8) & q_md(8) & NOT q_md(7 DOWNTO 0);
- disparity <= disparity - diff_q_md;
- ELSE
- dout <= NOT q_md(8)& q_md(8 DOWNTO 0);
- disparity <= disparity + diff_q_md;
- END IF;
- ELSE
- IF((disparity > 0 AND ones_q_md > 4) OR (disparity < 0 AND ones_q_md < 4)) THEN
- dout <= '1' & q_md(8) & NOT q_md(7 DOWNTO 0);
- IF(q_md(8) = '0') THEN
- disparity <= disparity - diff_q_md;
- ELSE
- disparity <= disparity - diff_q_md + 2;
- END IF;
- ELSE
- dout <= '0' & q_md(8 DOWNTO 0);
- IF(q_md(8) = '0') THEN
- disparity <= disparity + diff_q_md - 2;
- ELSE
- disparity <= disparity + diff_q_md;
- END IF;
- END IF;
- END IF;
- ELSE
- CASE ctrl IS
- WHEN "00" => dout <= "1101010100";
- WHEN "01" => dout <= "0010101011";
- WHEN "10" => dout <= "0101010100";
- WHEN "11" => dout <= "1010101011";
- WHEN OTHERS => NULL;
- END CASE;
- disparity <= 0;
- END IF;
- END IF;
- END PROCESS;
-
-END logic;
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