diff options
Diffstat (limited to 'fpga/hp_lcd_driver/ebaz4205.xdc')
| -rw-r--r-- | fpga/hp_lcd_driver/ebaz4205.xdc | 34 |
1 files changed, 16 insertions, 18 deletions
diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc index 64660eb..30b073a 100644 --- a/fpga/hp_lcd_driver/ebaz4205.xdc +++ b/fpga/hp_lcd_driver/ebaz4205.xdc @@ -27,8 +27,8 @@ set_property PACKAGE_PIN W14 [get_ports {red_led}] set_property IOSTANDARD LVCMOS33 [get_ports *_led] -#set_property IOSTANDARD LVCMOS33 [get_ports clk_50m] -#set_property PACKAGE_PIN R4 [get_ports clk_50m] +set_property IOSTANDARD LVCMOS33 [get_ports clk_50m] +set_property PACKAGE_PIN N18 [get_ports clk_50m] #set_property PACKAGE_PIN T1 [get_ports {led_1}] #set_property IOSTANDARD LVCMOS33 [get_ports {led_1}] @@ -37,14 +37,10 @@ set_property PACKAGE_PIN G19 [get_ports {hdmi_b_p}]; #data2-5 set_property PACKAGE_PIN G20 [get_ports {hdmi_b_n}]; #data2-7 set_property PACKAGE_PIN K19 [get_ports {hdmi_g_p}]; #data2-13 set_property PACKAGE_PIN J19 [get_ports {hdmi_g_n}]; #data2-9 -#set_property PACKAGE_PIN T20 [get_ports {hdmi_g_p}]; #data3-16 -#set_property PACKAGE_PIN U20 [get_ports {hdmi_g_n}]; #data3-17 set_property PACKAGE_PIN L19 [get_ports {hdmi_r_p}]; #data2-16 set_property PACKAGE_PIN L20 [get_ports {hdmi_r_n}]; #data2-18 set_property PACKAGE_PIN L16 [get_ports {hdmi_c_p}]; #data2-15 set_property PACKAGE_PIN L17 [get_ports {hdmi_c_n}]; #data2-20 -#set_property PACKAGE_PIN N17 [get_ports {hdmi_c_p}]; #data3-9 -#set_property PACKAGE_PIN P18 [get_ports {hdmi_c_n}]; #data3-7 set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}] @@ -55,13 +51,13 @@ set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}] -##set_property DRIVE 16 [get_ports {hdmi_c_p}] -##set_property DRIVE 16 [get_ports {hdmi_c_n}] -##set_property DRIVE 16 [get_ports {hdmi_r_p}] -##set_property DRIVE 16 [get_ports {hdmi_r_n}] -##set_property DRIVE 16 [get_ports {hdmi_g_p}] -##set_property DRIVE 16 [get_ports {hdmi_g_n}] -##set_property DRIVE 16 [get_ports {hdmi_b_p}] +set_property DRIVE 16 [get_ports {hdmi_c_p}] +set_property DRIVE 16 [get_ports {hdmi_c_n}] +set_property DRIVE 16 [get_ports {hdmi_r_p}] +set_property DRIVE 16 [get_ports {hdmi_r_n}] +set_property DRIVE 16 [get_ports {hdmi_g_p}] +set_property DRIVE 16 [get_ports {hdmi_g_n}] +set_property DRIVE 16 [get_ports {hdmi_b_p}] # set_property PACKAGE_PIN K18 [get_ports {hdmi_vcc}]; #data2-11 (12 is gnd) set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}] @@ -120,7 +116,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}] #set_property IOSTANDARD LVCMOS33 [get_ports {sys_rst_n}] #set_property PULLTYPE PULLUP [get_ports {sys_rst_n}] # -#create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m] + +create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m] ##set_false_path -from [get_ports pci_exp_rst_n] # @@ -147,10 +144,11 @@ set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] -set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[*]/D}] 9 -set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[*]/D}] 9 -set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[*]/D}] 9 -set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[*]/D}] 9 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[*]/D}] 7 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[*]/D}] 7 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[*]/D}] 7 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[*]/D}] 7 + |