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-rw-r--r--spartan6/hp_lcd_driver/clkgen_spartan6.vhdl48
-rw-r--r--spartan6/hp_lcd_driver/hp_lcd_driver.vhdl88
-rw-r--r--spartan6/hp_lcd_driver/input_formatter.vhdl103
-rw-r--r--spartan6/hp_lcd_driver/output_formatter.vhdl4
-rw-r--r--spartan6/hp_lcd_driver/output_stage.vhdl70
-rw-r--r--spartan6/hp_lcd_driver/tmds_encode.vhdl28
-rw-r--r--spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl30
-rw-r--r--spartan6/hp_lcd_driver/tmds_phy.vhdl4
8 files changed, 188 insertions, 187 deletions
diff --git a/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl b/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl
index e3c0242..f12c9c4 100644
--- a/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl
+++ b/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl
@@ -8,27 +8,27 @@ use UNISIM.vcomponents.all;
entity clkgen_spartan6 is
port (
- sys_rst_n:in std_logic;
- clk_in: in std_logic;
- i_clk:out std_logic;
- o_clk:out std_logic;
- o_clk_x2: out std_logic;
- o_clk_x10: out std_logic;
- locked: out std_logic
- );
+ sys_rst_n : in std_logic;
+ clk_in : in std_logic;
+ i_clk : out std_logic;
+ o_clk : out std_logic;
+ o_clk_x2 : out std_logic;
+ o_clk_x10 : out std_logic;
+ locked : out std_logic
+ );
end clkgen_spartan6;
architecture Behavioural of clkgen_spartan6 is
- signal clkfbout : std_logic;
- signal clk_200m : std_logic;
- signal clk_80m : std_logic;
- signal clk_40m : std_logic;
- signal clk_20m : std_logic;
- signal pll_locked : std_logic;
+ signal clkfbout : std_logic;
+ signal clk_200m : std_logic;
+ signal clk_80m : std_logic;
+ signal clk_40m : std_logic;
+ signal clk_20m : std_logic;
+ signal pll_locked : std_logic;
+
+ signal reset : std_logic;
+begin
- signal reset : std_logic;
-begin
-
pll : PLL_BASE generic map (
CLKIN_PERIOD => 20.0,
CLKFBOUT_MULT => 8,
@@ -53,19 +53,19 @@ begin
o_clk_buf : BUFG port map (
- I =>clk_20m,
- O =>o_clk);
+ I => clk_20m,
+ O => o_clk);
o_clk_x2_buf : BUFG port map (
- I =>clk_40m,
- O =>o_clk_x2);
+ I => clk_40m,
+ O => o_clk_x2);
i_clk_buf : BUFG port map (
- I =>clk_80m,
- O =>i_clk);
-
+ I => clk_80m,
+ O => i_clk);
+
o_clk_x10 <= clk_200m;
locked <= pll_locked;
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
index 0337320..53c3e5f 100644
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -6,7 +6,7 @@ use work.all;
entity hp_lcd_driver is
generic (video_width : natural := 2;
addr_width : natural := 18;
- target : string := "spartan6" );
+ target : string := "spartan6");
port (clk_50m : in std_logic;
sys_rst_n : in std_logic;
video : in std_logic_vector(video_width-1 downto 0);
@@ -46,26 +46,26 @@ architecture Behavioral of hp_lcd_driver is
signal i_clk : std_logic;
- signal o_clk : std_logic;
- signal o_clk_x2 : std_logic;
- signal o_clk_x10 : std_logic;
- signal sys_rst : std_logic;
+ signal o_clk : std_logic;
+ signal o_clk_x2 : std_logic;
+ signal o_clk_x10 : std_logic;
+ signal sys_rst : std_logic;
begin
- clkgen: entity work.clkgen_spartan6
- port map (
- sys_rst_n => sys_rst_n,
- clk_in => clk_50m,
- i_clk => i_clk,
- o_clk => o_clk,
- o_clk_x2 => o_clk_x2,
- o_clk_x10 => o_clk_x10,
- locked => clk_locked
-
- );
+ clkgen : entity work.clkgen_spartan6
+ port map (
+ sys_rst_n => sys_rst_n,
+ clk_in => clk_50m,
+ i_clk => i_clk,
+ o_clk => o_clk,
+ o_clk_x2 => o_clk_x2,
+ o_clk_x10 => o_clk_x10,
+ locked => clk_locked
+
+ );
input0 : entity work.input_stage
generic map(
@@ -104,12 +104,12 @@ begin
r <= x"ff" when rd_data(1) = '1' else
- x"00";
+ x"00";
g <= x"ff" when rd_data(0) = '1' else
- x"ff" when rd_data(1) = '1' else
- x"00";
+ x"ff" when rd_data(1) = '1' else
+ x"00";
b <= x"ff" when rd_data(1) = '1' else
- x"00";
+ x"00";
@@ -117,7 +117,7 @@ begin
-- works at 60Hz xrandr --newmode "$M" 18.24 384 400 440 600 592 593 596 613 -HSync +Vsync
generic map (
- target => target,
+ target => target,
addr_width => addr_width,
h_active => 384,
h_sync_start => 400,
@@ -131,29 +131,29 @@ begin
v_stride => 384
)
port map(
- clk_locked => clk_locked,
- clk => o_clk,
- clk_x2 => o_clk_x2,
- clk_x10 => o_clk_x10,
- sys_rst_n => sys_rst_n,
- vsync_in => vsync_in,
- r_in => r,
- g_in => g,
- b_in => b,
- addr_out => rd_addr,
- r_out => r_out,
- g_out => g_out,
- b_out => b_out,
- hsync_out => hsync_out,
- vsync_out => vsync_out,
- hdmi_c_p => hdmi_c_p,
- hdmi_c_n => hdmi_c_n,
- hdmi_r_p => hdmi_r_p,
- hdmi_r_n => hdmi_r_n,
- hdmi_g_p => hdmi_g_p,
- hdmi_g_n => hdmi_g_n,
- hdmi_b_p => hdmi_b_p,
- hdmi_b_n => hdmi_b_n
+ clk_locked => clk_locked,
+ clk => o_clk,
+ clk_x2 => o_clk_x2,
+ clk_x10 => o_clk_x10,
+ sys_rst_n => sys_rst_n,
+ vsync_in => vsync_in,
+ r_in => r,
+ g_in => g,
+ b_in => b,
+ addr_out => rd_addr,
+ r_out => r_out,
+ g_out => g_out,
+ b_out => b_out,
+ hsync_out => hsync_out,
+ vsync_out => vsync_out,
+ hdmi_c_p => hdmi_c_p,
+ hdmi_c_n => hdmi_c_n,
+ hdmi_r_p => hdmi_r_p,
+ hdmi_r_n => hdmi_r_n,
+ hdmi_g_p => hdmi_g_p,
+ hdmi_g_n => hdmi_g_n,
+ hdmi_b_p => hdmi_b_p,
+ hdmi_b_n => hdmi_b_n
);
diff --git a/spartan6/hp_lcd_driver/input_formatter.vhdl b/spartan6/hp_lcd_driver/input_formatter.vhdl
index ecde480..d50a43e 100644
--- a/spartan6/hp_lcd_driver/input_formatter.vhdl
+++ b/spartan6/hp_lcd_driver/input_formatter.vhdl
@@ -39,7 +39,7 @@ architecture beh of input_formatter is
signal v_active_counter : natural;
signal h_fp_counter : natural;
signal h_active_counter : natural;
- signal h_div:natural;
+ signal h_div : natural;
begin
@@ -49,8 +49,8 @@ begin
port map(
clk => clk,
sig => hsync,
- e => open,
- pe => open,
+ e => open,
+ pe => open,
ne => hsync_ne);
@@ -59,53 +59,54 @@ begin
addr_out <= addr;
- process (sys_rst_n,clk,hsync_ne,vsync) begin
- if sys_rst_n = '0' then
- row_addr<=(others =>'0');
- addr<=(others =>'0');
- h_div <=0;
- h_active_counter <=0;
- h_fp_counter <=0;
- v_active_counter <=0;
- v_fp_counter <=0;
- elsif rising_edge(clk) then
- if hsync_ne = '1' then
- if vsync='1' then
- row_addr<=(others =>'0');
- v_fp_counter <= v_front_porch;
- v_active_counter <= v_active;
- elsif v_fp_counter /= 0 then
- v_fp_counter <= v_fp_counter -1;
- elsif v_active_counter /= 0 then
- v_active_counter <=v_active_counter -1;
-
- h_fp_counter <= h_front_porch * clk_multiple + phase;
- h_active_counter <= h_active;
- h_div <=0;
-
- addr<=row_addr;
- row_addr<=std_logic_vector(unsigned(row_addr)+v_stride);
- end if;
- elsif h_fp_counter /= 0 then
- h_fp_counter <= h_fp_counter -1;
- elsif h_active_counter /= 0 then
-
- if h_div = 0 then
- wren <='1';
- h_div <= clk_multiple -1;
- elsif h_div =clk_multiple -1 then
- wren <='0';
- h_active_counter <= h_active_counter -1;
- addr<=std_logic_vector(unsigned(addr)+h_stride);
- h_div <=clk_multiple -1;
- else
- h_div <=clk_multiple -1;
- end if;
- end if;
- end if;
- end process;
-
- addr_out <= addr;
- wren_out <= wren;
+ process (sys_rst_n, clk, hsync_ne, vsync)
+ begin
+ if sys_rst_n = '0' then
+ row_addr <= (others => '0');
+ addr <= (others => '0');
+ h_div <= 0;
+ h_active_counter <= 0;
+ h_fp_counter <= 0;
+ v_active_counter <= 0;
+ v_fp_counter <= 0;
+ elsif rising_edge(clk) then
+ if hsync_ne = '1' then
+ if vsync = '1' then
+ row_addr <= (others => '0');
+ v_fp_counter <= v_front_porch;
+ v_active_counter <= v_active;
+ elsif v_fp_counter /= 0 then
+ v_fp_counter <= v_fp_counter -1;
+ elsif v_active_counter /= 0 then
+ v_active_counter <= v_active_counter -1;
+
+ h_fp_counter <= h_front_porch * clk_multiple + phase;
+ h_active_counter <= h_active;
+ h_div <= 0;
+
+ addr <= row_addr;
+ row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
+ end if;
+ elsif h_fp_counter /= 0 then
+ h_fp_counter <= h_fp_counter -1;
+ elsif h_active_counter /= 0 then
+
+ if h_div = 0 then
+ wren <= '1';
+ h_div <= clk_multiple -1;
+ elsif h_div = clk_multiple -1 then
+ wren <= '0';
+ h_active_counter <= h_active_counter -1;
+ addr <= std_logic_vector(unsigned(addr)+h_stride);
+ h_div <= clk_multiple -1;
+ else
+ h_div <= clk_multiple -1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ addr_out <= addr;
+ wren_out <= wren;
end beh;
diff --git a/spartan6/hp_lcd_driver/output_formatter.vhdl b/spartan6/hp_lcd_driver/output_formatter.vhdl
index 4969b8a..32e16c0 100644
--- a/spartan6/hp_lcd_driver/output_formatter.vhdl
+++ b/spartan6/hp_lcd_driver/output_formatter.vhdl
@@ -53,8 +53,8 @@ begin
port map(
clk => clk,
sig => vsync_in,
- e => open,
- pe => open,
+ e => open,
+ pe => open,
ne => vsync_in_ne);
process (clk, vsync_in_ne, sys_rst_n)
diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl
index 0c75b3d..49b7679 100644
--- a/spartan6/hp_lcd_driver/output_stage.vhdl
+++ b/spartan6/hp_lcd_driver/output_stage.vhdl
@@ -7,8 +7,8 @@ use UNISIM.vcomponents.all;
entity output_stage is
- generic (target : string := "spartan6";
- debounce_stages : natural := 2;
+ generic (target : string := "spartan6";
+ debounce_stages : natural := 2;
sync_stages : natural := 2;
addr_width : natural := 17;
h_front_porch : natural := 208;
@@ -25,11 +25,11 @@ entity output_stage is
);
port
(
- clk_locked : in std_logic;
- clk : in std_logic;
- clk_x2 : in std_logic;
- clk_x10 : in std_logic;
- sys_rst_n : in std_logic;
+ clk_locked : in std_logic;
+ clk : in std_logic;
+ clk_x2 : in std_logic;
+ clk_x10 : in std_logic;
+ sys_rst_n : in std_logic;
vsync_in : in std_logic;
@@ -72,10 +72,10 @@ architecture beh of output_stage is
signal addr : std_logic_vector(addr_width - 1 downto 0);
- signal r_p10 :std_logic_vector(9 downto 0);
- signal g_p10 :std_logic_vector(9 downto 0);
- signal b_p10 :std_logic_vector(9 downto 0);
- signal c_p10 :std_logic_vector(9 downto 0);
+ signal r_p10 : std_logic_vector(9 downto 0);
+ signal g_p10 : std_logic_vector(9 downto 0);
+ signal b_p10 : std_logic_vector(9 downto 0);
+ signal c_p10 : std_logic_vector(9 downto 0);
begin
@@ -145,38 +145,38 @@ begin
);
-tmds_e : entity work.tmds_encode port map (
- sys_rst_n => sys_rst_n,
- pclk => clk,
+ tmds_e : entity work.tmds_encode port map (
+ sys_rst_n => sys_rst_n,
+ pclk => clk,
- r_in => r_in,
- g_in => g_in,
- b_in => b_in,
- hsync => hsync,
- vsync => vsync,
- blank => blank,
+ r_in => r_in,
+ g_in => g_in,
+ b_in => b_in,
+ hsync => hsync,
+ vsync => vsync,
+ blank => blank,
- r_p10 => r_p10,
- g_p10 => g_p10,
- b_p10 => b_p10,
- c_p10 => c_p10
+ r_p10 => r_p10,
+ g_p10 => g_p10,
+ b_p10 => b_p10,
+ c_p10 => c_p10
- );
+ );
tmds_o : entity work.tmds_output_spartan6
port map (
- sys_rst_n => sys_rst_n,
- pclk_locked => clk_locked,
- pclk => clk,
- pclk_x2 => clk_x2,
- pclk_x10 => clk_x10,
-
- r_p10 => r_p10,
- g_p10 => g_p10,
- b_p10 => b_p10,
- c_p10 => c_p10,
+ sys_rst_n => sys_rst_n,
+ pclk_locked => clk_locked,
+ pclk => clk,
+ pclk_x2 => clk_x2,
+ pclk_x10 => clk_x10,
+
+ r_p10 => r_p10,
+ g_p10 => g_p10,
+ b_p10 => b_p10,
+ c_p10 => c_p10,
tmds_c_out_p => hdmi_c_p,
tmds_c_out_n => hdmi_c_n,
diff --git a/spartan6/hp_lcd_driver/tmds_encode.vhdl b/spartan6/hp_lcd_driver/tmds_encode.vhdl
index d302960..fe69a56 100644
--- a/spartan6/hp_lcd_driver/tmds_encode.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_encode.vhdl
@@ -5,32 +5,32 @@ use IEEE.NUMERIC_STD.all;
entity tmds_encode is
port (
- sys_rst_n : in std_logic;
- pclk : in std_logic;
+ sys_rst_n : in std_logic;
+ pclk : in std_logic;
- r_in : in std_logic_vector(7 downto 0);
- g_in : in std_logic_vector(7 downto 0);
- b_in : in std_logic_vector(7 downto 0);
- hsync : in std_logic;
- vsync : in std_logic;
- blank : in std_logic;
+ r_in : in std_logic_vector(7 downto 0);
+ g_in : in std_logic_vector(7 downto 0);
+ b_in : in std_logic_vector(7 downto 0);
+ hsync : in std_logic;
+ vsync : in std_logic;
+ blank : in std_logic;
- r_p10 : out std_logic_vector(9 downto 0);
- g_p10 : out std_logic_vector(9 downto 0);
- b_p10 : out std_logic_vector(9 downto 0);
- c_p10 : out std_logic_vector(9 downto 0)
+ r_p10 : out std_logic_vector(9 downto 0);
+ g_p10 : out std_logic_vector(9 downto 0);
+ b_p10 : out std_logic_vector(9 downto 0);
+ c_p10 : out std_logic_vector(9 downto 0)
);
end tmds_encode;
architecture beh of tmds_encode is
- signal ctrl : std_logic_vector(1 downto 0);
+ signal ctrl : std_logic_vector(1 downto 0);
begin
-c_p10 <= "1111100000";
+ c_p10 <= "1111100000";
ctrl <= vsync & hsync;
diff --git a/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl b/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl
index 3212998..fc0aba2 100644
--- a/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl
@@ -8,16 +8,16 @@ use UNISIM.vcomponents.all;
entity tmds_output_spartan6 is
port (
- sys_rst_n : in std_logic;
- pclk_locked : in std_logic;
- pclk : in std_logic;
- pclk_x2 : in std_logic;
- pclk_x10 : in std_logic;
+ sys_rst_n : in std_logic;
+ pclk_locked : in std_logic;
+ pclk : in std_logic;
+ pclk_x2 : in std_logic;
+ pclk_x10 : in std_logic;
- r_p10 : in std_logic_vector(9 downto 0);
- g_p10 : in std_logic_vector(9 downto 0);
- b_p10 : in std_logic_vector(9 downto 0);
- c_p10 : in std_logic_vector(9 downto 0);
+ r_p10 : in std_logic_vector(9 downto 0);
+ g_p10 : in std_logic_vector(9 downto 0);
+ b_p10 : in std_logic_vector(9 downto 0);
+ c_p10 : in std_logic_vector(9 downto 0);
tmds_c_out_p : out std_logic;
@@ -35,16 +35,16 @@ end tmds_output_spartan6;
architecture beh of tmds_output_spartan6 is
- signal phy_reset : std_logic;
- signal upper : std_logic;
- signal pll_locked: std_logic;
- signal ioclk: std_logic;
- signal serdesstrobe : std_logic;
+ signal phy_reset : std_logic;
+ signal upper : std_logic;
+ signal pll_locked : std_logic;
+ signal ioclk : std_logic;
+ signal serdesstrobe : std_logic;
begin
phy_reset <= not sys_rst_n or not pll_locked;
- process (pclk_x2,phy_reset)
+ process (pclk_x2, phy_reset)
begin
if phy_reset = '1' then
upper <= '1';
diff --git a/spartan6/hp_lcd_driver/tmds_phy.vhdl b/spartan6/hp_lcd_driver/tmds_phy.vhdl
index ece67e6..9b31e58 100644
--- a/spartan6/hp_lcd_driver/tmds_phy.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_phy.vhdl
@@ -58,8 +58,8 @@ begin
obuf : OBUFDS
generic map (IOSTANDARD => "TMDS_33")
port map (
- I =>s,
- O =>tmds_out_p,
+ I => s,
+ O => tmds_out_p,
OB => tmds_out_n
);
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-24 21:47:45 +0000