diff options
28 files changed, 0 insertions, 2304 deletions
diff --git a/fpga/hp_lcd_driver_a7/.gitignore b/fpga/hp_lcd_driver_a7/.gitignore deleted file mode 100644 index 7594c18..0000000 --- a/fpga/hp_lcd_driver_a7/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -build-rando_a7 -NOT -OLD_NOT diff --git a/fpga/hp_lcd_driver_a7/Makefile b/fpga/hp_lcd_driver_a7/Makefile deleted file mode 100644 index aa94c04..0000000 --- a/fpga/hp_lcd_driver_a7/Makefile +++ /dev/null @@ -1,104 +0,0 @@ -# -#RH=10.16.66.168 -RH=10.16.66.111 -#RH=10.16.66.96 -#RH=hagelin - -RD=$(shell pwd) - -ifeq (${BOARD},) -BOARD:=rando_a7 -endif - -BUILD=build-${BOARD} - -IP= \ - artix7_ip/blk_mem_gen_0.tcl \ - artix7_ip/mmcm_0.tcl \ - artix7_ip/mmcm_1.tcl - - -BIT=${BUILD}/out/hp_lcd_driver.bit - -IP_STAMP=${IP:artix7_ip/%.tcl=${BUILD}/ip/%/stamp} -SRCS= ${IP} \ - artix7_config.tcl \ - artix7_hp_lcd_driver.tcl \ - rando_a7.tcl \ - rando_a7.xdc \ - clkgen_artix7.vhdl \ - debounce.vhdl \ - delay.vhdl \ - edge_det.vhdl \ - hp_lcd_driver.vhdl \ - input_formatter.vhdl \ - input_stage.vhdl \ - output_analog.vhdl \ - output_formatter.vhdl \ - output_stage.vhdl \ - synchronizer.vhdl \ - tmds_encoder.vhdl \ - tmds_encode.vhdl \ - tmds_output_artix7.vhdl \ - tmds_phy_artix7.vhdl \ - vram_artix7.vhdl - - - -OPENOCD=openocd -f openocd/${BOARD}.cfg - -default: ${BUILD}/build.stamp - -${BUILD}/build.stamp:${SRCS} ${IP_STAMP} - mkdir -p ${BUILD} - (cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../artix7_hp_lcd_driver.tcl) - touch $@ - -${BUILD}/ip/%/stamp:artix7_ip/%.tcl - mkdir -p ${BUILD}/ip - /bin/rm -rf $(dir $@) - (cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../$<) && touch $@ - - -clean: - /bin/rm -rf build-* - - -${BIT}: ${BUILD}/build.stamp - -load: ${BUILD}/out/hp_lcd_driver.bit - ${OPENOCD} -c "init; pld load 0 {${BIT}}; exit" - - - -#flash: build/out/tpm_widget.bit -# openocd -f openocd/ft4232.cfg -f openocd/xc7k325t.cfg -c "init; fpga_flash {$<}; exit" - -rload: ${BUILD}/build.${RH}.synced - ssh "${RH}" "cd ${RD} && make BOARD=${BOARD} load" - -${BUILD}/build.${RH}.synced: ${BUILD}/build.stamp - ssh "${RH}" "mkdir -p '${RD}/${BUILD}/out/'" - rsync -varz ${BUILD}/out/ "${RH}:${RD}/${BUILD}/out/" - ssh "${RH}" "cd '${RD}' && touch $<" - touch $@ - -rsync-build: - ssh "${RH}" "mkdir -p ${RD}" - rsync -varz ./${BUILD}/ "${RH}:${RD}/${BUILD}/" -rsync-git: - ssh "${RH}" "mkdir -p ${RD}" - rsync -varz ./.git/ "${RH}:${RD}/.git/" - -rsync-all: - ssh "${RH}" "mkdir -p ${RD}" - rsync -varz ./ "${RH}:${RD}/" - -tidy: - #git diff --exit-code -s source - for i in source/*.vhdl; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done - - - - - diff --git a/fpga/hp_lcd_driver_a7/artix7_config.tcl b/fpga/hp_lcd_driver_a7/artix7_config.tcl deleted file mode 100644 index 65628b6..0000000 --- a/fpga/hp_lcd_driver_a7/artix7_config.tcl +++ /dev/null @@ -1,26 +0,0 @@ -# -set board $::env(BOARD) -set board_tcl $source_dir/$board.tcl -set build_dir . -set ip_dir $build_dir/ip -set bd_dir $build_dir/bd -set ipl_dir $build_dir/ip_library -set output_dir $build_dir/out -source $board_tcl -create_project -in_memory -part $part_num - -file mkdir $build_dir -file mkdir $bd_dir -file mkdir $ip_dir -file mkdir $ipl_dir -file mkdir $output_dir - -#WARNING: [Vivado 12-13651] The IP file '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0/mmcm_0.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. -set_msg_config -id 12-13651 -suppress - - - -#WARNING: [Synth 8-3848] Net dma_axi_awid in module/entity pcie_tpm_widget does not have driver. [/root/projects/tpm_interposer/logic_analyzer/source/pcie_tpm_widget.vhdl:88] -#set_msg_config -id 8-3848 -new_severity ERROR - - diff --git a/fpga/hp_lcd_driver_a7/artix7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver_a7/artix7_hp_lcd_driver.tcl deleted file mode 100644 index 684e493..0000000 --- a/fpga/hp_lcd_driver_a7/artix7_hp_lcd_driver.tcl +++ /dev/null @@ -1,85 +0,0 @@ -# -set source_dir [file dirname [file normalize [info script]]] - -source $source_dir/artix7_config.tcl - -file mkdir $output_dir - -set files [glob -nocomplain "$output_dir/*"] -if {[llength $files] != 0} { - # clear folder contents - puts "deleting contents of $output_dir" - file delete -force {*}[glob -directory $output_dir *]; -} else { - puts "$output_dir is empty" -} - -#Reference HDL and constraint source files - -#read_xdc $early_xdc - -#read_verilog [ glob ../source/*.v ] -#read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ] -read_vhdl -vhdl2008 -library work { ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../hp_lcd_driver.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl } - -set generics {} -append generics { } "video_width=$video_width" -append generics { } "BOARD=\"$board\"" -append generics { } "use_pclk=$use_pclk" - -set_property generic "$generics" [current_fileset] -puts $generics - -read_ip $ip_dir/blk_mem_gen_0/blk_mem_gen_0.xci -read_ip $ip_dir/mmcm_0/mmcm_0.xci -read_ip $ip_dir/mmcm_1/mmcm_1.xci - -read_xdc $normal_xdc - -#Run Synthesis -synth_design -top hp_lcd_driver -part $part_num -write_checkpoint -force $output_dir/post_synth.dcp -report_timing_summary -file $output_dir/post_synth_timing_summary.rpt -report_utilization -file $output_dir/post_synth_util.rpt - -set crdl [get_param tcl.collectionResultDisplayLimit] -set_param tcl.collectionResultDisplayLimit 10000000 - -set f [open "$output_dir/cells.txt" w] -puts $f [get_cells -hierarchical] -close $f - -set f [open "$output_dir/nets.txt" w] -puts $f [get_nets -hierarchical] -close $f -set_param tcl.collectionResultDisplayLimit $crdl - -set f [open "$output_dir/pins.txt" w] -puts $f [get_pins -hierarchical] -close $f -set_param tcl.collectionResultDisplayLimit $crdl - -#run optimization -opt_design -place_design -report_clock_utilization -file $output_dir/clock_util.rpt - -#get timing violations and run optimizations if needed -if {[get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] < 0} { - puts "Found setup timing violations => running physical optimization" - phys_opt_design -} -write_checkpoint -force $output_dir/post_place.dcp -report_utilization -file $output_dir/post_place_util.rpt -report_timing_summary -file $output_dir/post_place_timing_summary.rpt - -#Route design and generate bitstream -route_design -directive Explore -write_checkpoint -force $output_dir/post_route.dcp -report_route_status -file $output_dir/post_route_status.rpt -report_timing_summary -file $output_dir/post_route_timing_summary.rpt -report_power -file $output_dir/post_route_power.rpt -report_drc -file $output_dir/post_imp_drc.rpt -report_io -file $output_dir/post_imp_placed.rpt -write_verilog -force $output_dir/cpu_impl_netlist.v -mode timesim -sdf_anno true -write_bitstream -force $output_dir/hp_lcd_driver.bit diff --git a/fpga/hp_lcd_driver_a7/artix7_ip/blk_mem_gen_0.tcl b/fpga/hp_lcd_driver_a7/artix7_ip/blk_mem_gen_0.tcl deleted file mode 100644 index 84626aa..0000000 --- a/fpga/hp_lcd_driver_a7/artix7_ip/blk_mem_gen_0.tcl +++ /dev/null @@ -1,33 +0,0 @@ - - -set source_dir [file dirname [file dirname [file normalize [info script]]]] - -source $source_dir/artix7_config.tcl - -create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name blk_mem_gen_0 -dir $ip_dir - -set_property -dict [list \ - CONFIG.Memory_Type {Simple_Dual_Port_RAM} \ - CONFIG.Enable_32bit_Address {false} \ - CONFIG.Use_Byte_Write_Enable {false} \ - CONFIG.Byte_Size {9} \ - CONFIG.Write_Width_A {6} \ - CONFIG.Write_Depth_A {245760} \ - CONFIG.Read_Width_A {6} \ - CONFIG.Operating_Mode_A {NO_CHANGE} \ - CONFIG.Write_Width_B {6} \ - CONFIG.Read_Width_B {6} \ - CONFIG.Enable_B {Use_ENB_Pin} \ - CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ - CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \ - CONFIG.Use_RSTB_Pin {false} \ - CONFIG.Port_B_Clock {22} \ - CONFIG.Port_B_Enable_Rate {22} \ - CONFIG.Disable_Collision_Warnings {false} \ - CONFIG.EN_SAFETY_CKT {false} \ - ] [get_ips blk_mem_gen_0] - -generate_target all [get_ips] - -synth_ip [get_ips] - diff --git a/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_0.tcl b/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_0.tcl deleted file mode 100644 index a49c8f2..0000000 --- a/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_0.tcl +++ /dev/null @@ -1,38 +0,0 @@ -set source_dir [file dirname [file dirname [file normalize [info script]]]] - -source $source_dir/artix7_config.tcl - -create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_0 -dir $ip_dir - -set_property -dict [list \ - CONFIG.PRIM_IN_FREQ {50} \ - CONFIG.CLKOUT2_USED {true} \ - CONFIG.CLKOUT3_USED {true} \ - CONFIG.CLKOUT4_USED {true} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {240} \ - CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {80} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {48} \ - CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {24} \ - CONFIG.CLKIN1_JITTER_PS {200.0} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \ - CONFIG.MMCM_CLKIN1_PERIOD {20.000} \ - CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \ - CONFIG.MMCM_CLKOUT1_DIVIDE {15} \ - CONFIG.MMCM_CLKOUT2_DIVIDE {25} \ - CONFIG.MMCM_CLKOUT3_DIVIDE {50} \ - CONFIG.NUM_OUT_CLKS {4} \ - CONFIG.CLKOUT1_JITTER {120.627} \ - CONFIG.CLKOUT1_PHASE_ERROR {154.678} \ - CONFIG.CLKOUT2_JITTER {146.190} \ - CONFIG.CLKOUT2_PHASE_ERROR {154.678} \ - CONFIG.CLKOUT3_JITTER {165.425} \ - CONFIG.CLKOUT3_PHASE_ERROR {154.678} \ - CONFIG.CLKOUT4_JITTER {202.151} \ - CONFIG.CLKOUT4_PHASE_ERROR {154.678} \ - ] [get_ips mmcm_0] - -generate_target all [get_ips] - -synth_ip [get_ips] - diff --git a/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_1.tcl b/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_1.tcl deleted file mode 100644 index eb2143d..0000000 --- a/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_1.tcl +++ /dev/null @@ -1,35 +0,0 @@ -set source_dir [file dirname [file dirname [file normalize [info script]]]] - -source $source_dir/artix7_config.tcl - -create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_1 -dir $ip_dir - -set_property -dict [list \ - CONFIG.PRIM_IN_FREQ {50} \ - CONFIG.CLKOUT2_USED {true} \ - CONFIG.CLKOUT3_USED {true} \ - CONFIG.CLKOUT4_USED {true} \ - CONFIG.CLKOUT5_USED {false} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {78.571} \ - CONFIG.USE_SAFE_CLOCK_STARTUP {false} \ - CONFIG.CLKIN1_JITTER_PS {100.0} \ - CONFIG.CLKOUT1_DRIVES {BUFG} \ - CONFIG.CLKOUT2_DRIVES {BUFG} \ - CONFIG.CLKOUT3_DRIVES {BUFG} \ - CONFIG.CLKOUT4_DRIVES {BUFG} \ - CONFIG.CLKOUT5_DRIVES {BUFG} \ - CONFIG.CLKOUT6_DRIVES {BUFG} \ - CONFIG.CLKOUT7_DRIVES {BUFG} \ - CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ - CONFIG.MMCM_DIVCLK_DIVIDE {1} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {11.000} \ - CONFIG.MMCM_CLKIN1_PERIOD {20.000} \ - CONFIG.MMCM_CLKIN2_PERIOD {20.000} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {7} \ - CONFIG.NUM_OUT_CLKS {1} \ - ] [get_ips mmcm_1] - -generate_target all [get_ips] - -synth_ip [get_ips] - diff --git a/fpga/hp_lcd_driver_a7/clkgen_artix7.vhdl b/fpga/hp_lcd_driver_a7/clkgen_artix7.vhdl deleted file mode 100644 index f7f8971..0000000 --- a/fpga/hp_lcd_driver_a7/clkgen_artix7.vhdl +++ /dev/null @@ -1,61 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; -use work.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity clkgen is - port ( - sys_rst_n : in std_logic; - clk_in : in std_logic; - i_clk : out std_logic; - o_clk : out std_logic; - o_clk_x2 : out std_logic; - o_clk_phy : out std_logic; - locked : out std_logic - ); -end clkgen; -architecture Behavioural of clkgen is - - signal clk_240m : std_logic; - signal clk_78_571m : std_logic; - signal clk_80m : std_logic; - signal clk_24m : std_logic; - signal clk_48m : std_logic; - signal clk_50m : std_logic; - - signal reset : std_logic; -begin - - reset <= not sys_rst_n; - - o_clk_buf : BUFG port map ( - I => clk_in, - O => clk_50m); - - - mmcm_0_i : mmcm_0 port map ( - clk_in1 => clk_50m, - clk_out1 => clk_240m, - clk_out2 => clk_80m, - clk_out3 => clk_48m, - clk_out4 => clk_24m, - reset => reset, - locked => locked - ); - - mmcm_1_i : mmcm_1 port map ( - clk_in1 => clk_50m, - clk_out1 => clk_78_571m, - reset => reset - ); - - o_clk_phy <= clk_240m; - o_clk <= clk_24m; - o_clk_x2 <= clk_48m; - i_clk <= clk_78_571m; - - -end Behavioural; diff --git a/fpga/hp_lcd_driver_a7/debounce.vhdl b/fpga/hp_lcd_driver_a7/debounce.vhdl deleted file mode 100644 index 286367d..0000000 --- a/fpga/hp_lcd_driver_a7/debounce.vhdl +++ /dev/null @@ -1,32 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -entity debounce is - generic (stages : natural := 1); - port (clk : in std_logic; - i : in std_logic; - o : out std_logic); -end debounce; - -architecture Behavioral of debounce is - signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); - constant zero : std_logic_vector(stages-1 downto 0) := (others => '0'); - constant one : std_logic_vector(stages-1 downto 0) := (others => '1'); - signal output : std_logic := '0'; -begin - - o <= output; - - process (clk, flipflops, i) - begin - if rising_edge(clk) then - flipflops <= flipflops(flipflops'high-1 downto 0) & i; - if flipflops = one and i = '1' then - output <= '1'; - elsif flipflops = zero and i = '0' then - output <= '0'; - end if; - end if; - end process; - -end architecture; diff --git a/fpga/hp_lcd_driver_a7/delay.vhdl b/fpga/hp_lcd_driver_a7/delay.vhdl deleted file mode 100644 index 66c5c5d..0000000 --- a/fpga/hp_lcd_driver_a7/delay.vhdl +++ /dev/null @@ -1,24 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -entity delay is - generic (stages : natural := 2); - port (clk : in std_logic; - i : in std_logic; - o : out std_logic); -end delay; - -architecture Behavioral of delay is - signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); -begin - - o <= flipflops(flipflops'high); - - clk_proc : process(clk, flipflops, i) - begin - if rising_edge(clk) then - flipflops <= flipflops(flipflops'high-1 downto 0) & i; - end if; - end process; - -end Behavioral; diff --git a/fpga/hp_lcd_driver_a7/edge_det.vhdl b/fpga/hp_lcd_driver_a7/edge_det.vhdl deleted file mode 100644 index 2a592a5..0000000 --- a/fpga/hp_lcd_driver_a7/edge_det.vhdl +++ /dev/null @@ -1,28 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -entity edge_det is - port (clk : in std_logic; - sig : in std_logic; - pe : out std_logic; - ne : out std_logic; - e : out std_logic - ); -end edge_det; - -architecture Behavioral of edge_det is - signal last : std_logic := '0'; -begin - - process(clk, last, sig) - begin - if rising_edge(clk) then - last <= sig; - end if; - end process; - - pe <= '1' when sig = '1' and last = '0' else '0'; - ne <= '1' when sig = '0' and last = '1' else '0'; - - e <= sig xor last; -end Behavioral; diff --git a/fpga/hp_lcd_driver_a7/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver_a7/hp_lcd_driver.vhdl deleted file mode 100644 index 755c422..0000000 --- a/fpga/hp_lcd_driver_a7/hp_lcd_driver.vhdl +++ /dev/null @@ -1,340 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; -use work.all; - --- on the cyclone iv --- i_clk/4 = 19.676158 --- the scope's pixel clock is 19.66080 --- (p-0.25)*19.66080 = p * 19.676158 ---p=1/[4*(1-(19.676158/19.66080))]=320.04 - - -entity hp_lcd_driver is - generic (video_width : natural := 2; - addr_width : natural := 18; - phase_slip : natural := 320; - i_clk_multiple : natural := 4; - use_pclk : natural := 0; - target : string := "artix7"); - port (clk_50m : in std_logic; --- sys_rst_n : in std_logic; - video : in std_logic_vector(video_width -1 downto 0); - hsync_in : in std_logic; - vsync_in : in std_logic; - pclk_in : in std_logic; - r_out : out std_logic; - b_out : out std_logic; - g_out : out std_logic; - hsync_out : out std_logic; - vsync_out : out std_logic; - hdmi_c_p : out std_logic; - hdmi_c_n : out std_logic; - hdmi_r_p : out std_logic; - hdmi_r_n : out std_logic; - hdmi_g_p : out std_logic; - hdmi_g_n : out std_logic; - hdmi_b_p : out std_logic; - hdmi_b_n : out std_logic; - hdmi_vcc : out std_logic; - i_clk_out : out std_logic; - led_0 : out std_logic; - led_1 : out std_logic); - -end hp_lcd_driver; - -architecture Behavioral of hp_lcd_driver is - - signal sys_rst_n : std_logic; - signal wr_addr : std_logic_vector(addr_width-1 downto 0); - signal wr_data : std_logic_vector(video_width-1 downto 0); - signal wr_en : std_logic; - - signal rd_addr : std_logic_vector(addr_width-1 downto 0); - signal rd_data : std_logic_vector(video_width-1 downto 0); - - signal r : std_logic_vector(7 downto 0); - signal g : std_logic_vector(7 downto 0); - signal b : std_logic_vector(7 downto 0); - - - signal clk_locked : std_logic; - - signal i_clk : std_logic; - - signal o_clk : std_logic; - signal o_clk_x2 : std_logic; - signal o_clk_phy : std_logic; - signal sys_rst : std_logic; - - signal pa : natural; - signal epk : std_logic; - signal ic : natural; - - - signal h : natural; - signal v : natural; - - - signal c : natural; - signal t : std_logic; - -begin - - - sys_rst_n <= '1'; - --- clocking: --- i_clk is 4*(nominal) 20MHz to give us 4 choices of sampling position --- o_clk is the output pixel clock --- o_clk_x2 is used by the spartan serdes --- o_clk_phy is used the the hdmi phy (cylone4 it's o_clk x5, spartan 6 it's o_clk x 10) - - clkgen : entity work.clkgen - port map ( - sys_rst_n => sys_rst_n, - clk_in => clk_50m, - i_clk => i_clk, - o_clk => o_clk, - o_clk_x2 => o_clk_x2, - o_clk_phy => o_clk_phy, - locked => clk_locked - ); - - - - process (i_clk, sys_rst_n) - begin - if sys_rst_n = '0' then - ic <= 0; - pa <= phase_slip; - epk <= '0'; - elsif rising_edge(i_clk) then - - if ic = 0 then - epk <= '1'; - if pa = 0 then - pa <= phase_slip; - ic <= i_clk_multiple; - else - ic <= i_clk_multiple-1; - pa <= pa -1; - end if; - else - if epk = '1' then - epk <= '0'; - end if; - ic <= ic-1; - end if; - end if; - end process; - - - i_clk_out <= epk; - - - input0 : entity work.input_stage - generic map( - video_width => video_width, - addr_width => addr_width, - clk_multiple => i_clk_multiple, --- HP54502A --- phase => 1, --- h_front_porch => 210, --- h_active => 592, --- v_front_porch => 1, --- v_active => 384, --- frame_start => 383, --- h_stride => 384, --- v_stride => 262143, --- HP54522A - phase => 1, - h_front_porch => 213, - h_active => 640, - v_front_porch => 22, - v_active => 384, - frame_start => 383, - h_stride => 384, - v_stride => 524287, - phase_slip => phase_slip, - use_pclk => use_pclk - ) - port map ( - sys_rst_n => sys_rst_n, - clk => i_clk, - video_in => video, - pclk_in => pclk_in, - hsync_in => not hsync_in, - vsync_in => not vsync_in, - - video_out => wr_data, - addr_out => wr_addr, - wren_out => wr_en - ); - --- --- process (i_clk) begin --- if sys_rst_n='0' then --- h<=0; --- v<=0; --- wr_addr <=(others =>'0'); --- elsif rising_edge(i_clk) then --- if h /= 383 then --- h<=h+1; --- wr_addr <= std_logic_vector(unsigned(wr_addr)+1); --- else --- h<=0; --- if v /= 591 then --- v<=v+1; --- wr_addr <= std_logic_vector(unsigned(wr_addr)+1); --- else --- v<=0; --- wr_addr <=(others =>'0'); --- end if; --- end if; --- end if; --- end process; --- --- wr_en <= '1'; --- --- wr_data <="01" when (h=0) or (h=383) or (v=0) or (v=591) --- else "00"; --- - vram0 : entity work.vram - generic map ( - video_width => video_width, - addr_width => addr_width - ) - port map ( - wr_clk => i_clk, - wr_en => wr_en, - wr_addr => wr_addr, - wr_data => wr_data, - rd_clk => o_clk, - rd_addr => rd_addr, - rd_data => rd_data - ); - - - --- r<=x"00"; --- b<=x"00"; - - r <= rd_data(1 downto 0) & "000000"; - g <= rd_data(3 downto 2) & "000000"; - b <= rd_data(5 downto 4) & "000000"; - ---"ff" when rd_data(1) = '1' else --- x"80" when rd_data(0) = '1' else --- ix"00"; - - - - - output0 : entity work.output_stage - --- didn't work for me from this thing, only from mac, works at 60Hz xrandr --newmode "$M" 18.24 384 400 440 600 592 593 596 613 -HSync +Vsync --- Modeline "384x592_80.00" 25.40 384 408 448 512 592 593 596 620 -HSync +Vsync - - generic map ( - target => target, - addr_width => addr_width, --- h_active => 384, --- h_sync_start => 400, --- h_sync_end => 440, --- h_total => 640, --- v_active => 592, --- v_sync_start => 593, --- v_sync_end => 596, --- v_total => 613, --- h_stride => 1, --- v_stride => 384 - --- HP54502A --- h_active => 384, --- h_sync_start => 400, --- h_sync_end => 440, --- h_total => 660, --- v_active => 592, --- v_sync_start => 593, --- v_sync_end => 596, --- v_total => 613, --- h_stride => 1, --- v_stride => 384 - --- HP54522A - h_active => 384, - h_sync_start => 400, - h_sync_end => 440, - h_total => 660, --- h_active => 417, --- h_sync_start => 440, --- h_sync_end => 480, --- h_total => 660, - v_active => 640, - v_sync_start => 641, - v_sync_end => 644, - v_total => 650, - h_stride => 1, - v_stride => 384 - --- h_active => 640, --- h_sync_start=>656, --- h_sync_end =>752, --- h_total=>800, --- --- v_active =>480, --- v_sync_start=>490, --- v_sync_end=>492, --- v_total=>525, --- h_stride=>1, --- v_stride=>384 - - ) - - port map( - clk_locked => clk_locked, - clk => o_clk, - clk_x2 => o_clk_x2, - clk_phy => o_clk_phy, - sys_rst_n => sys_rst_n, - vsync_in => vsync_in, - r_in => r, - g_in => g, - b_in => b, - addr_out => rd_addr, - r_out => r_out, - g_out => g_out, - b_out => b_out, - hsync_out => hsync_out, - vsync_out => vsync_out, - hdmi_c_p => hdmi_c_p, - hdmi_c_n => hdmi_c_n, - hdmi_r_p => hdmi_r_p, - hdmi_r_n => hdmi_r_n, - hdmi_g_p => hdmi_g_p, - hdmi_g_n => hdmi_g_n, - hdmi_b_p => hdmi_b_p, - hdmi_b_n => hdmi_b_n - ); - - process (clk_50m, c) - begin - if rising_edge(clk_50m) then - - if c < 19999999 then - c <=c+1; - else - c <=0; - t <=not t; - end if; - end if; - end process; - - - led_0 <= t; - led_1 <= not t; - - -end Behavioral; - diff --git a/fpga/hp_lcd_driver_a7/input_formatter.vhdl b/fpga/hp_lcd_driver_a7/input_formatter.vhdl deleted file mode 100644 index 35916f5..0000000 --- a/fpga/hp_lcd_driver_a7/input_formatter.vhdl +++ /dev/null @@ -1,157 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - - - -entity input_formatter is - generic ( - addr_width : natural := 17; - clk_multiple : natural := 4; - phase : natural := 2; - h_front_porch : natural := 208; - h_active : natural := 592; - v_front_porch : natural := 2; - v_active : natural := 384; - frame_start : natural := 0; - h_stride : natural := 384; - v_stride : natural := 1; - phase_slip : natural := 320; - use_pclk : natural := 0 - ); - port - ( - sys_rst_n : in std_logic; - clk : in std_logic; - hsync : in std_logic; - vsync : in std_logic; - pclk : in std_logic; - addr_out : out std_logic_vector(addr_width-1 downto 0); - wren_out : out std_logic; - h_grid : out std_logic; - v_grid : out std_logic - ); - -end input_formatter; - - -architecture beh of input_formatter is - - signal row_addr : std_logic_vector(addr_width-1 downto 0); - signal addr : std_logic_vector(addr_width-1 downto 0); - signal wren : std_logic; - - signal pclk_ne : std_logic; - signal pclk_pe : std_logic; - - signal hsync_ne : std_logic; - signal hsync_pe : std_logic; - - signal v_fp_counter : natural; - signal v_active_counter : natural; - signal h_fp_counter : natural; - signal h_active_counter : natural; - - signal h_div : natural; - signal phase_accum : natural; - - -begin - - - hsync_ed : entity work.edge_det - port map( - clk => clk, - sig => hsync, - e => open, - ne => hsync_ne, - pe => hsync_pe); - - - pclk_ed : entity work.edge_det - port map( - clk => clk, - sig => pclk, - e => pclk_ne, - pe => pclk_pe); - - - - - addr_out <= addr; - - - process (sys_rst_n, clk, hsync_pe, vsync) - begin - if sys_rst_n = '0' then - row_addr <= (others => '0'); - addr <= (others => '0'); - h_div <= 0; - h_active_counter <= 0; - h_fp_counter <= 0; - v_active_counter <= 0; - v_fp_counter <= 0; - phase_accum <= phase_slip; - elsif rising_edge(clk) then - if hsync_pe = '1' then - --if v_active_counter = 0 and v_fp_counter=0 then - if vsync = '1' then - row_addr <= std_logic_vector(to_unsigned(frame_start, addr_width)); - v_fp_counter <= v_front_porch; - v_active_counter <= v_active; - elsif v_fp_counter /= 0 then - v_fp_counter <= v_fp_counter -1; - elsif v_active_counter /= 0 then - v_active_counter <= v_active_counter -1; - - h_fp_counter <= h_front_porch * clk_multiple + phase; - h_active_counter <= h_active; - phase_accum <= phase_slip; - h_div <= 0; - - addr <= row_addr; - row_addr <= std_logic_vector(unsigned(row_addr)+v_stride); - end if; - elsif h_fp_counter /= 0 then - h_fp_counter <= h_fp_counter -1; - elsif h_active_counter /= 0 then - - if use_pclk = 0 then - if h_div = 0 then - wren <= '1'; - if phase_accum = 0 then - phase_accum <= phase_slip; - h_div <= clk_multiple; - else - phase_accum <= phase_accum-1; - h_div <= clk_multiple-1; - end if; - else - h_div <= h_div -1; - wren <= '0'; - end if; - else - wren <= pclk_pe; - end if; - - if wren = '1' then - h_active_counter <= h_active_counter -1; - addr <= std_logic_vector(unsigned(addr)+h_stride); - end if; - end if; - end if; - end process; - - addr_out <= addr; - wren_out <= wren; - - - h_grid <= '1' when ((h_active_counter mod 16) = (h_active mod 16)) or (h_Active_counter = 1) --- h_grid <= '1' when (h_active_counter=h_active) or (h_active_counter=h_active-2) -else '0'; - - v_grid <= '1' when ((v_active_counter mod 16) = (v_active mod 16)) or (v_active_counter = 1) - else '0'; - - -end beh; diff --git a/fpga/hp_lcd_driver_a7/input_stage.vhdl b/fpga/hp_lcd_driver_a7/input_stage.vhdl deleted file mode 100644 index c124a59..0000000 --- a/fpga/hp_lcd_driver_a7/input_stage.vhdl +++ /dev/null @@ -1,165 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - -entity input_stage is - generic (debounce_stages : natural := 2; - sync_stages : natural := 2; - video_width : natural := 2; - addr_width : natural := 17; - clk_multiple : natural := 4; - phase : natural := 2; - h_front_porch : natural := 208; - h_active : natural := 592; - v_front_porch : natural := 2; - v_active : natural := 384; - frame_start : natural := 0; - h_stride : natural := 384; - v_stride : natural := 1; - phase_slip : natural := 320; - use_pclk : natural := 0); - port - ( - clk : in std_logic; - sys_rst_n : in std_logic; - - video_in : in std_logic_vector(video_width -1 downto 0); - - pclk_in : in std_logic; - hsync_in : in std_logic; - vsync_in : in std_logic; - - video_out : out std_logic_vector(video_width-1 downto 0); - addr_out : out std_logic_vector(addr_width - 1 downto 0); - wren_out : out std_logic - ); -end input_stage; - - -architecture beh of input_stage is - - signal s_pclk : std_logic; - signal d_pclk : std_logic; - - signal s_hsync : std_logic; - signal d_hsync : std_logic; - - signal s_vsync : std_logic; - signal d_vsync : std_logic; - - signal s_video : std_logic_vector(video_width-1 downto 0); - - signal addr : std_logic_vector(addr_width - 1 downto 0); - signal wren : std_logic; - - signal h_grid : std_logic; - signal v_grid : std_logic; - - signal addr_test : std_logic_vector(addr_width - 1 downto 0); - -begin - - video_sync_for : for b in 0 to video_width -1 generate - sync : entity work.synchronizer - generic map(stages => sync_stages + debounce_stages +1) - port map ( - clk => clk, - i => video_in(b), - o => s_video(b) - ); - end generate; - - - pclk_sync : entity work.synchronizer - generic map(stages => sync_stages) - port map ( - clk => clk, - i => pclk_in, - o => s_pclk - ); - - hsync_sync : entity work.synchronizer - generic map(stages => sync_stages) - port map ( - clk => clk, - i => hsync_in, - o => s_hsync - ); - - vsync_sync : entity work.synchronizer - generic map(stages => sync_stages) - port map ( - clk => clk, - i => vsync_in, - o => s_vsync - ); - - - pclk_debounce : entity work.debounce - generic map(stages => debounce_stages) - port map( - clk => clk, - i => s_pclk, - o => d_pclk); - - hsync_debounce : entity work.debounce - generic map(stages => debounce_stages) - port map( - clk => clk, - i => s_hsync, - o => d_hsync); - - vsync_debounce : entity work.debounce - generic map(stages => debounce_stages) - port map( - clk => clk, - i => s_vsync, - o => d_vsync); - - - input_formatter : entity work.input_formatter - generic map( - -- 20.000 592 608 680 816 384 385 400 402 - addr_width => addr_width, - clk_multiple => clk_multiple, - phase => phase, - h_front_porch => h_front_porch, - h_active => h_active, - v_front_porch => v_front_porch, - v_active => v_active, - frame_start => frame_start, - h_stride => h_stride, - v_stride => v_stride, - phase_slip => phase_slip, - use_pclk => use_pclk) - port map ( - sys_rst_n => sys_rst_n, - clk => clk, - pclk => d_pclk, - hsync => d_hsync, - vsync => d_vsync, - addr_out => addr, - wren_out => wren, - h_grid => h_grid, - v_grid => v_grid - ); - - ---wren_out <='1'; - ---video_out(0) <='1'; ---video_out(1) <='1'; - - addr_out <= addr; - wren_out <= wren; - - video_out <= s_video; - ---video_out(0) <= s_video(0); ---video_out(1) <= h_grid or v_grid; - - --video_out(0) <= h_grid; - --video_out(1) <= v_grid; - - -end beh; diff --git a/fpga/hp_lcd_driver_a7/output_analog.vhdl b/fpga/hp_lcd_driver_a7/output_analog.vhdl deleted file mode 100644 index af9eb71..0000000 --- a/fpga/hp_lcd_driver_a7/output_analog.vhdl +++ /dev/null @@ -1,82 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - - -entity output_analog is - port - ( - clk : in std_logic; - sys_rst_n : in std_logic; - - r_in : in std_logic; - g_in : in std_logic; - b_in : in std_logic; - hsync_in : in std_logic; - vsync_in : in std_logic; - blank_in : in std_logic; - - r_out : out std_logic; - g_out : out std_logic; - b_out : out std_logic; - hsync_out : out std_logic; - vsync_out : out std_logic - ); -end output_analog; - - -architecture beh of output_analog is - - - signal r_r : std_logic; - signal g_r : std_logic; - signal b_r : std_logic; - - signal hsync_r : std_logic; - signal vsync_r : std_logic; - signal blank_r : std_logic; - - - -begin - - process (sys_rst_n, clk) - begin - if sys_rst_n = '0' then - r_r <= '0'; - g_r <= '0'; - b_r <= '0'; - hsync_r <= '0'; - vsync_r <= '0'; - blank_r <= '0'; - elsif rising_edge(clk) then - r_r <= r_in; - g_r <= g_in; - b_r <= b_in; - hsync_r <= hsync_in; - vsync_r <= vsync_in; - blank_r <= blank_in; - - end if; - end process; - - - process (sys_rst_n, clk) - begin - if sys_rst_n = '0' then - r_out <= '0'; - g_out <= '0'; - b_out <= '0'; - hsync_out <= '0'; - vsync_out <= '0'; - elsif rising_edge(clk) then - r_out <= r_r and not blank_r; - g_out <= g_r and not blank_r; - b_out <= b_r and not blank_r; - hsync_out <= hsync_r; - vsync_out <= vsync_r; - end if; - end process; - - -end beh; diff --git a/fpga/hp_lcd_driver_a7/output_formatter.vhdl b/fpga/hp_lcd_driver_a7/output_formatter.vhdl deleted file mode 100644 index 558c222..0000000 --- a/fpga/hp_lcd_driver_a7/output_formatter.vhdl +++ /dev/null @@ -1,142 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - - - -entity output_formatter is - generic (addr_width : natural := 17; - h_front_porch : natural := 208; - h_active : natural := 384; - h_sync_start : natural := 400; - h_sync_end : natural := 440; - h_total : natural := 600; - v_active : natural := 592; - v_sync_start : natural := 593; - v_sync_end : natural := 596; - v_total : natural := 614; - h_stride : natural := 1; - v_stride : natural := 384 - ); - port ( - sys_rst_n : in std_logic; - clk : in std_logic; - vsync_in : in std_logic; - addr_out : out std_logic_vector(addr_width -1 downto 0); - blank_out : out std_logic; - vsync_out : out std_logic; - hsync_out : out std_logic; - h_grid : out std_logic; - v_grid : out std_logic - ); -end output_formatter; - - -architecture beh of output_formatter is - - signal row_addr : std_logic_vector(addr_width-1 downto 0); - signal addr : std_logic_vector(addr_width-1 downto 0); - - signal vsync_in_ne : std_logic; - - signal h : natural; - signal v : natural; - - - signal blank : std_logic; - signal vblank : std_logic; - signal vsync : std_logic; - signal hsync : std_logic; - - -begin - - vsync_ed : entity work.edge_det - port map( - clk => clk, - sig => vsync_in, - e => open, - pe => open, - ne => vsync_in_ne); - - process (clk, vsync_in_ne, sys_rst_n) - begin - if sys_rst_n = '0' then - h <= 0; - v <= 0; - elsif rising_edge(clk) then - if h /= (h_total-1) then - h <= h+1; - else - if v /= (v_total-1) then - v <= v+1; - h <= 0; - else --if vsync_in_ne = '1' then - h <= 0; - v <= 0; - end if; - end if; - end if; - end process; - - - process (clk, h, h, sys_rst_n) - begin - if sys_rst_n = '0' then - row_addr <= (others => '0'); - addr <= (others => '0'); - blank <= '1'; - vblank <= '1'; - vsync <= '0'; - hsync <= '0'; - elsif rising_edge(clk) then - - if h = 0 then - if v = 0 then - --row_addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length)); - row_addr <= std_logic_vector(to_unsigned(v_stride, row_addr'length)); - --addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length)); - addr <= (others => '0'); - blank <= '0'; - vblank <= '0'; - elsif v = v_active then - vblank <= '1'; - elsif v = v_sync_start then - vsync <= '1'; - elsif v = v_sync_end then - vsync <= '0'; - else - blank <= vblank; - row_addr <= std_logic_vector(unsigned(row_addr)+v_stride); - addr <= row_addr; - end if; - elsif h = h_active then - blank <= '1'; - elsif h = h_sync_start then - hsync <= '1'; - elsif h = h_sync_end then - hsync <= '0'; - else - addr <= std_logic_vector(unsigned(addr)+h_stride); - end if; - end if; - end process; - - h_grid <= '1' when (h mod 32) = 0 --- h_grid <= '1' when (h = 0) or (h = (h_active-1)) -else '0'; - - v_grid <= '1' when (v mod 32) = 0 --- v_grid <= '1' when (v = 0) or (v = (v_active-1)) -else '0'; - - - addr_out <= addr; - blank_out <= blank; - hsync_out <= hsync; - vsync_out <= vsync; - -end beh; - - - diff --git a/fpga/hp_lcd_driver_a7/output_stage.vhdl b/fpga/hp_lcd_driver_a7/output_stage.vhdl deleted file mode 100644 index 56f4ae4..0000000 --- a/fpga/hp_lcd_driver_a7/output_stage.vhdl +++ /dev/null @@ -1,258 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - -entity output_stage is - generic (target : string := "spartan6"; - debounce_stages : natural := 2; - sync_stages : natural := 2; - addr_width : natural := 17; - h_front_porch : natural := 208; - h_active : natural := 384; - h_sync_start : natural := 400; - h_sync_end : natural := 440; - h_total : natural := 600; - v_active : natural := 592; - v_sync_start : natural := 593; - v_sync_end : natural := 596; - v_total : natural := 614; - h_stride : natural := 1; - v_stride : natural := 384 - ); - port - ( - clk_locked : in std_logic; - clk : in std_logic; - clk_x2 : in std_logic; - clk_phy : in std_logic; - sys_rst_n : in std_logic; - - vsync_in : in std_logic; - - addr_out : out std_logic_vector(addr_width - 1 downto 0); - - r_in : in std_logic_vector(7 downto 0); - g_in : in std_logic_vector(7 downto 0); - b_in : in std_logic_vector(7 downto 0); - - - r_out : out std_logic; - g_out : out std_logic; - b_out : out std_logic; - hsync_out : out std_logic; - vsync_out : out std_logic; - - hdmi_c_p : out std_logic; - hdmi_c_n : out std_logic; - hdmi_r_p : out std_logic; - hdmi_r_n : out std_logic; - hdmi_g_p : out std_logic; - hdmi_g_n : out std_logic; - hdmi_b_p : out std_logic; - hdmi_b_n : out std_logic - ); -end output_stage; - - -architecture beh of output_stage is - - - signal s_vsync_in : std_logic; - signal d_vsync_in : std_logic; - - signal blank : std_logic; - signal hsync : std_logic; - signal vsync : std_logic; - - signal blank_d : std_logic; - signal hsync_d : std_logic; - signal vsync_d : std_logic; - signal grid_d : std_logic; - - signal addr : std_logic_vector(addr_width - 1 downto 0); - - signal r : std_logic_vector(7 downto 0); - signal g : std_logic_vector(7 downto 0); - signal b : std_logic_vector(7 downto 0); - - signal h_grid : std_logic; - signal v_grid : std_logic; - - signal r_p10 : std_logic_vector(9 downto 0); - signal g_p10 : std_logic_vector(9 downto 0); - signal b_p10 : std_logic_vector(9 downto 0); - signal c_p10 : std_logic_vector(9 downto 0); - - -begin - - - vsync_sync : entity work.synchronizer - generic map(stages => sync_stages) - port map ( - clk => clk, - i => vsync_in, - o => s_vsync_in - ); - - vsync_debounce : entity work.debounce - generic map(stages => debounce_stages) - port map( - clk => clk, - i => s_vsync_in, - o => d_vsync_in); - - - output_formatter : entity work.output_formatter - generic map( - addr_width => addr_width, - h_active => h_active, - h_sync_start => h_sync_start, - h_sync_end => h_sync_end, - h_total => h_total, - v_active => v_active, - v_sync_start => v_sync_start, - v_sync_end => v_sync_end, - v_total => v_total, - h_stride => h_stride, - v_stride => v_stride - ) - port map ( - sys_rst_n => sys_rst_n, - clk => clk, - vsync_in => d_vsync_in, - addr_out => addr, - blank_out => blank, - vsync_out => vsync, - hsync_out => hsync, - h_grid => h_grid, - v_grid => v_grid - ); - - - addr_out <= addr; - --- dg : entity work.delay --- generic map(stages => 1) --- port map ( --- clk => clk, --- i => h_grid or v_grid, --- o => grid_d --- ); - - r <= r_in; - g <= g_in; - b <= b_in; - - - --- b<=x"00" when v_grid='0' --- else x"ff"; - --- r<=x"00" when h_grid='0' --- else x"ff"; - --- b<=x"00" when v_grid='0' and h_grid='0' --- else x"ff"; - --- --- dh : entity work.delay --- generic map(stages => 10) --- port map ( --- clk => clk, --- i => hsync, --- o => hsync_d --- ); --- --- --- --- dv : entity work.delay --- generic map(stages => 10) --- port map ( --- clk => clk, --- i => vsync, --- o => vsync_d --- ); --- --- --- - dn : entity work.delay - generic map(stages => 1) - port map ( - clk => clk, - i => blank, - o => blank_d - ); - - - hsync_d <= hsync; - vsync_d <= vsync; - - - analog : entity work.output_analog - port map( - sys_rst_n => sys_rst_n, - - clk => clk, - - hsync_in => hsync_d, - vsync_in => vsync_d, - blank_in => blank_d, - r_in => g(7), - g_in => r(7), - b_in => b(7), - - r_out => r_out, - g_out => g_out, - b_out => b_out, - hsync_out => hsync_out, - vsync_out => vsync_out - ); - - - tmds_e : entity work.tmds_encode port map ( - sys_rst_n => sys_rst_n, - pclk => clk, - - r_in => r, - g_in => g, - b_in => b, - hsync => hsync_d, - vsync => vsync_d, - blank => blank_d, - - r_p10 => r_p10, - g_p10 => g_p10, - b_p10 => b_p10, - c_p10 => c_p10 - - ); - - - tmds_o : entity work.tmds_output - port map ( - sys_rst_n => sys_rst_n, - pclk_locked => clk_locked, - pclk => clk, - pclk_x2 => clk_x2, - pclk_phy => clk_phy, - - r_p10 => r_p10, - g_p10 => g_p10, - b_p10 => b_p10, - c_p10 => c_p10, - - tmds_c_out_p => hdmi_c_p, - tmds_c_out_n => hdmi_c_n, - tmds_r_out_p => hdmi_r_p, - tmds_r_out_n => hdmi_r_n, - tmds_g_out_p => hdmi_g_p, - tmds_g_out_n => hdmi_g_n, - tmds_b_out_p => hdmi_b_p, - tmds_b_out_n => hdmi_b_n - ); - - - - -end beh; diff --git a/fpga/hp_lcd_driver_a7/rando_a7.tcl b/fpga/hp_lcd_driver_a7/rando_a7.tcl deleted file mode 100644 index cfaa74d..0000000 --- a/fpga/hp_lcd_driver_a7/rando_a7.tcl +++ /dev/null @@ -1,5 +0,0 @@ -# -set part_num "xc7a35tfgg484-2" -set normal_xdc "../rando_a7.xdc" -set use_pclk 1 -set video_width 6 diff --git a/fpga/hp_lcd_driver_a7/rando_a7.xdc b/fpga/hp_lcd_driver_a7/rando_a7.xdc deleted file mode 100644 index e6460b8..0000000 --- a/fpga/hp_lcd_driver_a7/rando_a7.xdc +++ /dev/null @@ -1,111 +0,0 @@ -# "Normal" constraints file- not early not late - - -set_property IOSTANDARD LVCMOS33 [get_ports clk_50m] -set_property PACKAGE_PIN R4 [get_ports clk_50m] - -set_property PACKAGE_PIN U1 [get_ports {led_0}] -set_property PACKAGE_PIN T1 [get_ports {led_1}] -set_property IOSTANDARD LVCMOS33 [get_ports {led_0}] -set_property IOSTANDARD LVCMOS33 [get_ports {led_1}] - -set_property PACKAGE_PIN R3 [get_ports {hdmi_r_p}] -set_property PACKAGE_PIN R2 [get_ports {hdmi_r_n}] -set_property PACKAGE_PIN R6 [get_ports {hdmi_g_p}] -set_property PACKAGE_PIN T6 [get_ports {hdmi_g_n}] -set_property PACKAGE_PIN U3 [get_ports {hdmi_b_p}] -set_property PACKAGE_PIN V3 [get_ports {hdmi_b_n}] -set_property PACKAGE_PIN Y3 [get_ports {hdmi_c_p}] -set_property PACKAGE_PIN AA3 [get_ports {hdmi_c_n}] - -set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}] -set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}] -set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_p}] -set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_n}] -set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_p}] -set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}] -set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}] -set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}] - -#set_property DRIVE 16 [get_ports {hdmi_c_p}] -#set_property DRIVE 16 [get_ports {hdmi_c_n}] -#set_property DRIVE 16 [get_ports {hdmi_r_p}] -#set_property DRIVE 16 [get_ports {hdmi_r_n}] -#set_property DRIVE 16 [get_ports {hdmi_g_p}] -#set_property DRIVE 16 [get_ports {hdmi_g_n}] -#set_property DRIVE 16 [get_ports {hdmi_b_p}] - -set_property PACKAGE_PIN W1 [get_ports {hdmi_vcc}] -set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}] - - -#set_property PACKAGE_PIN P20 [get_ports rxd] -#set_property PACKAGE_PIN T20 [get_ports txd] -#set_property IOSTANDARD LVCMOS33 [get_ports rxd] -#set_property IOSTANDARD LVCMOS33 [get_ports txd] - -#set_property PACKAGE_PIN T3 [get_ports key] -#set_property IOSTANDARD LVCMOS33 [get_ports key] - -set_property PACKAGE_PIN N22 [get_ports {video[0]}] -set_property PACKAGE_PIN N20 [get_ports {video[1]}] -set_property PACKAGE_PIN N18 [get_ports {video[2]}] -set_property PACKAGE_PIN K18 [get_ports {video[3]}] -set_property PACKAGE_PIN M18 [get_ports {video[4]}] -set_property PACKAGE_PIN M15 [get_ports {video[5]}] -#set_property PACKAGE_PIN U20 [get_ports {video[6]}] -#set_property PACKAGE_PIN T21 [get_ports {video[7]}] - -set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}] -set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}] - -set_property PACKAGE_PIN W19 [get_ports {pclk_in}] -set_property PACKAGE_PIN R18 [get_ports {vsync_in}] -set_property PACKAGE_PIN Y18 [get_ports {hsync_in}] -set_property PACKAGE_PIN P16 [get_ports {r_out}] -set_property PACKAGE_PIN V18 [get_ports {g_out}] -set_property PACKAGE_PIN P15 [get_ports {b_out}] -set_property PACKAGE_PIN P14 [get_ports {i_clk_out}] -set_property PACKAGE_PIN V17 [get_ports {hsync_out}] -set_property PACKAGE_PIN N13 [get_ports {vsync_out}] - -set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}] -set_property IOSTANDARD LVCMOS33 [get_ports {vsync_in}] -set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}] -set_property IOSTANDARD LVCMOS33 [get_ports {r_out}] -set_property IOSTANDARD LVCMOS33 [get_ports {g_out}] -set_property IOSTANDARD LVCMOS33 [get_ports {b_out}] -set_property IOSTANDARD LVCMOS33 [get_ports {i_clk_out}] -set_property IOSTANDARD LVCMOS33 [get_ports {hsync_out}] -set_property IOSTANDARD LVCMOS33 [get_ports {vsync_out}] - -create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m] -#set_false_path -from [get_ports pci_exp_rst_n] - - -############################################################################### -# Additional design / project settings -############################################################################### - -# Power down on overtemp -set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design] - -# High-speed configuration so FPGA is up in time to negotiate with PCIe root complex -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Div-1 [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property CONFIG_MODE SPIx4 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] - -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property CFGBVS VCCO [current_design] - - - - diff --git a/fpga/hp_lcd_driver_a7/scripts/save_pci b/fpga/hp_lcd_driver_a7/scripts/save_pci deleted file mode 100755 index 5576e4b..0000000 --- a/fpga/hp_lcd_driver_a7/scripts/save_pci +++ /dev/null @@ -1,45 +0,0 @@ -#!/bin/bash - -S="$1" - -D="" - -for i in /sys/bus/pci/devices/*; do -if [ "$(cat "$i/subsystem_vendor")$(cat "$i/subsystem_device")" == "0x103c0x5450" ]; then - D="$(basename $i)" -fi -done -D="$(echo $D | sed -e 's/^0000://' )" - - -# check it's really there -H1 forces talking to the card not the kernel - -if [ "$(setpci -H1 -s "${D}" SUBSYSTEM_VENDOR_ID.l)" != "5450103c" ]; then - D="" -fi - -if [ -z "$D" ]; then - echo "PCIe device not found" 1>&2 - if [ ! -f "$S" ]; then - echo "and no saved config, try a load and then a reboot" 1>^2 - exit 1 - fi - exit 0 -fi - - -echo "Device found at $D" - -echo "#!/bin/sh" > "$S" - -for i in $(seq 0 4 255); do - R="$(printf "0x%02x.l" $i)" - V="$(setpci -H1 -s "${D}" "${R}")" - echo "setpci -H1 -s \"${D}\" \"${R}=${V}\"" >> "$S" -done - -echo "if [ \"\$(setpci -H1 -s \"${D}\" SUBSYSTEM_VENDOR_ID.l)\" != \"5450103c\" ]; then exit 1; fi" >> "$S" - - -chmod +x "$S" - diff --git a/fpga/hp_lcd_driver_a7/scripts/vhdl-pretty b/fpga/hp_lcd_driver_a7/scripts/vhdl-pretty deleted file mode 100755 index c514b85..0000000 --- a/fpga/hp_lcd_driver_a7/scripts/vhdl-pretty +++ /dev/null @@ -1,60 +0,0 @@ -#! /bin/sh -":"; exec emacs --no-site-file --script "$0" -- "$0" "$@" # -*-emacs-lisp-*- -; vim: noai:ts=4:sw=4:syntax=lisp - -(setq arg0 (file-truename (car (cdr argv)))) -(setq args (cdr (cdr argv))) -(setq argv nil) - -; Parse the command line arguments, -; --xxx -> ("xxx" t) -; --no-xxx -> ("xxx" nil) -; --xxx=123 -> ("xxx" 123) -; --xxx=abc -> ("xxx" "abc") -; --xxx='abc 123' -> ("xxx" "abc 123") -; --xxx=abc=123 -> ("xxx" "abc=123") -(setq args - (mapcar - (lambda (arg) - (cond - ((string-match "^--no-\\([^=]*\\)$" arg) - (list (intern (match-string 1 arg)) nil)) - ((string-match "^--\\([^=]*\\)$" arg) - (list (intern (match-string 1 arg)) t)) - ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\([0-9]+\\)\\2$" arg) - (list (intern (match-string 1 arg)) (string-to-number (match-string 3 arg)))) - ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\(.+?\\)\\2$" arg) - (list (intern (match-string 1 arg)) (match-string 3 arg))) - (t nil) - )) - args)) - -; Read stdin into buffer -(defun insert-standard-input () - "insert contents from standard input" - (condition-case nil - (let (line) - (while (setq line (read-from-minibuffer "")) - (insert line "\n"))) - (error nil))) - -(insert-standard-input) -(goto-char (point-min)) - -; Load library -(setq basedir (concat (file-name-directory arg0) "vhdl-mode")) -(setq load-path (cons basedir load-path)) -(load-library "vhdl-mode") - -; Default customisation -(vhdl-set-style "IEEE") - -; Customisation from cmdline -(mapc (lambda (arg) (customize-set-variable (car arg) (car (cdr arg)))) args) - -; Turn on mode and beautify -(vhdl-mode) -(vhdl-beautify-region (point-min) (point-max)) - -; Output buffer to stdout -(princ (buffer-string)) diff --git a/fpga/hp_lcd_driver_a7/scripts/vivado b/fpga/hp_lcd_driver_a7/scripts/vivado deleted file mode 100755 index 0dbf03c..0000000 --- a/fpga/hp_lcd_driver_a7/scripts/vivado +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/bash -HS3_BIN=/home/DISTRIB/Xilinx/Digilent-HS3/foo -HS3_LIB=/home/DISTRIB/Xilinx/Digilent-HS3/foo -VIVADO=/software/apps/xilinx/Vivado/2022.1/ -VIVADO_BIN=${VIVADO}/bin -VIVADO_LIB=${VIVADO}/lib64 - -XILINXD_LICENSE_FILE=${PWD}/xilinx_ise_vivado_license.lic -export XILINXD_LICENSE_FILE - -export LD_LIBRARY_PATH - -PATH="${VIVADO_BIN}:${HS3_BIN}:$PATH" -LD_LIBRAY_PATH="${LD_LIBRARY_PATH}:/usr/lib64:/usr/lib:/lib64:/lib:${VIVADO_LIB}:${HS3_LIB}" - -exec ${VIVADO_BIN}/vivado $@ diff --git a/fpga/hp_lcd_driver_a7/synchronizer.vhdl b/fpga/hp_lcd_driver_a7/synchronizer.vhdl deleted file mode 100644 index 302cef9..0000000 --- a/fpga/hp_lcd_driver_a7/synchronizer.vhdl +++ /dev/null @@ -1,26 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -entity synchronizer is - generic (stages : natural := 2); - port (clk : in std_logic; - i : in std_logic; - o : out std_logic); -end synchronizer; - -architecture Behavioral of synchronizer is - signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); - attribute ASYNC_REG : string; - attribute ASYNC_REG of flipflops : signal is "true"; -begin - - o <= flipflops(flipflops'high); - - clk_proc : process(clk, flipflops, i) - begin - if rising_edge(clk) then - flipflops <= flipflops(flipflops'high-1 downto 0) & i; - end if; - end process; - -end Behavioral; diff --git a/fpga/hp_lcd_driver_a7/tmds_encode.vhdl b/fpga/hp_lcd_driver_a7/tmds_encode.vhdl deleted file mode 100644 index fe69a56..0000000 --- a/fpga/hp_lcd_driver_a7/tmds_encode.vhdl +++ /dev/null @@ -1,73 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - - -entity tmds_encode is - port ( - sys_rst_n : in std_logic; - pclk : in std_logic; - - r_in : in std_logic_vector(7 downto 0); - g_in : in std_logic_vector(7 downto 0); - b_in : in std_logic_vector(7 downto 0); - hsync : in std_logic; - vsync : in std_logic; - blank : in std_logic; - - - r_p10 : out std_logic_vector(9 downto 0); - g_p10 : out std_logic_vector(9 downto 0); - b_p10 : out std_logic_vector(9 downto 0); - c_p10 : out std_logic_vector(9 downto 0) - - ); -end tmds_encode; - - -architecture beh of tmds_encode is - signal ctrl : std_logic_vector(1 downto 0); - -begin - - c_p10 <= "1111100000"; - - ctrl <= vsync & hsync; - - - enc_r : entity work.tmds_encoder - port map ( - sys_rst_n => sys_rst_n, - clk => pclk, - ctrl => ctrl, - blank => blank, - din => r_in, - dout => r_p10 - ); - - enc_g : entity work.tmds_encoder - port map ( - sys_rst_n => sys_rst_n, - clk => pclk, - ctrl => "11", - blank => blank, - din => g_in, - dout => g_p10 - ); - - - - enc_b : entity work.tmds_encoder - port map ( - sys_rst_n => sys_rst_n, - clk => pclk, - ctrl => "11", - blank => blank, - din => b_in, - dout => b_p10 - ); - - -end beh; - - diff --git a/fpga/hp_lcd_driver_a7/tmds_encoder.vhdl b/fpga/hp_lcd_driver_a7/tmds_encoder.vhdl deleted file mode 100644 index 40f8dd4..0000000 --- a/fpga/hp_lcd_driver_a7/tmds_encoder.vhdl +++ /dev/null @@ -1,117 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity tmds_encoder is - port ( - clk : in std_logic; - sys_rst_n : in std_logic; - blank : in std_logic; - ctrl : in std_logic_vector(1 downto 0); - din : in std_logic_vector(7 downto 0); - dout : out std_logic_vector(9 downto 0) - ); -end tmds_encoder; - -architecture beh of tmds_encoder is - signal n_ones_din : integer range 0 to 8; - - signal xored, xnored : std_logic_vector(8 downto 0); - signal q_m : std_logic_vector(8 downto 0); - - -- a positive value represents the excess number of 1's that have been transmitted - -- a negative value represents the excess number of 0's that have been transmitted - signal disparity : signed(3 downto 0) := to_signed(0, 4); - -- difference between 1's and 0's (/2 since the last bit is never used) - signal diff : signed(3 downto 0) := to_signed(0, 4); - -begin - - -- ones counter for input data - process(din) is - variable c : integer range 0 to 8; - begin - c := 0; - for i in 0 to 7 loop - if din(i) = '1' then - c := c + 1; - end if; - end loop; - n_ones_din <= c; - end process; - - -- create xor encodings - xored(0) <= din(0); - encode_xor : for i in 1 to 7 generate - begin - xored(i) <= din(i) xor xored(i - 1); - end generate; - xored(8) <= '1'; - - -- create xnor encodings - xnored(0) <= din(0); - encode_xnor : for i in 1 to 7 generate - begin - xnored(i) <= din(i) xnor xnored(i - 1); - end generate; - xnored(8) <= '0'; - - -- use xnored or xored data based on the ones - q_m <= xnored when n_ones_din > 4 or (n_ones_din = 4 and din(0) = '0') else xored; - - -- ones counter for internal data - process(q_m) is - variable c : integer range 0 to 8; - begin - c := 0; - for i in 0 to 7 loop - if q_m(i) = '1' then - c := c + 1; - end if; - end loop; - diff <= to_signed(c-4, 4); - end process; - - process(clk) is - begin - if rising_edge(clk) then - if blank = '1' then - case ctrl is - when "00" => dout <= "1101010100"; - when "01" => dout <= "0010101011"; - when "10" => dout <= "0101010100"; - when others => dout <= "1010101011"; - end case; - disparity <= (others => '0'); - else - if disparity = 0 or diff = 0 then - -- xnored data - if q_m(8) = '0' then - dout <= "10" & not q_m(7 downto 0); - disparity <= disparity - diff; - -- xored data - else - dout <= "01" & q_m(7 downto 0); - disparity <= disparity + diff; - end if; - elsif (diff(diff'left) = '0' and disparity(disparity'left) = '0') or - (diff(diff'left) = '1' and disparity(disparity'left) = '1') then - dout <= '1' & q_m(8) & not q_m(7 downto 0); - if q_m(8) = '1' then - disparity <= disparity + 1 - diff; - else - disparity <= disparity - diff; - end if; - else - dout <= '0' & q_m; - if q_m(8) = '1' then - disparity <= disparity + diff; - else - disparity <= disparity - 1 + diff; - end if; - end if; - end if; - end if; - end process; -end beh; - diff --git a/fpga/hp_lcd_driver_a7/tmds_output_artix7.vhdl b/fpga/hp_lcd_driver_a7/tmds_output_artix7.vhdl deleted file mode 100644 index 7370bb7..0000000 --- a/fpga/hp_lcd_driver_a7/tmds_output_artix7.vhdl +++ /dev/null @@ -1,115 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - -library UNISIM; -use UNISIM.vcomponents.all; - - -entity tmds_output is - port ( - sys_rst_n : in std_logic; - pclk_locked : in std_logic; - pclk : in std_logic; - pclk_x2 : in std_logic; - pclk_phy : in std_logic; - - r_p10 : in std_logic_vector(9 downto 0); - g_p10 : in std_logic_vector(9 downto 0); - b_p10 : in std_logic_vector(9 downto 0); - c_p10 : in std_logic_vector(9 downto 0); - - - tmds_c_out_p : out std_logic; - tmds_c_out_n : out std_logic; - tmds_r_out_p : out std_logic; - tmds_r_out_n : out std_logic; - tmds_g_out_p : out std_logic; - tmds_g_out_n : out std_logic; - tmds_b_out_p : out std_logic; - tmds_b_out_n : out std_logic - ); -end tmds_output; - - -architecture beh of tmds_output is - - signal phy_reset : std_logic; - signal b : natural := 0; - - -begin - phy_reset <= not sys_rst_n; -- or not pll_locked; - - process (pclk_phy, b, sys_rst_n) - begin - if sys_rst_n = '0' then - b <= 0; - elsif rising_edge(pclk_phy) then - if b = 9 then - b <= 0; - else - b <= b+1; - end if; - end if; - end process; - - - phy_c : entity work.tmds_phy_artix7 - port map ( - reset => phy_reset, - pix_clk => pclk, - phy_clk => pclk_phy, - b =>b, - din => c_p10, - tmds_out_p => tmds_c_out_p, - tmds_out_n => tmds_c_out_n - ); - - phy_r : entity work.tmds_phy_artix7 - port map ( - reset => phy_reset, - pix_clk => pclk, - phy_clk => pclk_phy, - b =>b, - din => r_p10, - tmds_out_p => tmds_r_out_p, - tmds_out_n => tmds_r_out_n - ); - - - phy_g : entity work.tmds_phy_artix7 - port map ( - reset => phy_reset, - pix_clk => pclk, - phy_clk => pclk_phy, - b =>b, - din => g_p10, - tmds_out_p => tmds_g_out_p, - tmds_out_n => tmds_g_out_n - ); - - - phy_b : entity work.tmds_phy_artix7 - port map ( - reset => phy_reset, - pix_clk => pclk, - phy_clk => pclk_phy, - b =>b, - din => b_p10, - tmds_out_p => tmds_b_out_p, - tmds_out_n => tmds_b_out_n - ); - - --- tmds_c_out_p <= '0'; --- tmds_c_out_n <= '0'; --- tmds_r_out_p <= '0'; --- tmds_r_out_n <= '0'; --- tmds_g_out_p <= '0'; --- tmds_g_out_n <= '0'; --- tmds_b_out_p <= '0'; --- tmds_b_out_n <= '0'; --- - -end beh; diff --git a/fpga/hp_lcd_driver_a7/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver_a7/tmds_phy_artix7.vhdl deleted file mode 100644 index 8c8106e..0000000 --- a/fpga/hp_lcd_driver_a7/tmds_phy_artix7.vhdl +++ /dev/null @@ -1,85 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - -library UNISIM; -use UNISIM.vcomponents.all; - - -entity tmds_phy_artix7 is - port ( - reset : in std_logic; - pix_clk : in std_logic; - phy_clk : in std_logic; - din : in std_logic_vector(9 downto 0); - b : in natural; - tmds_out_p : out std_logic; - tmds_out_n : out std_logic - ); -end tmds_phy_artix7; - - -architecture beh of tmds_phy_artix7 is - - signal ld : std_logic_vector(9 downto 0); - signal sr : std_logic_vector(9 downto 0); - - signal s : std_logic; - -begin - - - process(pix_clk) - begin - if rising_edge(pix_clk) then - ld <= din; - end if; - end process; - - --- Using ODDR --- process(phy_clk) --- begin --- if rising_edge(phy_clk) then --- if b=0 then --- sr<= ld; --- else --- sr(7 downto 0) <= sr (9 downto 2); --- end if; --- end if; --- end process; --- ---ODDR_inst : ODDR ---generic map( --- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" --- INIT => '0', -- Initial value for Q port ('1' or '0') --- SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC") ---port map ( --- Q => s, -- 1-bit DDR output --- C => phy_clk, -- 1-bit clock input --- CE => '1', -- 1-bit clock enable input --- D1 => sr(0), -- 1-bit data input (positive edge) --- D2 => sr(1), -- 1-bit data input (negative edge) --- R => '0', -- 1-bit reset input --- S => '0' -- 1-bit set input ---); - - --- Using a shift register - process(phy_clk) - begin - if rising_edge(phy_clk) then - if b = 0 then - sr <= ld; - else - sr(8 downto 0) <= sr (9 downto 1); - s <=sr(0); - end if; - end if; - end process; - - - - od : OBUFDS port map (O => tmds_out_p, OB => tmds_out_n, I => s); - -end beh; diff --git a/fpga/hp_lcd_driver_a7/vram_artix7.vhdl b/fpga/hp_lcd_driver_a7/vram_artix7.vhdl deleted file mode 100644 index 82186e1..0000000 --- a/fpga/hp_lcd_driver_a7/vram_artix7.vhdl +++ /dev/null @@ -1,38 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity vram is - generic ( - addr_width : natural := 18; - video_width : natural := 6 - ); - port ( - wr_clk : in std_logic; - wr_en : in std_logic; - wr_addr : in std_logic_vector(addr_width-1 downto 0); - wr_data : in std_logic_vector(video_width-1 downto 0); - rd_clk : in std_logic; - rd_addr : in std_logic_vector(addr_width-1 downto 0); - rd_data : out std_logic_vector(video_width-1 downto 0) - ); -end vram; - -architecture beh of vram is - signal wr_en_v : std_logic_vector(0 downto 0); -begin - - wr_en_v(0) <= wr_en; - - bmg0 : entity work.blk_mem_gen_0 - port map ( - ena => '1', - enb => '1', - clka => wr_clk, - wea => wr_en_v, - addra => wr_addr, - dina => wr_data, - clkb => rd_clk, - doutb => rd_data, - addrb => rd_addr - ); -end beh; |