diff options
| -rw-r--r-- | spartan6/hp_lcd_driver/Makefile | 1 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/ep4ce15.cfg | 3 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/ep4ce15.mk | 2 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft | 9 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.vhdl | 58 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/input_formatter.vhdl | 55 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/input_stage.vhdl | 29 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/output_stage.vhdl | 11 |
8 files changed, 137 insertions, 31 deletions
diff --git a/spartan6/hp_lcd_driver/Makefile b/spartan6/hp_lcd_driver/Makefile index ba5560a..693085b 100644 --- a/spartan6/hp_lcd_driver/Makefile +++ b/spartan6/hp_lcd_driver/Makefile @@ -1,4 +1,5 @@ TARGETS= ep4ce15 spartan6 #ep4ce6 +fish:ep4ce15 default: ${TARGETS:%=build_%/hp_lcd_driver.svf} ep4ce15: build_ep4ce15/hp_lcd_driver.svf diff --git a/spartan6/hp_lcd_driver/ep4ce15.cfg b/spartan6/hp_lcd_driver/ep4ce15.cfg index 28de10c..39925e2 100644 --- a/spartan6/hp_lcd_driver/ep4ce15.cfg +++ b/spartan6/hp_lcd_driver/ep4ce15.cfg @@ -1,5 +1,4 @@ -interface usb_blaster -usb_blaster_lowlevel_driver ftdi + set CHIPNAME ep4ce15 set FPGA_TAPID 0x020f20dd diff --git a/spartan6/hp_lcd_driver/ep4ce15.mk b/spartan6/hp_lcd_driver/ep4ce15.mk index 2d00f9b..982934b 100644 --- a/spartan6/hp_lcd_driver/ep4ce15.mk +++ b/spartan6/hp_lcd_driver/ep4ce15.mk @@ -8,7 +8,7 @@ OF=output_files PROJECT = hp_lcd_driver VSRCS =synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl -IPS= vram_cyclone4_impl.vhdl clkgen_cyclone4_impl.vhdl +IPS= vram_cyclone4_impl.vhdl clkgen_cyclone4_impl.vhdl input_pll.vhdl DESIGN_NAME=${TOP} diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft b/spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft index 4f7ec29..e22c246 100644 --- a/spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft @@ -76,10 +76,11 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_r_p set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_r_n -set_location_assignment PIN_A10 -to hsync_in -set_location_assignment PIN_C10 -to vsync_in -set_location_assignment PIN_A13 -to video[0] -set_location_assignment PIN_C13 -to video[1] +set_location_assignment PIN_AA14 -to hsync_in +set_location_assignment PIN_W14 -to vsync_in +set_location_assignment PIN_AA15 -to video[0] +set_location_assignment PIN_V15 -to video[1] +set_location_assignment PIN_W7 -to i_clk_out diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl index d21cd2b..d8a8de3 100644 --- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl @@ -6,6 +6,7 @@ use work.all; entity hp_lcd_driver is generic (video_width : natural := 2; addr_width : natural := 18; + phase_slip : natural :=320; target : string := "spartan6"); port (clk_50m : in std_logic; sys_rst_n : in std_logic; @@ -24,7 +25,8 @@ entity hp_lcd_driver is hdmi_g_p : out std_logic; hdmi_g_n : out std_logic; hdmi_b_p : out std_logic; - hdmi_b_n : out std_logic); + hdmi_b_n : out std_logic; + i_clk_out : out std_logic); end hp_lcd_driver; @@ -51,6 +53,11 @@ architecture Behavioral of hp_lcd_driver is signal o_clk_phy : std_logic; signal sys_rst : std_logic; + signal pa: natural; + signal epk: std_logic; + signal ic: natural; + + begin @@ -61,17 +68,55 @@ begin -- o_clk_x2 is used by the spartan serdes -- o_clk_phy is used the the hdmi phy (cylone4 it's o_clk x5, spartan 6 it's o_clk x 10) + i_clkgen : entity work.input_pll + port map ( + areset => open, + inclk0 => clk_50m, + c0 => i_clk, + locked => open); + + + process (i_clk,sys_rst_n) begin + if sys_rst_n='0' then + ic<=0; + pa<=phase_slip; + epk<='0'; + elsif rising_edge(i_clk) then + + if ic =0 then + epk<='1'; + if pa = 0 then + pa<= phase_slip; + ic <= 4; + else + ic <=3; + pa <= pa -1; + end if; + else + if epk='1' then + epk<='0'; + end if; + ic<=ic-1; + end if; + end if; + end process; + + +i_clk_out <= epk; + clkgen : entity work.clkgen port map ( sys_rst_n => sys_rst_n, clk_in => clk_50m, - i_clk => i_clk, + i_clk => open, o_clk => o_clk, o_clk_x2 => o_clk_x2, o_clk_phy => o_clk_phy, locked => clk_locked - ); + + --i_clk_out <= i_clk; + input0 : entity work.input_stage generic map( video_width => video_width, @@ -82,8 +127,10 @@ begin h_active => 592, v_front_porch => 2, v_active => 384, + frame_start => 380, h_stride => 384, - v_stride => 1 + v_stride => 262143, + phase_slip => phase_slip ) port map ( sys_rst_n => sys_rst_n, @@ -91,6 +138,9 @@ begin video_in => video, hsync_in => hsync_in, vsync_in => vsync_in, + --hsync_in => '0', + --vsync_in => '0', + video_out => wr_data, addr_out => wr_addr, wren_out => wr_en); diff --git a/spartan6/hp_lcd_driver/input_formatter.vhdl b/spartan6/hp_lcd_driver/input_formatter.vhdl index d50a43e..6f8af72 100644 --- a/spartan6/hp_lcd_driver/input_formatter.vhdl +++ b/spartan6/hp_lcd_driver/input_formatter.vhdl @@ -2,6 +2,12 @@ library ieee; use ieee.std_logic_1164.all; use IEEE.NUMERIC_STD.all; +-- i_clk is 78.704625 +-- the scope's pixel clock is 19.660819 +-- ratio is 4.003120 +-- 1/0.003120 is 320 + + entity input_formatter is generic ( @@ -12,8 +18,10 @@ entity input_formatter is h_active : natural := 592; v_front_porch : natural := 2; v_active : natural := 384; + frame_start : natural := 0; h_stride : natural := 384; - v_stride : natural := 1); + v_stride : natural := 1; + phase_slip : natural := 320); port ( sys_rst_n : in std_logic; @@ -21,7 +29,9 @@ entity input_formatter is hsync : in std_logic; vsync : in std_logic; addr_out : out std_logic_vector(addr_width-1 downto 0); - wren_out : out std_logic + wren_out : out std_logic; + h_grid : out std_logic; + v_grid : out std_logic ); end input_formatter; @@ -34,6 +44,7 @@ architecture beh of input_formatter is signal wren : std_logic; signal hsync_ne : std_logic; + signal hsync_pe : std_logic; signal v_fp_counter : natural; signal v_active_counter : natural; @@ -41,6 +52,8 @@ architecture beh of input_formatter is signal h_active_counter : natural; signal h_div : natural; + signal phase_accum : natural; + begin @@ -50,8 +63,8 @@ begin clk => clk, sig => hsync, e => open, - pe => open, - ne => hsync_ne); + ne => hsync_ne, + pe => hsync_pe); @@ -59,7 +72,7 @@ begin addr_out <= addr; - process (sys_rst_n, clk, hsync_ne, vsync) + process (sys_rst_n, clk, hsync_pe, vsync) begin if sys_rst_n = '0' then row_addr <= (others => '0'); @@ -69,10 +82,12 @@ begin h_fp_counter <= 0; v_active_counter <= 0; v_fp_counter <= 0; + phase_accum <= 0; elsif rising_edge(clk) then - if hsync_ne = '1' then + if hsync_pe = '1' then + --if v_active_counter = 0 and v_fp_counter=0 then if vsync = '1' then - row_addr <= (others => '0'); + row_addr <= std_logic_vector(to_unsigned(frame_start,addr_width)); v_fp_counter <= v_front_porch; v_active_counter <= v_active; elsif v_fp_counter /= 0 then @@ -82,6 +97,7 @@ begin h_fp_counter <= h_front_porch * clk_multiple + phase; h_active_counter <= h_active; + phase_accum <= phase_slip; h_div <= 0; addr <= row_addr; @@ -93,14 +109,21 @@ begin if h_div = 0 then wren <= '1'; - h_div <= clk_multiple -1; - elsif h_div = clk_multiple -1 then + if phase_accum = 0 then + phase_accum <= phase_slip; + h_div <= clk_multiple ; + else + phase_accum <= phase_accum-1; + h_div <= clk_multiple -1; + end if; + + else + if wren = '1' then wren <= '0'; h_active_counter <= h_active_counter -1; addr <= std_logic_vector(unsigned(addr)+h_stride); - h_div <= clk_multiple -1; - else - h_div <= clk_multiple -1; + end if; + h_div <= h_div -1; end if; end if; end if; @@ -109,4 +132,12 @@ begin addr_out <= addr; wren_out <= wren; + + h_grid <='1' when (h_active_counter mod 8)=0 + else '0'; + + v_grid <='1' when (v_active_counter mod 8)=0 + else '0'; + + end beh; diff --git a/spartan6/hp_lcd_driver/input_stage.vhdl b/spartan6/hp_lcd_driver/input_stage.vhdl index 077d8a3..0658abb 100644 --- a/spartan6/hp_lcd_driver/input_stage.vhdl +++ b/spartan6/hp_lcd_driver/input_stage.vhdl @@ -13,8 +13,10 @@ entity input_stage is h_active : natural := 592; v_front_porch : natural := 2; v_active : natural := 384; + frame_start : natural := 0; h_stride : natural := 384; - v_stride : natural := 1); + v_stride : natural := 1; + phase_slip:natural := 320); port ( clk : in std_logic; @@ -45,6 +47,11 @@ architecture beh of input_stage is signal addr : std_logic_vector(addr_width - 1 downto 0); signal wren : std_logic; + signal h_grid: std_logic; + signal v_grid: std_logic; + + signal addr_test : std_logic_vector(addr_width - 1 downto 0); + begin video_sync_for : for b in 0 to video_width -1 generate @@ -57,7 +64,6 @@ begin ); end generate; - video_out <= s_video; hsync_sync : entity work.synchronizer @@ -103,19 +109,34 @@ begin h_active => h_active, v_front_porch => v_front_porch, v_active => v_active, + frame_start => frame_start, h_stride => h_stride, - v_stride => v_stride) + v_stride => v_stride, + phase_slip => phase_slip) port map ( sys_rst_n => sys_rst_n, clk => clk, hsync => d_hsync, vsync => d_vsync, addr_out => addr, - wren_out => wren + wren_out => wren, + h_grid => h_grid, + v_grid => v_grid ); +--wren_out <='1'; + +--video_out(0) <='1'; +--video_out(1) <='1'; + addr_out <= addr; wren_out <= wren; + video_out <= s_video; + + --video_out(0) <= h_grid; + --video_out(1) <= v_grid; + + end beh; diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl index 41b1760..ae1b2bd 100644 --- a/spartan6/hp_lcd_driver/output_stage.vhdl +++ b/spartan6/hp_lcd_driver/output_stage.vhdl @@ -129,13 +129,16 @@ begin addr_out <= addr; + r<=r_in; + g<=g_in; b<=b_in; - r<=x"00" when h_grid='0' - else x"ff"; - g<=x"00" when v_grid='0' - else x"ff"; +-- r<=x"00" when h_grid='0' +-- else x"ff"; + +-- g<=x"00" when v_grid='0' +-- else x"ff"; |