diff options
| -rw-r--r-- | spartan6/hp_lcd_driver/.gitignore | 2 | ||||
| l---------[-rw-r--r--] | spartan6/hp_lcd_driver/Makefile | 130 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/Makefile.spartan6 | 129 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/clkgen_spartan6.vhdl (renamed from spartan6/hp_lcd_driver/clkgen.vhdl) | 6 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.ucf | 2 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.vhdl | 36 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/output_stage.vhdl | 39 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/tmds_encode.vhdl | 73 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl (renamed from spartan6/hp_lcd_driver/tmds_output.vhdl) | 66 |
9 files changed, 255 insertions, 228 deletions
diff --git a/spartan6/hp_lcd_driver/.gitignore b/spartan6/hp_lcd_driver/.gitignore index 567609b..984573f 100644 --- a/spartan6/hp_lcd_driver/.gitignore +++ b/spartan6/hp_lcd_driver/.gitignore @@ -1 +1 @@ -build/ +build_spartan6/ diff --git a/spartan6/hp_lcd_driver/Makefile b/spartan6/hp_lcd_driver/Makefile index e1beea7..b3e7186 100644..120000 --- a/spartan6/hp_lcd_driver/Makefile +++ b/spartan6/hp_lcd_driver/Makefile @@ -1,129 +1 @@ -include relpath.mk - -XILNXD_LICENSE_FILE:=${PWD}/xilinx_ise_vivado_license.lic -export XILINXD_LICENSE_FILE -PART=xc6slx9-2-tqg144 -TOP=hp_lcd_driver -BUILD=build -VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1.vhdl tmds_encoder.vhdl tmds_phy.vhdl tmds_output.vhdl output_stage.vhdl clkgen.vhdl hp_lcd_driver.vhdl -UCF=hp_lcd_driver.ucf -UT=hp_lcd_driver.ut -IPSRCS=vram.xco -DESIGN_NAME=${TOP} -DS_HOME=/software/apps/xilinx/ISE/14.7/ISE_DS -ISE_HOME=${DS_HOME}/ISE -ISE_BINDIR_32=${ISE_HOME}/bin/lin -ISE_BINDIR_64=${ISE_HOME}/bin/lin64 -INTSTYLE= - -XST_FLAGS=${INTSTYLE} -NGDBUILD_FLAGS=${INTSTYLE} -p ${PART} -dd _ngo -nt timestamp -MAP_FLAGS=${INTSTYLE} -p ${PART} -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -PAR_FLAGS=${INTSTYLE} -w -ol high -mt off -TRCE_FLAGS=${INTSTYLE} -v 3 -s 2 -n 3 -fastpaths -BITGEN_FLAGS=${INTSTYLE} - - - -GEN_VSRCS=${IPSRCS:%.xco=${BUILD}/%.vhd} -BASE=${BUILD}/${DESIGN_NAME} -XST=${BASE}.xst -PRJ=${BASE}.prj -SYR=${BASE}.syr -NGC=${BASE}.ngc -NGD=${BASE}.ngd -MAP_NCD=${BASE}_map.ncd -NCD=${BASE}.ncd -PCF=${BASE}.pcf -TWR=${BASE}.twr -TWX=${BASE}.twx -BIT=${BASE}.bit -SVF=${BASE}.svf -PA=${BUILD}/pa -PAT=${PA}/script.tcl - -XST_TMPDIR=xst/projnav.tmp -XST_DIR=xst - - - -default: ${NCD} ${TWR} ${TWX} ${BIT} ${SVF} - -clean: - /bin/rm -rf ${BUILD} *.orig *~ - -${PRJ}: ${VSRCS} ${GEN_VSRCS} - mkdir -p ${BUILD} - rm -f $@ - for file in $(GEN_VSRCS) ${VSRCS}; do \ - echo "vhdl work $$(realpath -m --relative-to=${BUILD} $${file})" >> $@ ; \ - done ; - -${NGC}:${XST} - (cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR_64}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD})) - -${XST}: ${PRJ} ${DESIGN_NAME}.xst_template - rm -f $@ - echo 'set -tmpdir "${XST_TMPDIR}"' >> $@ - echo 'set -xsthdpdir "${XST_DIR}"' >> $@ - cat ${DESIGN_NAME}.xst_template >> $@ - echo "-ifn $(call relpath,${PRJ},${BUILD})" >> $@ - echo "-ofn $(call relpath,${BASE},${BUILD})" >> $@ - echo "-p ${PART}" >> $@ - echo "-top ${TOP}" >> $@ - -${NGD}:${NGC} ${UCF} - (cd ${BUILD} && ${ISE_BINDIR_64}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD})) - -${MAP_NCD} ${PCF}:${NGD} - (cd ${BUILD} && ${ISE_BINDIR_64}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD}) $(call relpath,${PCF},${BUILD})) - -${NCD}: ${MAP_NCD} ${PCF} - (cd ${BUILD} && ${ISE_BINDIR_64}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD})) - -${TWR} ${TWX}: ${NCD} ${PCF} - (cd ${BUILD} && ${ISE_BINDIR_64}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD})) - -${BIT}:${NCD} ${UT} - (cd ${BUILD} && ${ISE_BINDIR_64}/bitgen ${BITGEN_FLAGS} -f $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD})) - -${SVF}:${BIT} - ( cd ${BUILD} && \ - echo -e "setMode -bs \n\ - setCable -p svf -file \"$(call relpath,${SVF},${BUILD})\" \n\ - addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\" \n\ - program -p 1 \n\ - quit \n" > impact.run &&\ - ${ISE_BINDIR_64}/impact -batch impact.run) - - -${BUILD}/%.vhd:%.xco - mkdir -p ${BUILD} - (cd ${BUILD} && touch empty.prj && ${ISE_BINDIR_32}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj) - - -planahead: ${NGC} ${TWX} - rm -rf ${PA} - mkdir -p ${PA} - echo 'create_project -name ${TOP} -dir "$(abspath ${PA})" -part ${PART}' >> ${PAT} - echo 'set srcset [get_property srcset [current_run -impl]]' >> ${PAT} - echo 'set_property design_mode GateLvl $$srcset' >> ${PAT} - echo 'set_property top ${TOP} [current_fileset]' >> ${PAT} - echo 'set_property edif_top_file "$(abspasth ${NGC})" [ get_property srcset [ current_run ] ]' >> ${PAT} - echo 'add_files -norecurse { {$(abspath ${BUILD})} }' >> ${PAT} - echo 'set_property target_constrs_file "$(abspath ${UCF})" [current_fileset -constrset]' >> ${PAT} - echo 'add_files [list {$(abspath ${UCF})}] -fileset [get_property constrset [current_run]]' >> ${PAT} - echo 'link_design' >> ${PAT} - echo 'read_xdl -file "$(abspath ${NCD})"' >> ${PAT} - echo 'if {[catch {read_twx -name results_1 -file "$(abspath ${TWX})"} eInfo]} {' >> ${PAT} - echo 'puts "WARNING: there was a problem importing \"$(abspath ${TWX})\": $$eInfo"' >> ${PAT} - echo '}' >> ${PAT} - (cd ${PA} && ${DS_HOME}/PlanAhead/bin/planAhead -log $(abspath ${PA}/pa.log) -journal $(abspath ${PA}/pa.jou) -source $(abspath ${PAT})) - - - -tidy: - git diff --exit-code -s ${VSRCS} - for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done - - +Makefile.spartan6
\ No newline at end of file diff --git a/spartan6/hp_lcd_driver/Makefile.spartan6 b/spartan6/hp_lcd_driver/Makefile.spartan6 new file mode 100644 index 0000000..83a389e --- /dev/null +++ b/spartan6/hp_lcd_driver/Makefile.spartan6 @@ -0,0 +1,129 @@ +include relpath.mk + +XILNXD_LICENSE_FILE:=${PWD}/xilinx_ise_vivado_license.lic +export XILINXD_LICENSE_FILE +PART=xc6slx9-2-tqg144 +TOP=hp_lcd_driver +BUILD=build_spartan6 +VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1.vhdl tmds_encoder.vhdl tmds_phy.vhdl tmds_encode.vhdl tmds_output_spartan6.vhdl output_stage.vhdl clkgen_spartan6.vhdl hp_lcd_driver.vhdl +UCF=hp_lcd_driver.ucf +UT=hp_lcd_driver.ut +IPSRCS=vram.xco +DESIGN_NAME=${TOP} +DS_HOME=/software/apps/xilinx/ISE/14.7/ISE_DS +ISE_HOME=${DS_HOME}/ISE +ISE_BINDIR_32=${ISE_HOME}/bin/lin +ISE_BINDIR_64=${ISE_HOME}/bin/lin64 +INTSTYLE= + +XST_FLAGS=${INTSTYLE} +NGDBUILD_FLAGS=${INTSTYLE} -p ${PART} -dd _ngo -nt timestamp +MAP_FLAGS=${INTSTYLE} -p ${PART} -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off +PAR_FLAGS=${INTSTYLE} -w -ol high -mt off +TRCE_FLAGS=${INTSTYLE} -v 3 -s 2 -n 3 -fastpaths +BITGEN_FLAGS=${INTSTYLE} + + + +GEN_VSRCS=${IPSRCS:%.xco=${BUILD}/%.vhd} +BASE=${BUILD}/${DESIGN_NAME} +XST=${BASE}.xst +PRJ=${BASE}.prj +SYR=${BASE}.syr +NGC=${BASE}.ngc +NGD=${BASE}.ngd +MAP_NCD=${BASE}_map.ncd +NCD=${BASE}.ncd +PCF=${BASE}.pcf +TWR=${BASE}.twr +TWX=${BASE}.twx +BIT=${BASE}.bit +SVF=${BASE}.svf +PA=${BUILD}/pa +PAT=${PA}/script.tcl + +XST_TMPDIR=xst/projnav.tmp +XST_DIR=xst + + + +default: ${NCD} ${TWR} ${TWX} ${BIT} ${SVF} + +clean: + /bin/rm -rf ${BUILD} *.orig *~ + +${PRJ}: ${VSRCS} ${GEN_VSRCS} + mkdir -p ${BUILD} + rm -f $@ + for file in $(GEN_VSRCS) ${VSRCS}; do \ + echo "vhdl work $$(realpath -m --relative-to=${BUILD} $${file})" >> $@ ; \ + done ; + +${NGC}:${XST} + (cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR_64}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD})) + +${XST}: ${PRJ} ${DESIGN_NAME}.xst_template + rm -f $@ + echo 'set -tmpdir "${XST_TMPDIR}"' >> $@ + echo 'set -xsthdpdir "${XST_DIR}"' >> $@ + cat ${DESIGN_NAME}.xst_template >> $@ + echo "-ifn $(call relpath,${PRJ},${BUILD})" >> $@ + echo "-ofn $(call relpath,${BASE},${BUILD})" >> $@ + echo "-p ${PART}" >> $@ + echo "-top ${TOP}" >> $@ + +${NGD}:${NGC} ${UCF} + (cd ${BUILD} && ${ISE_BINDIR_64}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD})) + +${MAP_NCD} ${PCF}:${NGD} + (cd ${BUILD} && ${ISE_BINDIR_64}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD}) $(call relpath,${PCF},${BUILD})) + +${NCD}: ${MAP_NCD} ${PCF} + (cd ${BUILD} && ${ISE_BINDIR_64}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD})) + +${TWR} ${TWX}: ${NCD} ${PCF} + (cd ${BUILD} && ${ISE_BINDIR_64}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD})) + +${BIT}:${NCD} ${UT} + (cd ${BUILD} && ${ISE_BINDIR_64}/bitgen ${BITGEN_FLAGS} -f $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD})) + +${SVF}:${BIT} + ( cd ${BUILD} && \ + echo -e "setMode -bs \n\ + setCable -p svf -file \"$(call relpath,${SVF},${BUILD})\" \n\ + addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\" \n\ + program -p 1 \n\ + quit \n" > impact.run &&\ + ${ISE_BINDIR_64}/impact -batch impact.run) + + +${BUILD}/%.vhd:%.xco + mkdir -p ${BUILD} + (cd ${BUILD} && touch empty.prj && ${ISE_BINDIR_32}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj) + + +planahead: ${NGC} ${TWX} + rm -rf ${PA} + mkdir -p ${PA} + echo 'create_project -name ${TOP} -dir "$(abspath ${PA})" -part ${PART}' >> ${PAT} + echo 'set srcset [get_property srcset [current_run -impl]]' >> ${PAT} + echo 'set_property design_mode GateLvl $$srcset' >> ${PAT} + echo 'set_property top ${TOP} [current_fileset]' >> ${PAT} + echo 'set_property edif_top_file "$(abspasth ${NGC})" [ get_property srcset [ current_run ] ]' >> ${PAT} + echo 'add_files -norecurse { {$(abspath ${BUILD})} }' >> ${PAT} + echo 'set_property target_constrs_file "$(abspath ${UCF})" [current_fileset -constrset]' >> ${PAT} + echo 'add_files [list {$(abspath ${UCF})}] -fileset [get_property constrset [current_run]]' >> ${PAT} + echo 'link_design' >> ${PAT} + echo 'read_xdl -file "$(abspath ${NCD})"' >> ${PAT} + echo 'if {[catch {read_twx -name results_1 -file "$(abspath ${TWX})"} eInfo]} {' >> ${PAT} + echo 'puts "WARNING: there was a problem importing \"$(abspath ${TWX})\": $$eInfo"' >> ${PAT} + echo '}' >> ${PAT} + (cd ${PA} && ${DS_HOME}/PlanAhead/bin/planAhead -log $(abspath ${PA}/pa.log) -journal $(abspath ${PA}/pa.jou) -source $(abspath ${PAT})) + + + +tidy: + git diff --exit-code -s ${VSRCS} + for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done + + diff --git a/spartan6/hp_lcd_driver/clkgen.vhdl b/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl index 5d3c8f2..e3c0242 100644 --- a/spartan6/hp_lcd_driver/clkgen.vhdl +++ b/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl @@ -6,7 +6,7 @@ use work.all; library UNISIM; use UNISIM.vcomponents.all; -entity clkgen is +entity clkgen_spartan6 is port ( sys_rst_n:in std_logic; clk_in: in std_logic; @@ -16,8 +16,8 @@ entity clkgen is o_clk_x10: out std_logic; locked: out std_logic ); -end clkgen; -architecture Behavioural of clkgen is +end clkgen_spartan6; +architecture Behavioural of clkgen_spartan6 is signal clkfbout : std_logic; signal clk_200m : std_logic; diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.ucf b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf index c30e6e3..ae00a1b 100644 --- a/spartan6/hp_lcd_driver/hp_lcd_driver.ucf +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf @@ -15,7 +15,7 @@ NET "vsync_out" IOSTANDARD = LVCMOS33; INST "clkgen/pll" LOC = PLL_ADV_X0Y1; -INST "output0/tmds/ioclk_buf" LOC = BUFPLL_X1Y5; +INST "output0/tmds_o/ioclk_buf" LOC = BUFPLL_X1Y5; NET "hdmi_c_p" LOC = P144; NET "hdmi_c_n" LOC = P143; diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl index d37db58..0337320 100644 --- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl @@ -1,41 +1,12 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:20:32 04/26/2025 --- Design Name: --- Module Name: hp_lcd_driver - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.all; -library UNISIM; -use UNISIM.vcomponents.all; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity hp_lcd_driver is generic (video_width : natural := 2; - addr_width : natural := 18); + addr_width : natural := 18; + target : string := "spartan6" ); port (clk_50m : in std_logic; sys_rst_n : in std_logic; video : in std_logic_vector(video_width-1 downto 0); @@ -84,7 +55,7 @@ architecture Behavioral of hp_lcd_driver is begin - clkgen: entity work.clkgen + clkgen: entity work.clkgen_spartan6 port map ( sys_rst_n => sys_rst_n, clk_in => clk_50m, @@ -146,6 +117,7 @@ begin -- works at 60Hz xrandr --newmode "$M" 18.24 384 400 440 600 592 593 596 613 -HSync +Vsync generic map ( + target => target, addr_width => addr_width, h_active => 384, h_sync_start => 400, diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl index 0b04de0..0c75b3d 100644 --- a/spartan6/hp_lcd_driver/output_stage.vhdl +++ b/spartan6/hp_lcd_driver/output_stage.vhdl @@ -7,7 +7,8 @@ use UNISIM.vcomponents.all; entity output_stage is - generic (debounce_stages : natural := 2; + generic (target : string := "spartan6"; + debounce_stages : natural := 2; sync_stages : natural := 2; addr_width : natural := 17; h_front_porch : natural := 208; @@ -70,6 +71,13 @@ architecture beh of output_stage is signal addr : std_logic_vector(addr_width - 1 downto 0); + + signal r_p10 :std_logic_vector(9 downto 0); + signal g_p10 :std_logic_vector(9 downto 0); + signal b_p10 :std_logic_vector(9 downto 0); + signal c_p10 :std_logic_vector(9 downto 0); + + begin @@ -137,14 +145,9 @@ begin ); - - tmds : entity work.tmds_output - port map ( +tmds_e : entity work.tmds_encode port map ( sys_rst_n => sys_rst_n, - pclk_locked => clk_locked, pclk => clk, - pclk_x2 => clk_x2, - pclk_x10 => clk_x10, r_in => r_in, g_in => g_in, @@ -153,6 +156,28 @@ begin vsync => vsync, blank => blank, + r_p10 => r_p10, + g_p10 => g_p10, + b_p10 => b_p10, + c_p10 => c_p10 + + ); + + + + tmds_o : entity work.tmds_output_spartan6 + port map ( + sys_rst_n => sys_rst_n, + pclk_locked => clk_locked, + pclk => clk, + pclk_x2 => clk_x2, + pclk_x10 => clk_x10, + + r_p10 => r_p10, + g_p10 => g_p10, + b_p10 => b_p10, + c_p10 => c_p10, + tmds_c_out_p => hdmi_c_p, tmds_c_out_n => hdmi_c_n, tmds_r_out_p => hdmi_r_p, diff --git a/spartan6/hp_lcd_driver/tmds_encode.vhdl b/spartan6/hp_lcd_driver/tmds_encode.vhdl new file mode 100644 index 0000000..d302960 --- /dev/null +++ b/spartan6/hp_lcd_driver/tmds_encode.vhdl @@ -0,0 +1,73 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; + + +entity tmds_encode is + port ( + sys_rst_n : in std_logic; + pclk : in std_logic; + + r_in : in std_logic_vector(7 downto 0); + g_in : in std_logic_vector(7 downto 0); + b_in : in std_logic_vector(7 downto 0); + hsync : in std_logic; + vsync : in std_logic; + blank : in std_logic; + + + r_p10 : out std_logic_vector(9 downto 0); + g_p10 : out std_logic_vector(9 downto 0); + b_p10 : out std_logic_vector(9 downto 0); + c_p10 : out std_logic_vector(9 downto 0) + + ); +end tmds_encode; + + +architecture beh of tmds_encode is + signal ctrl : std_logic_vector(1 downto 0); + +begin + +c_p10 <= "1111100000"; + + ctrl <= vsync & hsync; + + + enc_r : entity work.tmds_encoder + port map ( + sys_rst_n => sys_rst_n, + clk => pclk, + ctrl => ctrl, + blank => blank, + din => r_in, + dout => r_p10 + ); + + enc_g : entity work.tmds_encoder + port map ( + sys_rst_n => sys_rst_n, + clk => pclk, + ctrl => "11", + blank => blank, + din => g_in, + dout => g_p10 + ); + + + + enc_b : entity work.tmds_encoder + port map ( + sys_rst_n => sys_rst_n, + clk => pclk, + ctrl => "11", + blank => blank, + din => b_in, + dout => b_p10 + ); + + +end beh; + + diff --git a/spartan6/hp_lcd_driver/tmds_output.vhdl b/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl index ba095ef..3212998 100644 --- a/spartan6/hp_lcd_driver/tmds_output.vhdl +++ b/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl @@ -6,19 +6,20 @@ library UNISIM; use UNISIM.vcomponents.all; -entity tmds_output is +entity tmds_output_spartan6 is port ( sys_rst_n : in std_logic; pclk_locked : in std_logic; pclk : in std_logic; pclk_x2 : in std_logic; pclk_x10 : in std_logic; - r_in : in std_logic_vector(7 downto 0); - g_in : in std_logic_vector(7 downto 0); - b_in : in std_logic_vector(7 downto 0); - hsync : in std_logic; - vsync : in std_logic; - blank : in std_logic; + + r_p10 : in std_logic_vector(9 downto 0); + g_p10 : in std_logic_vector(9 downto 0); + b_p10 : in std_logic_vector(9 downto 0); + c_p10 : in std_logic_vector(9 downto 0); + + tmds_c_out_p : out std_logic; tmds_c_out_n : out std_logic; tmds_r_out_p : out std_logic; @@ -28,15 +29,11 @@ entity tmds_output is tmds_b_out_p : out std_logic; tmds_b_out_n : out std_logic ); -end tmds_output; +end tmds_output_spartan6; -architecture beh of tmds_output is +architecture beh of tmds_output_spartan6 is - signal ctrl : std_logic_vector(1 downto 0); - signal r_p10 : std_logic_vector(9 downto 0); - signal g_p10 : std_logic_vector(9 downto 0); - signal b_p10 : std_logic_vector(9 downto 0); signal phy_reset : std_logic; signal upper : std_logic; @@ -45,47 +42,6 @@ architecture beh of tmds_output is signal serdesstrobe : std_logic; begin - - - ctrl <= vsync & hsync; - - - - - enc_r : entity work.tmds_encoder - port map ( - sys_rst_n => sys_rst_n, - clk => pclk, - ctrl => ctrl, - blank => blank, - din => r_in, - dout => r_p10 - ); - - - enc_g : entity work.tmds_encoder - port map ( - sys_rst_n => sys_rst_n, - clk => pclk, - ctrl => "11", - blank => blank, - din => g_in, - dout => g_p10 - ); - - - - enc_b : entity work.tmds_encoder - port map ( - sys_rst_n => sys_rst_n, - clk => pclk, - ctrl => "11", - blank => blank, - din => b_in, - dout => b_p10 - ); - - phy_reset <= not sys_rst_n or not pll_locked; process (pclk_x2,phy_reset) @@ -115,7 +71,7 @@ begin serdesstrobe => serdesstrobe, ioclk => ioclk, upper => upper, - din => "1111100000", + din => c_p10, tmds_out_p => tmds_c_out_p, tmds_out_n => tmds_c_out_n ); |