diff options
| -rw-r--r-- | spartan6/hp_lcd_driver/.gitignore | 1 | ||||
| l--------- | spartan6/hp_lcd_driver/Makefile | 2 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/Makefile.cyclone4 | 126 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl | 80 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/clkgen_spartan6.vhdl | 6 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.qsf_template | 51 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.vhdl | 27 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/output_stage.vhdl | 65 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl | 6 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl | 125 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl | 14 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl | 8 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/vram_cyclone4.vhdl | 35 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/vram_cyclone4_impl.vhdl | 231 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/vram_spartan6_impl.xco | 6 |
15 files changed, 743 insertions, 40 deletions
diff --git a/spartan6/hp_lcd_driver/.gitignore b/spartan6/hp_lcd_driver/.gitignore index 984573f..6adc620 100644 --- a/spartan6/hp_lcd_driver/.gitignore +++ b/spartan6/hp_lcd_driver/.gitignore @@ -1 +1,2 @@ build_spartan6/ +build_cyclone4/ diff --git a/spartan6/hp_lcd_driver/Makefile b/spartan6/hp_lcd_driver/Makefile index b3e7186..b11d7da 120000 --- a/spartan6/hp_lcd_driver/Makefile +++ b/spartan6/hp_lcd_driver/Makefile @@ -1 +1 @@ -Makefile.spartan6
\ No newline at end of file +Makefile.cyclone4
\ No newline at end of file diff --git a/spartan6/hp_lcd_driver/Makefile.cyclone4 b/spartan6/hp_lcd_driver/Makefile.cyclone4 new file mode 100644 index 0000000..5184c7c --- /dev/null +++ b/spartan6/hp_lcd_driver/Makefile.cyclone4 @@ -0,0 +1,126 @@ +include relpath.mk + +FAMILY=Cyclone IV E +PART=EP4CE15F23C8 +TOP=hp_lcd_driver +BUILD=build_cyclone4 +OF=output_files + +PROJECT = hp_lcd_driver +VSRCS =synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_output_cyclone4.vhdl output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl +IPS= vram_cyclone4_impl.vhdl + +DESIGN_NAME=${TOP} + +MAP_ARGS = --smart +FIT_ARGS = +ASM_ARGS = +STA_ARGS = +CPF_ARGS = -c -q 1MHZ -g 3.3 -n p + +GEN_VSRCS=${IPS:%.vhdl=${BUILD}/%.vhd} +QIP=${GEN_VSRCS:%.vhd=%.qip} + +BASE=${BUILD}/${DESIGN_NAME} +QSF=${BASE}.qsf +QPF=${BASE}.qpf +MAP=${BUILD}/${OF}/$(PROJECT).map.rpt +FIT=${BUILD}/${OF}/$(PROJECT).fit.rpt +ASM=${BUILD}/${OF}/$(PROJECT).asm.rpt +ASM=${BUILD}/${OF}/$(PROJECT).sta.rpt +SOF=${BUILD}/${OF}/${PROJECT}.sof +SVF=${BUILD}/${PROJECT}.svf + +default:${SVF} + + +${BUILD}/%.vhd ${BUILD}/%.qip:%.vhdl + cat $< > ${BUILD}/${<:%.vhdl=%.vhd} + (cd ${BUILD} && run_quartus qmegawiz -silent $(call relpath,${BUILD}/${<:%.vhdl=%.vhd},${BUILD})) + + +${QSF}: ${PRJ} ${DESIGN_NAME}.qsf_template + mkdir -p ${BUILD} + rm -f $@ + echo 'set_global_assignment -name TOP_LEVEL_ENTITY ${TOP}' >> $@ + echo 'set_global_assignment -name FAMILY "${FAMILY}"' >> $@ + echo 'set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ${OF}' >> $@ + echo 'set_global_assignment -name DEVICE ${PART}' >> $@ + cat ${DESIGN_NAME}.qsf_template >> $@ + for file in ${GEN_VSRCS} ${VSRCS}; do \ + echo "set_global_assignment -name VHDL_FILE $$(realpath -m --relative-to=${BUILD} $${file})" >> $@; \ + done + + + +${QPF}: + mkdir -p ${BUILD} + rm -f $@ + echo 'PROJECT_REVISION = "${TOP}"' > $@ + + +map: ${MAP} +${MAP}: ${VSRCS} ${QPF} ${QSF} ${GEN_VSRCS} ${QIP} + (cd ${BUILD} && run_quartus quartus_map $(MAP_ARGS) ${PROJECT}) + +fit: ${FIT} +${FIT}:${MAP} + (cd ${BUILD} && run_quartus quartus_fit $(FIT_ARGS) $(PROJECT)) + +asm: ${ASM} +sof: ${ASM} +${SOF} ${ASM}:${FIT} + (cd ${BUILD} && run_quartus quartus_asm $(ASM_ARGS) $(PROJECT)) + +sta: ${STA} +${STA}:${FIT} + (cd ${BUILD} && run_quartus quartus_sta $(STA_ARGS) $(PROJECT)) + + +svf:${SVF} +${SVF}:${SOF} + (cd ${BUILD} && run_quartus quartus_cpf ${CPF_ARGS} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) ) + + + +tidy: + git diff --exit-code -s ${VSRCS} + for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done + + + +# +# +##OPENOCD=openocd -f interface/altera-usb-blaster.cfg -f cpld/altera-epm240.cfg +# +#FIT_ARGS = +#ASM_ARGS = +# +#SVF=${PROJECT}.svf +# +# +# +#default: ${SVF} +# +#${SVF}: ${BUILD}/${PROJECT}.svf +# cat $< > $@ || /bin/rm -f $@ +# +#program: ${SVF} +# ${OPENOCD} -c "init; svf $<; exit" +# +#all: ${BUILD}/$(PROJECT).asm.rpt ${BUILD}/$(PROJECT).sta.rpt ${BUILD}/${PROJECT}.svf +# +clean: + rm -rf db ${BUILD} *.orig *.bak incremental_db db + +# +# +# +# +# +# + +#tidy: +# for i in ${SOURCE_FILES}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done +# +# diff --git a/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl b/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl new file mode 100644 index 0000000..6caaa8d --- /dev/null +++ b/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl @@ -0,0 +1,80 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.all; + +entity clkgen is + port ( + sys_rst_n : in std_logic; + clk_in : in std_logic; + i_clk : out std_logic; + o_clk : out std_logic; + o_clk_x2 : out std_logic; + o_clk_x10 : out std_logic; + locked : out std_logic + ); +end clkgen; +architecture Behavioural of clkgen is + + signal clkfbout : std_logic; + signal clk_200m : std_logic; + signal clk_80m : std_logic; + signal clk_40m : std_logic; + signal clk_20m : std_logic; + signal pll_locked : std_logic; + + signal reset : std_logic; +begin + +-- pll : PLL_BASE generic map ( +-- CLKIN_PERIOD => 20.0, +-- CLKFBOUT_MULT => 8, +-- CLKOUT0_DIVIDE => 2, +-- CLKOUT1_DIVIDE => 5, +-- CLKOUT2_DIVIDE => 10, +-- CLKOUT3_DIVIDE => 20, +-- COMPENSATION => "INTERNAL") +-- port map ( +-- CLKFBOUT => clkfbout, +-- CLKOUT0 => clk_200m, +-- CLKOUT1 => clk_80m, +-- CLKOUT2 => clk_40m, +-- CLKOUT3 => clk_20m, +-- LOCKED => pll_locked, +-- CLKFBIN => clkfbout, +-- CLKIN => clk_in, +-- RST => reset); +-- +-- reset <= (not pll_locked) or (not sys_rst_n); +-- +-- +-- +-- o_clk_buf : BUFG port map ( +-- I => clk_20m, +-- O => o_clk); +-- +-- +-- o_clk_x2_buf : BUFG port map ( +-- I => clk_40m, +-- O => o_clk_x2); +-- +-- +-- i_clk_buf : BUFG port map ( +-- I => clk_80m, +-- O => i_clk); +-- +-- o_clk_x10 <= clk_200m; +-- +-- locked <= pll_locked; + + + +i_clk <= clk_in; +o_clk <= clk_in; +o_clk_x2 <= clk_in; +o_clk_x10 <= clk_in; +locked <= '1'; + + + +end Behavioural; diff --git a/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl b/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl index f12c9c4..f3ae134 100644 --- a/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl +++ b/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl @@ -6,7 +6,7 @@ use work.all; library UNISIM; use UNISIM.vcomponents.all; -entity clkgen_spartan6 is +entity clkgen is port ( sys_rst_n : in std_logic; clk_in : in std_logic; @@ -16,8 +16,8 @@ entity clkgen_spartan6 is o_clk_x10 : out std_logic; locked : out std_logic ); -end clkgen_spartan6; -architecture Behavioural of clkgen_spartan6 is +end clkgen; +architecture Behavioural of clkgen is signal clkfbout : std_logic; signal clk_200m : std_logic; diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.qsf_template b/spartan6/hp_lcd_driver/hp_lcd_driver.qsf_template new file mode 100644 index 0000000..19aca2e --- /dev/null +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.qsf_template @@ -0,0 +1,51 @@ +#set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +#set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:47:00 APRIL 20, 2025" +#set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" + +set_parameter -name target "cyclone4" + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" + +#set_location_assignment PIN_T22 -to clk_50m +#set_location_assignment PIN_U20 -to sys_rst_n +# +# +#set_location_assignment PIN_H22 -to hdmi_clk_n +#set_location_assignment PIN_H21 -to hdmi_clk_p +# +##set_location_assignment PIN_F22 -to hdmi_red_n +##set_location_assignment PIN_E22 -to hdmi_green_n +##set_location_assignment PIN_D22 -to hdmi_blue_n +# +#set_location_assignment PIN_F21 -to hdmi_red +#set_location_assignment PIN_E21 -to hdmi_green +#set_location_assignment PIN_D21 -to hdmi_blue +# +# +#set_location_assignment PIN_N22 -to hdmi_ddc_scl +#set_location_assignment PIN_R22 -to hdmi_ddc_sda +# +# +# +#set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk +#set_instance_assignment -name IO_STANDARD LVDS -to hdmi_red +#set_instance_assignment -name IO_STANDARD LVDS -to hdmi_green +#set_instance_assignment -name IO_STANDARD LVDS -to hdmi_blue +# +# +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + + + diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl index 53c3e5f..697e90a 100644 --- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl @@ -32,7 +32,7 @@ architecture Behavioral of hp_lcd_driver is signal wr_addr : std_logic_vector(addr_width-1 downto 0); signal wr_data : std_logic_vector(video_width-1 downto 0); - signal wr_en : std_logic_vector(0 downto 0); + signal wr_en : std_logic; signal rd_addr : std_logic_vector(addr_width-1 downto 0); signal rd_data : std_logic_vector(video_width-1 downto 0); @@ -55,7 +55,7 @@ architecture Behavioral of hp_lcd_driver is begin - clkgen : entity work.clkgen_spartan6 + clkgen : entity work.clkgen port map ( sys_rst_n => sys_rst_n, clk_in => clk_50m, @@ -66,7 +66,6 @@ begin locked => clk_locked ); - input0 : entity work.input_stage generic map( video_width => video_width, @@ -88,18 +87,22 @@ begin vsync_in => vsync_in, video_out => wr_data, addr_out => wr_addr, - wren_out => wr_en(0)); + wren_out => wr_en); - VRAM0 : entity work.vram + vram0 : entity work.vram + generic map ( + video_width => video_width, + addr_width => addr_width + ) port map ( - clka => i_clk, - wea => wr_en, - addra => wr_addr, - dina => wr_data, - clkb => o_clk, - addrb => rd_addr, - doutb => rd_data + wr_clk => i_clk, + wr_en => wr_en, + wr_addr => wr_addr, + wr_data => wr_data, + rd_clk => o_clk, + rd_addr => rd_addr, + rd_data => rd_data ); diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl index 49b7679..6eef0b0 100644 --- a/spartan6/hp_lcd_driver/output_stage.vhdl +++ b/spartan6/hp_lcd_driver/output_stage.vhdl @@ -2,10 +2,6 @@ library ieee; use ieee.std_logic_1164.all; use IEEE.NUMERIC_STD.all; -library UNISIM; -use UNISIM.vcomponents.all; - - entity output_stage is generic (target : string := "spartan6"; debounce_stages : natural := 2; @@ -164,8 +160,7 @@ begin ); - - tmds_o : entity work.tmds_output_spartan6 + tmds_o : entity work.tmds_output port map ( sys_rst_n => sys_rst_n, pclk_locked => clk_locked, @@ -188,7 +183,63 @@ begin tmds_b_out_n => hdmi_b_n ); - +-- +-- g_tmds_o_s6: if target = "qspartan6" generate +-- +-- tmds_o : entity work.tmds_output_spartan6 +-- port map ( +-- sys_rst_n => sys_rst_n, +-- pclk_locked => clk_locked, +-- pclk => clk, +-- pclk_x2 => clk_x2, +-- pclk_x10 => clk_x10, +-- +-- r_p10 => r_p10, +-- g_p10 => g_p10, +-- b_p10 => b_p10, +-- c_p10 => c_p10, +-- +-- tmds_c_out_p => hdmi_c_p, +-- tmds_c_out_n => hdmi_c_n, +-- tmds_r_out_p => hdmi_r_p, +-- tmds_r_out_n => hdmi_r_n, +-- tmds_g_out_p => hdmi_g_p, +-- tmds_g_out_n => hdmi_g_n, +-- tmds_b_out_p => hdmi_b_p, +-- tmds_b_out_n => hdmi_b_n +-- ); +-- +-- end generate g_tmds_o_s6; +-- +-- g_tmds_o_c4:if target = "qcyclone4" generate +-- +-- tmds_o : entity work.tmds_output_cyclone4 +-- port map ( +-- sys_rst_n => sys_rst_n, +-- pclk_locked => clk_locked, +-- pclk => clk, +-- pclk_x2 => clk_x2, +-- pclk_x10 => clk_x10, +-- +-- r_p10 => r_p10, +-- g_p10 => g_p10, +-- b_p10 => b_p10, +-- c_p10 => c_p10, +-- +-- tmds_c_out_p => hdmi_c_p, +-- tmds_c_out_n => hdmi_c_n, +-- tmds_r_out_p => hdmi_r_p, +-- tmds_r_out_n => hdmi_r_n, +-- tmds_g_out_p => hdmi_g_p, +-- tmds_g_out_n => hdmi_g_n, +-- tmds_b_out_p => hdmi_b_p, +-- tmds_b_out_n => hdmi_b_n +-- ); +-- +-- +-- end generate g_tmds_o_c4; +-- +-- diff --git a/spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl b/spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl index dec3c9a..01fc578 100644 --- a/spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl +++ b/spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl @@ -6,7 +6,7 @@ library UNISIM; use UNISIM.vcomponents.all; -entity serdes_n_to_1 is +entity serdes_n_to_1_spartan6 is generic ( SF : natural := 8 ); @@ -19,10 +19,10 @@ entity serdes_n_to_1 is datain : in std_logic_vector(SF-1 downto 0); iob_data_out : out std_logic ); -end serdes_n_to_1; +end serdes_n_to_1_spartan6; -architecture beh of serdes_n_to_1 is +architecture beh of serdes_n_to_1_spartan6 is signal cascade_di : std_logic; signal cascade_do : std_logic; diff --git a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl new file mode 100644 index 0000000..401c4ec --- /dev/null +++ b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl @@ -0,0 +1,125 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; + +entity tmds_output is + port ( + sys_rst_n : in std_logic; + pclk_locked : in std_logic; + pclk : in std_logic; + pclk_x2 : in std_logic; + pclk_x10 : in std_logic; + + r_p10 : in std_logic_vector(9 downto 0); + g_p10 : in std_logic_vector(9 downto 0); + b_p10 : in std_logic_vector(9 downto 0); + c_p10 : in std_logic_vector(9 downto 0); + + + tmds_c_out_p : out std_logic; + tmds_c_out_n : out std_logic; + tmds_r_out_p : out std_logic; + tmds_r_out_n : out std_logic; + tmds_g_out_p : out std_logic; + tmds_g_out_n : out std_logic; + tmds_b_out_p : out std_logic; + tmds_b_out_n : out std_logic + ); +end tmds_output; + + +architecture beh of tmds_output is + + + signal phy_reset : std_logic; + signal upper : std_logic; + signal pll_locked : std_logic; + signal ioclk : std_logic; + signal serdesstrobe : std_logic; + +begin +-- phy_reset <= not sys_rst_n or not pll_locked; +-- +-- process (pclk_x2, phy_reset) +-- begin +-- if phy_reset = '1' then +-- upper <= '1'; +-- elsif rising_edge(pclk_x2) then +-- upper <= not upper; +-- end if; +-- end process; +-- +-- +-- ioclk_buf : BUFPLL generic map (DIVIDE => 5) +-- port map ( +-- PLLIN => pclk_x10, +-- GCLK => pclk_x2, +-- LOCKED => pclk_locked, +-- IOCLK => ioclk, +-- SERDESSTROBE => serdesstrobe, +-- LOCK => pll_locked); +-- +-- +-- phy_c : entity work.tmds_phy_spartan6 +-- port map ( +-- reset => phy_reset, +-- pclk_x2 => pclk_x2, +-- serdesstrobe => serdesstrobe, +-- ioclk => ioclk, +-- upper => upper, +-- din => c_p10, +-- tmds_out_p => tmds_c_out_p, +-- tmds_out_n => tmds_c_out_n +-- ); +-- +-- phy_r : entity work.tmds_phy_spartan6 +-- port map ( +-- reset => phy_reset, +-- pclk_x2 => pclk_x2, +-- serdesstrobe => serdesstrobe, +-- ioclk => ioclk, +-- upper => upper, +-- din => r_p10, +-- tmds_out_p => tmds_r_out_p, +-- tmds_out_n => tmds_r_out_n +-- ); +-- +-- +-- phy_g : entity work.tmds_phy_spartan6 +-- port map ( +-- reset => phy_reset, +-- pclk_x2 => pclk_x2, +-- serdesstrobe => serdesstrobe, +-- ioclk => ioclk, +-- upper => upper, +-- din => g_p10, +-- tmds_out_p => tmds_g_out_p, +-- tmds_out_n => tmds_g_out_n +-- ); +-- +-- +-- phy_b : entity work.tmds_phy_spartan6 +-- port map ( +-- reset => phy_reset, +-- pclk_x2 => pclk_x2, +-- serdesstrobe => serdesstrobe, +-- ioclk => pclk_x10, +-- upper => upper, +-- din => b_p10, +-- tmds_out_p => tmds_b_out_p, +-- tmds_out_n => tmds_b_out_n +-- ); +-- +-- +-- + + tmds_c_out_p <= '1'; + tmds_c_out_n <= '0'; + tmds_r_out_p <= '1'; + tmds_r_out_n <= '0'; + tmds_g_out_p <= '1'; + tmds_g_out_n <= '0'; + tmds_b_out_p <= '1'; + tmds_b_out_n <= '0'; + +end beh; diff --git a/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl b/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl index fc0aba2..f0304ef 100644 --- a/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl +++ b/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl @@ -6,7 +6,7 @@ library UNISIM; use UNISIM.vcomponents.all; -entity tmds_output_spartan6 is +entity tmds_output is port ( sys_rst_n : in std_logic; pclk_locked : in std_logic; @@ -29,10 +29,10 @@ entity tmds_output_spartan6 is tmds_b_out_p : out std_logic; tmds_b_out_n : out std_logic ); -end tmds_output_spartan6; +end tmds_output; -architecture beh of tmds_output_spartan6 is +architecture beh of tmds_output is signal phy_reset : std_logic; @@ -64,7 +64,7 @@ begin LOCK => pll_locked); - phy_c : entity work.tmds_phy + phy_c : entity work.tmds_phy_spartan6 port map ( reset => phy_reset, pclk_x2 => pclk_x2, @@ -76,7 +76,7 @@ begin tmds_out_n => tmds_c_out_n ); - phy_r : entity work.tmds_phy + phy_r : entity work.tmds_phy_spartan6 port map ( reset => phy_reset, pclk_x2 => pclk_x2, @@ -89,7 +89,7 @@ begin ); - phy_g : entity work.tmds_phy + phy_g : entity work.tmds_phy_spartan6 port map ( reset => phy_reset, pclk_x2 => pclk_x2, @@ -102,7 +102,7 @@ begin ); - phy_b : entity work.tmds_phy + phy_b : entity work.tmds_phy_spartan6 port map ( reset => phy_reset, pclk_x2 => pclk_x2, diff --git a/spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl b/spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl index 9b31e58..1f3d77e 100644 --- a/spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl +++ b/spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl @@ -5,7 +5,7 @@ use IEEE.NUMERIC_STD.all; library UNISIM; use UNISIM.vcomponents.all; -entity tmds_phy is +entity tmds_phy_spartan6 is port ( reset : in std_logic; pclk_x2 : in std_logic; @@ -16,10 +16,10 @@ entity tmds_phy is tmds_out_p : out std_logic; tmds_out_n : out std_logic ); -end tmds_phy; +end tmds_phy_spartan6; -architecture beh of tmds_phy is +architecture beh of tmds_phy_spartan6 is signal din_s : std_logic_vector(9 downto 0); signal p5_n : std_logic_vector(4 downto 0); @@ -44,7 +44,7 @@ begin end process; - serdes : entity work.serdes_n_to_1 + serdes : entity work.serdes_n_to_1_spartan6 generic map(SF => 5) port map ( ioclk => ioclk, diff --git a/spartan6/hp_lcd_driver/vram_cyclone4.vhdl b/spartan6/hp_lcd_driver/vram_cyclone4.vhdl new file mode 100644 index 0000000..4ccfc73 --- /dev/null +++ b/spartan6/hp_lcd_driver/vram_cyclone4.vhdl @@ -0,0 +1,35 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY vram IS + generic ( + addr_width:natural :=17; + video_width:natural :=2 + ); + PORT ( + wr_clk: in std_logic; + wr_en : in std_logic; + wr_addr : in STD_LOGIC_VECTOR(addr_width-1 downto 0); + wr_data : in std_logic_vector(video_width-1 downto 0); + rd_clk : in std_logic; + rd_addr : in STD_LOGIC_VECTOR(addr_width-1 downto 0); + rd_data : out std_logic_vector(video_width-1 downto 0) + ); +END vram; + +ARCHITECTURE beh OF vram IS +BEGIN + + + +vram_impl0: entity work.vram_cyclone4_impl + port map ( + wrclock => wr_clk, + wren => wr_en, + wraddress => wr_addr, + data => wr_data, + rdclock => rd_clk, + q => rd_data, + rdaddress => rd_addr + ); +END beh; diff --git a/spartan6/hp_lcd_driver/vram_cyclone4_impl.vhdl b/spartan6/hp_lcd_driver/vram_cyclone4_impl.vhdl new file mode 100644 index 0000000..aea5b80 --- /dev/null +++ b/spartan6/hp_lcd_driver/vram_cyclone4_impl.vhdl @@ -0,0 +1,231 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: vram_cyclone4_impl.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY vram_cyclone4_impl IS + PORT + ( + data : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + rdclock : IN STD_LOGIC ; + wraddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + wrclock : IN STD_LOGIC := '1'; + wren : IN STD_LOGIC := '0'; + q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END vram_cyclone4_impl; + + +ARCHITECTURE SYN OF vram_cyclone4_impl IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_aclr_b : STRING; + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_b : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_b : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + clock0 : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + wren_a : IN STD_LOGIC ; + address_b : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + clock1 : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_b => "NONE", + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "Cyclone IV E", + lpm_type => "altsyncram", + numwords_a => 228096, + numwords_b => 228096, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + widthad_a => 18, + widthad_b => 18, + width_a => 2, + width_b => 2, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => wraddress, + clock0 => wrclock, + data_a => data, + wren_a => wren, + address_b => rdaddress, + clock1 => rdclock, + q_b => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "1" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "456192" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "2" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "2" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "2" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "2" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "228096" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "228096" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "18" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "18" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "2" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "2" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]" +-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 18 0 INPUT NODEFVAL "rdaddress[17..0]" +-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock" +-- Retrieval info: USED_PORT: wraddress 0 0 18 0 INPUT NODEFVAL "wraddress[17..0]" +-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 18 0 wraddress 0 0 18 0 +-- Retrieval info: CONNECT: @address_b 0 0 18 0 rdaddress 0 0 18 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 2 0 data 0 0 2 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 2 0 @q_b 0 0 2 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.vhd FALSE diff --git a/spartan6/hp_lcd_driver/vram_spartan6_impl.xco b/spartan6/hp_lcd_driver/vram_spartan6_impl.xco index f4624c4..131955a 100644 --- a/spartan6/hp_lcd_driver/vram_spartan6_impl.xco +++ b/spartan6/hp_lcd_driver/vram_spartan6_impl.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version 14.7 -# Date: Sat Apr 26 13:15:00 2025 +# Date: Mon Apr 28 10:29:36 2025 # ############################################################## # @@ -48,7 +48,7 @@ CSET axi_type=AXI4_Full CSET byte_size=9 CSET coe_file=no_coe_file_loaded CSET collision_warnings=ALL -CSET component_name=vram +CSET component_name=vram_spartan6_impl CSET disable_collision_warnings=false CSET disable_out_of_range_warnings=false CSET ecc=false @@ -105,4 +105,4 @@ CSET write_width_b=2 MISC pkg_timestamp=2012-11-19T16:22:25Z # END Extra information GENERATE -# CRC: 74d82cad +# CRC: 10ea0a8c |