diff options
| -rw-r--r-- | spartan6/hp_lcd_driver/Makefile.cyclone4 | 4 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl | 57 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/clkgen_spartan6.vhdl | 4 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.qsf_template | 46 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.vhdl | 6 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/output_stage.vhdl | 62 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl | 149 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl | 6 |
8 files changed, 125 insertions, 209 deletions
diff --git a/spartan6/hp_lcd_driver/Makefile.cyclone4 b/spartan6/hp_lcd_driver/Makefile.cyclone4 index 5184c7c..1bdeaf8 100644 --- a/spartan6/hp_lcd_driver/Makefile.cyclone4 +++ b/spartan6/hp_lcd_driver/Makefile.cyclone4 @@ -7,8 +7,8 @@ BUILD=build_cyclone4 OF=output_files PROJECT = hp_lcd_driver -VSRCS =synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_output_cyclone4.vhdl output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl -IPS= vram_cyclone4_impl.vhdl +VSRCS =synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl +IPS= vram_cyclone4_impl.vhdl clkgen_cyclone4_impl.vhdl DESIGN_NAME=${TOP} diff --git a/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl b/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl index e1a9c58..7869b01 100644 --- a/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl +++ b/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl @@ -10,14 +10,14 @@ entity clkgen is i_clk : out std_logic; o_clk : out std_logic; o_clk_x2 : out std_logic; - o_clk_x10 : out std_logic; + o_clk_phy : out std_logic; locked : out std_logic ); end clkgen; architecture Behavioural of clkgen is signal clkfbout : std_logic; - signal clk_200m : std_logic; + signal clk_100m : std_logic; signal clk_80m : std_logic; signal clk_40m : std_logic; signal clk_20m : std_logic; @@ -26,55 +26,38 @@ architecture Behavioural of clkgen is signal reset : std_logic; begin --- pll : PLL_BASE generic map ( --- CLKIN_PERIOD => 20.0, --- CLKFBOUT_MULT => 8, --- CLKOUT0_DIVIDE => 2, --- CLKOUT1_DIVIDE => 5, --- CLKOUT2_DIVIDE => 10, --- CLKOUT3_DIVIDE => 20, --- COMPENSATION => "INTERNAL") --- port map ( --- CLKFBOUT => clkfbout, --- CLKOUT0 => clk_200m, --- CLKOUT1 => clk_80m, --- CLKOUT2 => clk_40m, --- CLKOUT3 => clk_20m, --- LOCKED => pll_locked, --- CLKFBIN => clkfbout, --- CLKIN => clk_in, --- RST => reset); --- --- reset <= (not pll_locked) or (not sys_rst_n); --- --- --- +clkgen_impl0: entity work.clkgen_cyclone4_impl + port map ( + areset => not sys_rst_n, + inclk0 => clk_in, + c0 => clk_100m, + c1 => clk_80m, + c2 => clk_40m, + c3 => clk_20m, + locked => pll_locked); + + o_clk <= clk_20m; -- o_clk_buf : BUFG port map ( -- I => clk_20m, -- O => o_clk); -- --- + + o_clk_x2 <= clk_40m; + -- o_clk_x2_buf : BUFG port map ( -- I => clk_40m, -- O => o_clk_x2); -- --- + + i_clk <= clk_80m; -- i_clk_buf : BUFG port map ( -- I => clk_80m, -- O => i_clk); -- --- o_clk_x10 <= clk_200m; --- --- locked <= pll_locked; - - - i_clk <= clk_in; - o_clk <= clk_in; - o_clk_x2 <= clk_in; - o_clk_x10 <= clk_in; - locked <= '1'; + o_clk_phy <= clk_100m; + locked <= pll_locked; end Behavioural; diff --git a/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl b/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl index f3ae134..7240abc 100644 --- a/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl +++ b/spartan6/hp_lcd_driver/clkgen_spartan6.vhdl @@ -13,7 +13,7 @@ entity clkgen is i_clk : out std_logic; o_clk : out std_logic; o_clk_x2 : out std_logic; - o_clk_x10 : out std_logic; + o_clk_phy : out std_logic; locked : out std_logic ); end clkgen; @@ -66,7 +66,7 @@ begin I => clk_80m, O => i_clk); - o_clk_x10 <= clk_200m; + o_clk_phy <= clk_200m; locked <= pll_locked; diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.qsf_template b/spartan6/hp_lcd_driver/hp_lcd_driver.qsf_template index 19aca2e..d333c5b 100644 --- a/spartan6/hp_lcd_driver/hp_lcd_driver.qsf_template +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.qsf_template @@ -21,18 +21,7 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" #set_location_assignment PIN_U20 -to sys_rst_n # # -#set_location_assignment PIN_H22 -to hdmi_clk_n -#set_location_assignment PIN_H21 -to hdmi_clk_p -# -##set_location_assignment PIN_F22 -to hdmi_red_n -##set_location_assignment PIN_E22 -to hdmi_green_n -##set_location_assignment PIN_D22 -to hdmi_blue_n -# -#set_location_assignment PIN_F21 -to hdmi_red -#set_location_assignment PIN_E21 -to hdmi_green -#set_location_assignment PIN_D21 -to hdmi_blue -# -# + #set_location_assignment PIN_N22 -to hdmi_ddc_scl #set_location_assignment PIN_R22 -to hdmi_ddc_sda # @@ -46,6 +35,39 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" # set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_location_assignment PIN_T22 -to clk_50m +set_location_assignment PIN_U20 -to sys_rst_n + +set_location_assignment PIN_H21 -to hdmi_c_p +set_location_assignment PIN_H22 -to hdmi_c_n + +set_location_assignment PIN_F21 -to hdmi_r_p +set_location_assignment PIN_F22 -to hdmi_r_n + +set_location_assignment PIN_E21 -to hdmi_g_p +set_location_assignment PIN_E22 -to hdmi_g_n + +set_location_assignment PIN_D21 -to hdmi_b_p +set_location_assignment PIN_D22 -to hdmi_b_n + +set_location_assignment PIN_AB17 -to vsync_out +set_location_assignment PIN_AA18 -to hsync_out +set_location_assignment PIN_J21 -to r_out +#set_location_assignment PIN_K21 -to rgb[14] +#set_location_assignment PIN_L22 -to rgb[13] +#set_location_assignment PIN_L21 -to rgb[12] +#set_location_assignment PIN_M22 -to rgb[11] +set_location_assignment PIN_M21 -to g_out +#set_location_assignment PIN_N21 -to rgb[9] +#set_location_assignment PIN_N20 -to rgb[8] +#set_location_assignment PIN_U22 -to rgb[7] +#set_location_assignment PIN_U21 -to rgb[6] +#set_location_assignment PIN_W20 -to rgb[5] +set_location_assignment PIN_W19 -to b_out +#set_location_assignment PIN_Y21 -to rgb[3] +#set_location_assignment PIN_AB19 -to rgb[2] +#set_location_assignment PIN_AA19 -to rgb[1] +#set_location_assignment PIN_AB18 -to rgb[0] diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl index 4d82d86..a16b193 100644 --- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl @@ -48,7 +48,7 @@ architecture Behavioral of hp_lcd_driver is signal o_clk : std_logic; signal o_clk_x2 : std_logic; - signal o_clk_x10 : std_logic; + signal o_clk_phy : std_logic; signal sys_rst : std_logic; @@ -62,7 +62,7 @@ begin i_clk => i_clk, o_clk => o_clk, o_clk_x2 => o_clk_x2, - o_clk_x10 => o_clk_x10, + o_clk_phy => o_clk_phy, locked => clk_locked ); @@ -137,7 +137,7 @@ begin clk_locked => clk_locked, clk => o_clk, clk_x2 => o_clk_x2, - clk_x10 => o_clk_x10, + clk_phy => o_clk_phy, sys_rst_n => sys_rst_n, vsync_in => vsync_in, r_in => r, diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl index 6eef0b0..8dc91ae 100644 --- a/spartan6/hp_lcd_driver/output_stage.vhdl +++ b/spartan6/hp_lcd_driver/output_stage.vhdl @@ -24,7 +24,7 @@ entity output_stage is clk_locked : in std_logic; clk : in std_logic; clk_x2 : in std_logic; - clk_x10 : in std_logic; + clk_phy : in std_logic; sys_rst_n : in std_logic; vsync_in : in std_logic; @@ -166,7 +166,7 @@ begin pclk_locked => clk_locked, pclk => clk, pclk_x2 => clk_x2, - pclk_x10 => clk_x10, + pclk_phy => clk_phy, r_p10 => r_p10, g_p10 => g_p10, @@ -183,64 +183,6 @@ begin tmds_b_out_n => hdmi_b_n ); --- --- g_tmds_o_s6: if target = "qspartan6" generate --- --- tmds_o : entity work.tmds_output_spartan6 --- port map ( --- sys_rst_n => sys_rst_n, --- pclk_locked => clk_locked, --- pclk => clk, --- pclk_x2 => clk_x2, --- pclk_x10 => clk_x10, --- --- r_p10 => r_p10, --- g_p10 => g_p10, --- b_p10 => b_p10, --- c_p10 => c_p10, --- --- tmds_c_out_p => hdmi_c_p, --- tmds_c_out_n => hdmi_c_n, --- tmds_r_out_p => hdmi_r_p, --- tmds_r_out_n => hdmi_r_n, --- tmds_g_out_p => hdmi_g_p, --- tmds_g_out_n => hdmi_g_n, --- tmds_b_out_p => hdmi_b_p, --- tmds_b_out_n => hdmi_b_n --- ); --- --- end generate g_tmds_o_s6; --- --- g_tmds_o_c4:if target = "qcyclone4" generate --- --- tmds_o : entity work.tmds_output_cyclone4 --- port map ( --- sys_rst_n => sys_rst_n, --- pclk_locked => clk_locked, --- pclk => clk, --- pclk_x2 => clk_x2, --- pclk_x10 => clk_x10, --- --- r_p10 => r_p10, --- g_p10 => g_p10, --- b_p10 => b_p10, --- c_p10 => c_p10, --- --- tmds_c_out_p => hdmi_c_p, --- tmds_c_out_n => hdmi_c_n, --- tmds_r_out_p => hdmi_r_p, --- tmds_r_out_n => hdmi_r_n, --- tmds_g_out_p => hdmi_g_p, --- tmds_g_out_n => hdmi_g_n, --- tmds_b_out_p => hdmi_b_p, --- tmds_b_out_n => hdmi_b_n --- ); --- --- --- end generate g_tmds_o_c4; --- --- - diff --git a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl index 60ddb6d..3ea07fe 100644 --- a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl +++ b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl @@ -8,7 +8,7 @@ entity tmds_output is pclk_locked : in std_logic; pclk : in std_logic; pclk_x2 : in std_logic; - pclk_x10 : in std_logic; + pclk_phy : in std_logic; r_p10 : in std_logic_vector(9 downto 0); g_p10 : in std_logic_vector(9 downto 0); @@ -30,96 +30,65 @@ end tmds_output; architecture beh of tmds_output is - - signal phy_reset : std_logic; - signal upper : std_logic; - signal pll_locked : std_logic; - signal ioclk : std_logic; - signal serdesstrobe : std_logic; + signal b: natural; begin --- phy_reset <= not sys_rst_n or not pll_locked; --- --- process (pclk_x2, phy_reset) --- begin --- if phy_reset = '1' then --- upper <= '1'; --- elsif rising_edge(pclk_x2) then --- upper <= not upper; --- end if; --- end process; --- --- --- ioclk_buf : BUFPLL generic map (DIVIDE => 5) --- port map ( --- PLLIN => pclk_x10, --- GCLK => pclk_x2, --- LOCKED => pclk_locked, --- IOCLK => ioclk, --- SERDESSTROBE => serdesstrobe, --- LOCK => pll_locked); --- --- --- phy_c : entity work.tmds_phy_spartan6 --- port map ( --- reset => phy_reset, --- pclk_x2 => pclk_x2, --- serdesstrobe => serdesstrobe, --- ioclk => ioclk, --- upper => upper, --- din => c_p10, --- tmds_out_p => tmds_c_out_p, --- tmds_out_n => tmds_c_out_n --- ); --- --- phy_r : entity work.tmds_phy_spartan6 --- port map ( --- reset => phy_reset, --- pclk_x2 => pclk_x2, --- serdesstrobe => serdesstrobe, --- ioclk => ioclk, --- upper => upper, --- din => r_p10, --- tmds_out_p => tmds_r_out_p, --- tmds_out_n => tmds_r_out_n --- ); --- --- --- phy_g : entity work.tmds_phy_spartan6 --- port map ( --- reset => phy_reset, --- pclk_x2 => pclk_x2, --- serdesstrobe => serdesstrobe, --- ioclk => ioclk, --- upper => upper, --- din => g_p10, --- tmds_out_p => tmds_g_out_p, --- tmds_out_n => tmds_g_out_n --- ); --- --- --- phy_b : entity work.tmds_phy_spartan6 --- port map ( --- reset => phy_reset, --- pclk_x2 => pclk_x2, --- serdesstrobe => serdesstrobe, --- ioclk => pclk_x10, --- upper => upper, --- din => b_p10, --- tmds_out_p => tmds_b_out_p, --- tmds_out_n => tmds_b_out_n --- ); --- --- --- - - tmds_c_out_p <= '1'; - tmds_c_out_n <= '0'; - tmds_r_out_p <= '1'; - tmds_r_out_n <= '0'; - tmds_g_out_p <= '1'; - tmds_g_out_n <= '0'; - tmds_b_out_p <= '1'; - tmds_b_out_n <= '0'; + + + + process (pclk_phy,b,sys_rst_n) begin + if sys_rst_n='1' then + b<=0; + elsif rising_edge(pclk_phy) then + if b=5 then + b<=0; + else + b<=b+1; + end if; + end if; + end process; + + + phy_c : entity work.tmds_phy_cyclone4 + port map ( + sys_rst_n => sys_rst_n, + pclk_phy => pclk_phy, + b =>b, + din => c_p10, + tmds_out_p => tmds_c_out_p, + tmds_out_n => tmds_c_out_n + ); + + phy_r : entity work.tmds_phy_cyclone4 + port map ( + sys_rst_n => sys_rst_n, + pclk_phy => pclk_phy, + b =>b, + din => r_p10, + tmds_out_p => tmds_r_out_p, + tmds_out_n => tmds_r_out_n + ); + + + phy_g : entity work.tmds_phy_cyclone4 + port map ( + sys_rst_n => sys_rst_n, + pclk_phy => pclk_phy, + b =>b, + din => g_p10, + tmds_out_p => tmds_g_out_p, + tmds_out_n => tmds_g_out_n + ); + + + phy_b : entity work.tmds_phy_cyclone4 + port map ( + sys_rst_n => sys_rst_n, + pclk_phy => pclk_phy, + b =>b, + din => b_p10, + tmds_out_p => tmds_b_out_p, + tmds_out_n => tmds_b_out_n + ); end beh; diff --git a/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl b/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl index f0304ef..9307563 100644 --- a/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl +++ b/spartan6/hp_lcd_driver/tmds_output_spartan6.vhdl @@ -12,7 +12,7 @@ entity tmds_output is pclk_locked : in std_logic; pclk : in std_logic; pclk_x2 : in std_logic; - pclk_x10 : in std_logic; + pclk_phy : in std_logic; r_p10 : in std_logic_vector(9 downto 0); g_p10 : in std_logic_vector(9 downto 0); @@ -56,7 +56,7 @@ begin ioclk_buf : BUFPLL generic map (DIVIDE => 5) port map ( - PLLIN => pclk_x10, + PLLIN => pclk_phy, GCLK => pclk_x2, LOCKED => pclk_locked, IOCLK => ioclk, @@ -107,7 +107,7 @@ begin reset => phy_reset, pclk_x2 => pclk_x2, serdesstrobe => serdesstrobe, - ioclk => pclk_x10, + ioclk => pclk_phy, upper => upper, din => b_p10, tmds_out_p => tmds_b_out_p, |