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-rw-r--r--fpga/ebaz4205/src/ebaz4205-zynq7.dts1
-rw-r--r--fpga/hp_lcd_driver/Makefile8
-rw-r--r--fpga/hp_lcd_driver/artix7.mk3
-rw-r--r--fpga/hp_lcd_driver/common.vhdl20
-rw-r--r--fpga/hp_lcd_driver/ebaz4205.xdc106
-rw-r--r--fpga/hp_lcd_driver/fifo_to_axi.vhdl8
-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.vhdl2
-rw-r--r--fpga/hp_lcd_driver/tmds_output_artix7.vhdl2
-rw-r--r--fpga/hp_lcd_driver/tmds_phy_artix7.vhdl8
-rw-r--r--fpga/hp_lcd_driver/vnc_serializer.vhdl45
-rw-r--r--fpga/hp_lcd_driver/zynq7.mk4
-rw-r--r--fpga/hp_lcd_driver/zynq7_wrapper.vhdl85
12 files changed, 197 insertions, 95 deletions
diff --git a/fpga/ebaz4205/src/ebaz4205-zynq7.dts b/fpga/ebaz4205/src/ebaz4205-zynq7.dts
index 0d3a7c1..9283b09 100644
--- a/fpga/ebaz4205/src/ebaz4205-zynq7.dts
+++ b/fpga/ebaz4205/src/ebaz4205-zynq7.dts
@@ -24,6 +24,7 @@
compatible = "jmm,video-capture-device";
status = "okay";
gpios = <&gpio0 56 0>;
+ reg = <0xfffc0000 0x40000>;
};
diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index 8c0c55d..6b72967 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -1,11 +1,13 @@
-TARGETS= ebaz4205 rando_a7 #smh-ac415b #spartan6 #ep4ce6 smh-ac415
+DIP=10.16.66.113
+TARGETS= ebaz4205 #rando_a7 #smh-ac415b #spartan6 #ep4ce6 smh-ac415
#fish:smh-ac415
#better_default: build_rando_a7/hp_lcd_driver.svf
# ./prog_a7
-#better_default: build_ebaz4205/out/hp_lcd_driver.bin
-# scp build_ebaz4205/out/hp_lcd_driver.bin 10.16.66.163:/boot/uboot/hp_lcd_driver.bin
+better_default: ${TARGETS:%=build_%/hp_lcd_driver.svf}
+ scp build_ebaz4205/out/hp_lcd_driver.bin ${DIP}:/boot/uboot/hp_lcd_driver.bin
+ ssh -n ${DIP} reboot < /dev/null &
default: ${TARGETS:%=build_%/hp_lcd_driver.svf}
diff --git a/fpga/hp_lcd_driver/artix7.mk b/fpga/hp_lcd_driver/artix7.mk
index 218797c..c20c11d 100644
--- a/fpga/hp_lcd_driver/artix7.mk
+++ b/fpga/hp_lcd_driver/artix7.mk
@@ -51,3 +51,6 @@ ${BUILD}/ip/%/stamp:artix7_ip/%.tcl
${BIT}: ${BUILD}/build.stamp
+
+clean:
+ /bin/rm -rf ${BUILD}
diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl
index df58203..7275184 100644
--- a/fpga/hp_lcd_driver/common.vhdl
+++ b/fpga/hp_lcd_driver/common.vhdl
@@ -84,8 +84,8 @@ architecture Behavioral of common is
signal c : natural;
signal t : std_logic;
-
- signal wr_index: std_logic;
+
+ signal wr_index : std_logic;
begin
@@ -250,19 +250,19 @@ begin
- r <=x"ff" when rd_data(0) = '1' else
- x"00";
+ r <= x"ff" when rd_data(0) = '1' else
+ x"00";
-- r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else
-- x"80" when rd_data(0)='1' else
-- x"00";
- g <=x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else
- x"80" when rd_data(1) = '1' else
- x"00";
- b <=x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else
- x"80" when rd_data(2) = '1' else
- x"00";
+ g <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else
+ x"80" when rd_data(1) = '1' else
+ x"00";
+ b <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else
+ x"80" when rd_data(2) = '1' else
+ x"00";
diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc
index f5e5c93..64660eb 100644
--- a/fpga/hp_lcd_driver/ebaz4205.xdc
+++ b/fpga/hp_lcd_driver/ebaz4205.xdc
@@ -33,14 +33,18 @@ set_property IOSTANDARD LVCMOS33 [get_ports *_led]
#set_property PACKAGE_PIN T1 [get_ports {led_1}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led_1}]
-set_property PACKAGE_PIN G19 [get_ports {hdmi_r_p}]; #data2-5
-set_property PACKAGE_PIN G20 [get_ports {hdmi_r_n}]; #data2-7
+set_property PACKAGE_PIN G19 [get_ports {hdmi_b_p}]; #data2-5
+set_property PACKAGE_PIN G20 [get_ports {hdmi_b_n}]; #data2-7
set_property PACKAGE_PIN K19 [get_ports {hdmi_g_p}]; #data2-13
set_property PACKAGE_PIN J19 [get_ports {hdmi_g_n}]; #data2-9
-set_property PACKAGE_PIN L19 [get_ports {hdmi_b_p}]; #data2-16
-set_property PACKAGE_PIN L20 [get_ports {hdmi_b_n}]; #data2-18
+#set_property PACKAGE_PIN T20 [get_ports {hdmi_g_p}]; #data3-16
+#set_property PACKAGE_PIN U20 [get_ports {hdmi_g_n}]; #data3-17
+set_property PACKAGE_PIN L19 [get_ports {hdmi_r_p}]; #data2-16
+set_property PACKAGE_PIN L20 [get_ports {hdmi_r_n}]; #data2-18
set_property PACKAGE_PIN L16 [get_ports {hdmi_c_p}]; #data2-15
set_property PACKAGE_PIN L17 [get_ports {hdmi_c_n}]; #data2-20
+#set_property PACKAGE_PIN N17 [get_ports {hdmi_c_p}]; #data3-9
+#set_property PACKAGE_PIN P18 [get_ports {hdmi_c_n}]; #data3-7
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}]
@@ -59,7 +63,7 @@ set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}]
##set_property DRIVE 16 [get_ports {hdmi_g_n}]
##set_property DRIVE 16 [get_ports {hdmi_b_p}]
#
-set_property PACKAGE_PIN H20 [get_ports {hdmi_vcc}]; #data2-8
+set_property PACKAGE_PIN K18 [get_ports {hdmi_vcc}]; #data2-11 (12 is gnd)
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}]
#
#
@@ -72,14 +76,14 @@ set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}]
##set_property IOSTANDARD LVCMOS33 [get_ports key]
#
set_property PACKAGE_PIN A20 [get_ports {video[0]}]; #data1-5
-set_property PACKAGE_PIN B19 [get_ports {video[1]}]; #data1-7
-set_property PACKAGE_PIN C20 [get_ports {video[2]}]; #data1-9
-set_property PACKAGE_PIN H17 [get_ports {video[3]}]; #data1-11
+set_property PACKAGE_PIN H16 [get_ports {video[1]}]; #data1-6
+set_property PACKAGE_PIN B19 [get_ports {video[2]}]; #data1-7
+set_property PACKAGE_PIN B20 [get_ports {video[3]}]; #data1-8
set_property PACKAGE_PIN D20 [get_ports {video[4]}]; #data1-13
-set_property PACKAGE_PIN H18 [get_ports {video[5]}]; #data1-15
-set_property PACKAGE_PIN F20 [get_ports {video[6]}]; #data1-17
-set_property PACKAGE_PIN F19 [get_ports {video[7]}]; #data1-19
-#
+set_property PACKAGE_PIN D18 [get_ports {video[5]}]; #data1-14
+set_property PACKAGE_PIN H18 [get_ports {video[6]}]; #data1-15
+set_property PACKAGE_PIN D19 [get_ports {video[7]}]; #data1-16
+##
set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}]
@@ -89,9 +93,10 @@ set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
#
-set_property PACKAGE_PIN H16 [get_ports {pclk_in}]; #data1-6
-set_property PACKAGE_PIN D18 [get_ports {vsync_in}]; #data1-14
-set_property PACKAGE_PIN D19 [get_ports {hsync_in}]; #data1-16
+set_property PACKAGE_PIN H17 [get_ports {pclk_in}]; #data1-11 (12 is gnd)
+
+set_property PACKAGE_PIN F19 [get_ports {vsync_in}]; #data1-19
+set_property PACKAGE_PIN K17 [get_ports {hsync_in}]; #data1-20
#
#set_property PACKAGE_PIN P16 [get_ports {r_out}]
#set_property PACKAGE_PIN V18 [get_ports {g_out}]
@@ -119,7 +124,11 @@ set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}]
##set_false_path -from [get_ports pci_exp_rst_n]
#
-set_false_path -from [get_clocks clk_out4_mmcm_0] -to [get_clocks clk_out1_mmcm_0]
+#set_false_path -from [get_clocks clk_out4_mmcm_0] -to [get_clocks clk_out1_mmcm_0]
+#
+
+
+exit
@@ -138,5 +147,70 @@ set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
+set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[*]/D}] 9
+set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[*]/D}] 9
+set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[*]/D}] 9
+set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[*]/D}] 9
+
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[0]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[0]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[0]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[0]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[1]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[1]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[1]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[1]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[2]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[2]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[2]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[2]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[3]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[3]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[3]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[3]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[4]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[4]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[4]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[4]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[5]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[5]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[5]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[5]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[6]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[6]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[6]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[6]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[7]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[7]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[7]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[7]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[8]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[8]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[8]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[8]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[9]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[9]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[9]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[9]/D}]
+#
+#
diff --git a/fpga/hp_lcd_driver/fifo_to_axi.vhdl b/fpga/hp_lcd_driver/fifo_to_axi.vhdl
index 64da115..c527ea1 100644
--- a/fpga/hp_lcd_driver/fifo_to_axi.vhdl
+++ b/fpga/hp_lcd_driver/fifo_to_axi.vhdl
@@ -87,10 +87,10 @@ begin
elsif do_bus_cycle = '0' then
if fifo_empty = '0' then
- data <= fifo_rdata (63 downto 0);
- if fifo_rdata(64)='1' then
- addr <= std_logic_vector(START);
- end if;
+ data <= fifo_rdata (63 downto 0);
+ if fifo_rdata(64) = '1' then
+ addr <= std_logic_vector(START);
+ end if;
fifo_rd_en <= '1';
do_bus_cycle <= '1';
axi_awvalid <= '1';
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index 491ccf3..15fe76f 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -71,7 +71,7 @@ begin
hdmi_vcc => hdmi_vcc,
i_clk_out => i_clk_out,
led => led,
- video_out_clk => open,
+ video_out_clk => open,
video_out_index => open,
video_out_data => open,
video_out_valid => open
diff --git a/fpga/hp_lcd_driver/tmds_output_artix7.vhdl b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl
index 6c91041..8749d3f 100644
--- a/fpga/hp_lcd_driver/tmds_output_artix7.vhdl
+++ b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl
@@ -35,7 +35,7 @@ end tmds_output;
architecture beh of tmds_output is
signal phy_reset : std_logic;
- signal b : natural := 0;
+ signal b : natural range 0 to 9:= 0;
begin
diff --git a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
index 8c8106e..604ec23 100644
--- a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
+++ b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
@@ -22,6 +22,7 @@ end tmds_phy_artix7;
architecture beh of tmds_phy_artix7 is
signal ld : std_logic_vector(9 downto 0);
+ signal ld2 : std_logic_vector(9 downto 0);
signal sr : std_logic_vector(9 downto 0);
signal s : std_logic;
@@ -32,7 +33,7 @@ begin
process(pix_clk)
begin
if rising_edge(pix_clk) then
- ld <= din;
+ ld2 <= din;
end if;
end process;
@@ -69,11 +70,14 @@ begin
process(phy_clk)
begin
if rising_edge(phy_clk) then
+ if b=5 then
+ ld<=ld2;
+ end if;
if b = 0 then
sr <= ld;
else
sr(8 downto 0) <= sr (9 downto 1);
- s <=sr(0);
+ s <= sr(0);
end if;
end if;
end process;
diff --git a/fpga/hp_lcd_driver/vnc_serializer.vhdl b/fpga/hp_lcd_driver/vnc_serializer.vhdl
index ce4b951..9ec89a8 100644
--- a/fpga/hp_lcd_driver/vnc_serializer.vhdl
+++ b/fpga/hp_lcd_driver/vnc_serializer.vhdl
@@ -18,38 +18,50 @@ end vnc_serializer;
architecture Behavioural of vnc_serializer is
- type REGS is array (0 to 7) of std_logic_vector(video_width -1 downto 0);
+ --type REGS is array (0 to 7) of std_logic_vector(video_width-1 downto 0);
+ type REGS is array (0 to 7) of std_logic_vector(7 downto 0);
signal reg : REGS;
signal i : natural := 0;
signal wren : std_logic;
signal next_index : std_logic;
- signal index : std_logic;
+ signal index : std_logic;
+ signal rgb : std_logic_vector(7 downto 0);
begin
+ rgb(2 downto 0) <= "111" when vnc_data(0)='1' else
+ "000";
+ rgb(5 downto 3) <= "111" when vnc_data(1)='1' and vnc_data(3)='1' else
+ "100" when vnc_data(1)='1' else
+ "000";
+ rgb(7 downto 6) <= "11" when vnc_data(2)='1' and vnc_data(3)='1' else
+ "10" when vnc_data(2)='1' else
+ "00";
+
+
process (clk)
begin
if rising_edge(clk) then
if vnc_valid = '1' then
if vnc_index = '1' then
- reg(0) <= vnc_data;
+ reg(0)<=rgb;
next_index <= '1';
- i <=1;
- wren <= '0';
+ i <= 1;
+ wren <= '0';
else
- reg(i) <= vnc_data;
+ reg(i) <=rgb;
if i /= 7 then
- i <=i+1;
+ i <= i+1;
wren <= '0';
else
- i <=0;
- wren <= '1';
- index <= next_index;
- next_index <= '0';
+ i <= 0;
+ wren <= '1';
+ index <= next_index;
+ next_index <= '0';
end if;
- end if;
+ end if;
else
- wren <= '0';
+ wren <= '0';
end if;
end if;
end process;
@@ -57,11 +69,12 @@ begin
g_j : for j in 0 to 7 generate
- fifo_data(((j*8)+video_width-1) downto (j*8)) <= reg(j);
- fifo_data(((j*8)+7) downto ((j*8)+video_width)) <= (others =>'0');
+-- fifo_data(((j*8)+video_width-1) downto (j*8)) <= reg(j);
+-- fifo_data(((j*8)+7) downto ((j*8)+video_width)) <= (others => '0');
+ fifo_data(((j*8)+7) downto (j*8)) <= reg(j);
end generate g_j;
- fifo_data(64)<=index;
+ fifo_data(64) <= index;
fifo_wren <= wren;
diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk
index c99e325..e6acad8 100644
--- a/fpga/hp_lcd_driver/zynq7.mk
+++ b/fpga/hp_lcd_driver/zynq7.mk
@@ -58,3 +58,7 @@ ${BUILD}/ip/%/stamp:zynq7_ip/%.tcl
${BIT}: ${BUILD}/build.stamp
+
+clean:
+ /bin/rm -rf ${BUILD}
+
diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
index 1fde3c8..529a1b1 100644
--- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
@@ -129,12 +129,12 @@ architecture arch of zynq7_wrapper is
signal fifo_rst_cnt : natural;
- signal fifo_rst: std_logic;
- signal fifo_wr_en : std_logic;
- signal fifo_wdata : std_logic_vector(64 downto 0);
- signal fifo_rd_en : std_logic;
- signal fifo_rdata : std_logic_vector(64 downto 0);
- signal fifo_empty : std_logic;
+ signal fifo_rst : std_logic;
+ signal fifo_wr_en : std_logic;
+ signal fifo_wdata : std_logic_vector(64 downto 0);
+ signal fifo_rd_en : std_logic;
+ signal fifo_rdata : std_logic_vector(64 downto 0);
+ signal fifo_empty : std_logic;
signal run : std_logic;
@@ -309,43 +309,44 @@ begin
vnc_serializer_i : entity work.vnc_serializer
- generic map (
- video_width => video_width
- )
- port map (
- clk => vnc_clk,
- vnc_valid => vnc_valid,
- vnc_data => vnc_data,
- vnc_index => vnc_index,
-
- fifo_data => fifo_wdata,
- fifo_wren => fifo_wr_en);
-
-
-process (clk_50m) begin
-if rising_edge(clk_50m) then
-if sys_rst_n='0' then
- fifo_rst_cnt <= 20;
- fifo_rst <='1';
-elsif fifo_rst_cnt /= 0 then
- fifo_rst_cnt <= fifo_rst_cnt -1;
-else
- fifo_rst <='0';
-end if;
-end if;
-end process;
+ generic map (
+ video_width => video_width
+ )
+ port map (
+ clk => vnc_clk,
+ vnc_valid => vnc_valid,
+ vnc_data => vnc_data,
+ vnc_index => vnc_index,
+
+ fifo_data => fifo_wdata,
+ fifo_wren => fifo_wr_en);
+
+
+ process (clk_50m)
+ begin
+ if rising_edge(clk_50m) then
+ if sys_rst_n = '0' then
+ fifo_rst_cnt <= 20;
+ fifo_rst <= '1';
+ elsif fifo_rst_cnt /= 0 then
+ fifo_rst_cnt <= fifo_rst_cnt -1;
+ else
+ fifo_rst <= '0';
+ end if;
+ end if;
+ end process;
fifo_i : entity work.fifo_generator_0
- port map (
- rst => fifo_rst,
- wr_clk => vnc_clk,
- din => fifo_wdata,
- wr_en => fifo_wr_en,
- rd_clk=>hp0_aclk,
- rd_en =>fifo_rd_en,
- dout => fifo_rdata,
- empty => fifo_empty
- );
+ port map (
+ rst => fifo_rst,
+ wr_clk => vnc_clk,
+ din => fifo_wdata,
+ wr_en => fifo_wr_en,
+ rd_clk => hp0_aclk,
+ rd_en => fifo_rd_en,
+ dout => fifo_rdata,
+ empty => fifo_empty
+ );
@@ -363,7 +364,7 @@ end process;
axi_bvalid => hp0_bvalid,
axi_bready => hp0_bready,
- run => run,
+ run => run,
fifo_empty => fifo_empty,
fifo_rdata => fifo_rdata,
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-06 09:58:56 +0000