make a7 code look more like s6/c4 code

9 files changed, 139 insertions, 144 deletions

diff --git a/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl b/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl
index f2bb7b6..f7f8971 100644
--- a/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl
@@ -19,12 +19,12 @@ entity clkgen is
 end clkgen;
 architecture Behavioural of clkgen is
 
-    signal clk_240m   : std_logic;
-    signal clk_78_571m    : std_logic;
-    signal clk_80m    : std_logic;
-    signal clk_24m    : std_logic;
-    signal clk_48m    : std_logic;
-    signal clk_50m : std_logic;
+    signal clk_240m    : std_logic;
+    signal clk_78_571m : std_logic;
+    signal clk_80m     : std_logic;
+    signal clk_24m     : std_logic;
+    signal clk_48m     : std_logic;
+    signal clk_50m     : std_logic;
 
     signal reset : std_logic;
 begin
@@ -43,7 +43,7 @@ begin
         clk_out3 => clk_48m,
         clk_out4 => clk_24m,
         reset    => reset,
-	locked   => locked
+        locked   => locked
         );
 
     mmcm_1_i : mmcm_1 port map (
@@ -53,9 +53,9 @@ begin
         );
 
     o_clk_phy <= clk_240m;
-    o_clk<= clk_24m;
-    o_clk_x2<= clk_48m;
-    i_clk<=clk_78_571m;
+    o_clk     <= clk_24m;
+    o_clk_x2  <= clk_48m;
+    i_clk     <= clk_78_571m;
 
 
 end Behavioural;
diff --git a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl
index b98c722..618895f 100644
--- a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl
+++ b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl
@@ -19,8 +19,8 @@ if {[llength $files] != 0} {
 #read_xdc $early_xdc
 
 #read_verilog [ glob ../source/*.v ]
-#read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ]
-read_vhdl -vhdl2008 -library work { clkgen_artix7.vhdl debounce.vhdl delay.vhdl edge_det.vhdl hp_lcd_driver.vhdl input_formatter.vhdl input_stage.vhdl output_analog.vhdl output_formatter.vhdl output_stage.vhdl synchronizer.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_output_artix7.vhdl tmds_phy_artix7.vhdl vram_artix7.vhdl }
+read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ]
+#read_vhdl -vhdl2008 -library work { clkgen_artix7.vhdl debounce.vhdl delay.vhdl edge_det.vhdl hp_lcd_driver.vhdl input_formatter.vhdl input_stage.vhdl output_analog.vhdl output_formatter.vhdl output_stage.vhdl synchronizer.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_output_artix7.vhdl tmds_phy_artix7.vhdl vram_artix7.vhdl }
 
 set generics {}
 append generics { } "video_width=$video_width"
diff --git a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl
index 28c00f4..755c422 100644
--- a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl
@@ -15,14 +15,14 @@ entity hp_lcd_driver is
              addr_width     : natural := 18;
              phase_slip     : natural := 320;
              i_clk_multiple : natural := 4;
-	     use_pclk       : natural := 0;
+             use_pclk       : natural := 0;
              target         : string  := "artix7");
     port (clk_50m   : in  std_logic;
 --          sys_rst_n : in  std_logic;
           video     : in  std_logic_vector(video_width -1 downto 0);
           hsync_in  : in  std_logic;
           vsync_in  : in  std_logic;
-          pclk_in   : in std_logic;
+          pclk_in   : in  std_logic;
           r_out     : out std_logic;
           b_out     : out std_logic;
           g_out     : out std_logic;
@@ -36,19 +36,19 @@ entity hp_lcd_driver is
           hdmi_g_n  : out std_logic;
           hdmi_b_p  : out std_logic;
           hdmi_b_n  : out std_logic;
-	  hdmi_vcc: out std_logic;
+          hdmi_vcc  : out std_logic;
           i_clk_out : out std_logic;
-	  led_0: out std_logic;
-	  led_1: out std_logic);
+          led_0     : out std_logic;
+          led_1     : out std_logic);
 
 end hp_lcd_driver;
 
 architecture Behavioral of hp_lcd_driver is
 
-    signal sys_rst_n:std_logic;
-    signal wr_addr : std_logic_vector(addr_width-1 downto 0);
-    signal wr_data : std_logic_vector(video_width-1 downto 0);
-    signal wr_en   : std_logic;
+    signal sys_rst_n : std_logic;
+    signal wr_addr   : std_logic_vector(addr_width-1 downto 0);
+    signal wr_data   : std_logic_vector(video_width-1 downto 0);
+    signal wr_en     : std_logic;
 
     signal rd_addr : std_logic_vector(addr_width-1 downto 0);
     signal rd_data : std_logic_vector(video_width-1 downto 0);
@@ -76,13 +76,13 @@ architecture Behavioral of hp_lcd_driver is
     signal v : natural;
 
 
-signal c:natural;
-signal t:std_logic;
+    signal c : natural;
+    signal t : std_logic;
 
 begin
 
 
-sys_rst_n <='1';
+    sys_rst_n <= '1';
 
 -- clocking:
 -- i_clk is 4*(nominal) 20MHz to give us 4 choices of sampling position
@@ -157,13 +157,13 @@ sys_rst_n <='1';
             h_stride      => 384,
             v_stride      => 524287,
             phase_slip    => phase_slip,
-	    use_pclk => use_pclk,
+            use_pclk      => use_pclk
             )
         port map (
             sys_rst_n => sys_rst_n,
             clk       => i_clk,
             video_in  => video,
-		pclk_in => pclk_in,
+            pclk_in   => pclk_in,
             hsync_in  => not hsync_in,
             vsync_in  => not vsync_in,
 
@@ -215,7 +215,7 @@ sys_rst_n <='1';
             rd_data => rd_data
             );
 
-	
+
 
 --   r<=x"00";
 --   b<=x"00";
@@ -226,7 +226,7 @@ sys_rst_n <='1';
 
 --"ff" when rd_data(1) = '1' else
 --         x"80" when rd_data(0) = '1' else
---	ix"00";
+--      ix"00";
 
 
 
@@ -278,17 +278,17 @@ sys_rst_n <='1';
             h_stride     => 1,
             v_stride     => 384
 
---		h_active	=> 640,
---		h_sync_start=>656,
---		h_sync_end =>752,
---		h_total=>800,
+--              h_active        => 640,
+--              h_sync_start=>656,
+--              h_sync_end =>752,
+--              h_total=>800,
 --
---		v_active =>480,
---		v_sync_start=>490,
---		v_sync_end=>492,
---		v_total=>525,
---		h_stride=>1,
---		v_stride=>384
+--              v_active =>480,
+--              v_sync_start=>490,
+--              v_sync_end=>492,
+--              v_total=>525,
+--              h_stride=>1,
+--              v_stride=>384
 
             )
 
@@ -318,21 +318,22 @@ sys_rst_n <='1';
             hdmi_b_n   => hdmi_b_n
             );
 
-process (clk_50m,c) begin
-if rising_edge(clk_50m) then
+    process (clk_50m, c)
+    begin
+        if rising_edge(clk_50m) then
 
-if c<19999999  then
-        c<=c+1;
-else
-        c<=0;
-        t<=not t;
-end if;
-end if;
-end process;
+            if c < 19999999 then
+                c <=c+1;
+            else
+                c <=0;
+                t <=not t;
+            end if;
+        end if;
+    end process;
 
 
-led_0<=t;
-led_1<=not t;
+    led_0 <= t;
+    led_1 <= not t;
 
 
 end Behavioral;
diff --git a/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl b/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl
index 1f27932..35916f5 100644
--- a/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl
@@ -16,16 +16,16 @@ entity input_formatter is
         frame_start   : natural := 0;
         h_stride      : natural := 384;
         v_stride      : natural := 1;
-        phase_slip    : natural := 320
-	use_pclk      : natural := 0
-	);
+        phase_slip    : natural := 320;
+        use_pclk      : natural := 0
+        );
     port
         (
             sys_rst_n : in  std_logic;
             clk       : in  std_logic;
             hsync     : in  std_logic;
             vsync     : in  std_logic;
-	    pclk      : in  std_logic;
+            pclk      : in  std_logic;
             addr_out  : out std_logic_vector(addr_width-1 downto 0);
             wren_out  : out std_logic;
             h_grid    : out std_logic;
@@ -52,7 +52,7 @@ architecture beh of input_formatter is
     signal h_fp_counter     : natural;
     signal h_active_counter : natural;
 
-    signal h_div            : natural;
+    signal h_div       : natural;
     signal phase_accum : natural;
 
 
@@ -116,34 +116,28 @@ begin
                 h_fp_counter <= h_fp_counter -1;
             elsif h_active_counter /= 0 then
 
-
-	    g_hclk: if use_pclk='0' generate
-                if h_div = 0 then
-                    wren <= '1';
-                    if phase_accum = 0 then
-                        phase_accum <= phase_slip;
-                        h_div       <= clk_multiple;
+                if use_pclk = 0 then
+                    if h_div = 0 then
+                        wren <= '1';
+                        if phase_accum = 0 then
+                            phase_accum <= phase_slip;
+                            h_div       <= clk_multiple;
+                        else
+                            phase_accum <= phase_accum-1;
+                            h_div       <= clk_multiple-1;
+                        end if;
                     else
-                        phase_accum <= phase_accum-1;
-                        h_div       <= clk_multiple-1;
+                        h_div <= h_div -1;
+                        wren  <= '0';
                     end if;
                 else
-                    h_div <= h_div -1;
-                        wren             <= '0';
+		    wren <= pclk_pe;
                 end if;
-	end generate;
-	    g_hclk: if use_pclk='0' generate
-                if pclk_pe = '1' then
-                    wren <= '1';
-                else
-                        wren             <= '0';
-		end if;
-		end generate;
 
-                    if wren = '1' then
-                        h_active_counter <= h_active_counter -1;
-                        addr             <= std_logic_vector(unsigned(addr)+h_stride);
-                    end if;
+                if wren = '1' then
+                    h_active_counter <= h_active_counter -1;
+                    addr             <= std_logic_vector(unsigned(addr)+h_stride);
+                end if;
             end if;
         end if;
     end process;
diff --git a/fpga/hp_lcd_driver_a7/source/input_stage.vhdl b/fpga/hp_lcd_driver_a7/source/input_stage.vhdl
index 16ea9bb..c124a59 100644
--- a/fpga/hp_lcd_driver_a7/source/input_stage.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/input_stage.vhdl
@@ -16,8 +16,8 @@ entity input_stage is
              frame_start     : natural := 0;
              h_stride        : natural := 384;
              v_stride        : natural := 1;
-             phase_slip      : natural := 320
-             use_pclk      : natural := 0);
+             phase_slip      : natural := 320;
+             use_pclk        : natural := 0);
     port
         (
             clk       : in std_logic;
@@ -25,7 +25,7 @@ entity input_stage is
 
             video_in : in std_logic_vector(video_width -1 downto 0);
 
-	    pclk_in : in std_logic;
+            pclk_in  : in std_logic;
             hsync_in : in std_logic;
             vsync_in : in std_logic;
 
@@ -94,7 +94,7 @@ begin
             o   => s_vsync
             );
 
- 
+
     pclk_debounce : entity work.debounce
         generic map(stages => debounce_stages)
         port map(
@@ -131,11 +131,11 @@ begin
             h_stride      => h_stride,
             v_stride      => v_stride,
             phase_slip    => phase_slip,
-		use_pclk => use_pclk)
+            use_pclk      => use_pclk)
         port map (
             sys_rst_n => sys_rst_n,
             clk       => clk,
-	    pclk      => d_pclk,
+            pclk      => d_pclk,
             hsync     => d_hsync,
             vsync     => d_vsync,
             addr_out  => addr,
diff --git a/fpga/hp_lcd_driver_a7/source/output_formatter.vhdl b/fpga/hp_lcd_driver_a7/source/output_formatter.vhdl
index 3e26515..558c222 100644
--- a/fpga/hp_lcd_driver_a7/source/output_formatter.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/output_formatter.vhdl
@@ -124,11 +124,11 @@ begin
 
     h_grid <= '1' when (h mod 32) = 0
 --    h_grid <= '1' when (h = 0) or (h = (h_active-1))
-              else '0';
+else '0';
 
     v_grid <= '1' when (v mod 32) = 0
 --    v_grid <= '1' when (v = 0) or (v = (v_active-1))
-              else '0';
+else '0';
 
 
     addr_out  <= addr;
diff --git a/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl b/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl
index 9a7ee7d..7370bb7 100644
--- a/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl
@@ -34,12 +34,12 @@ end tmds_output;
 
 architecture beh of tmds_output is
 
-signal phy_reset : std_logic;
-    signal b : natural := 0;
+    signal phy_reset : std_logic;
+    signal b         : natural := 0;
 
 
 begin
-    phy_reset <= not sys_rst_n; -- or not pll_locked;
+    phy_reset <= not sys_rst_n;         -- or not pll_locked;
 
     process (pclk_phy, b, sys_rst_n)
     begin
@@ -57,48 +57,48 @@ begin
 
     phy_c : entity work.tmds_phy_artix7
         port map (
-            reset        => phy_reset,
-            pix_clk      => pclk,
-            phy_clk      => pclk_phy,
-	b=>b,
-            din          => c_p10,
-            tmds_out_p   => tmds_c_out_p,
-            tmds_out_n   => tmds_c_out_n
+            reset      => phy_reset,
+            pix_clk    => pclk,
+            phy_clk    => pclk_phy,
+            b          =>b,
+            din        => c_p10,
+            tmds_out_p => tmds_c_out_p,
+            tmds_out_n => tmds_c_out_n
             );
 
     phy_r : entity work.tmds_phy_artix7
         port map (
-            reset        => phy_reset,
-            pix_clk      => pclk,
-            phy_clk      => pclk_phy,
-	b=>b,
-            din          => r_p10,
-            tmds_out_p   => tmds_r_out_p,
-            tmds_out_n   => tmds_r_out_n
+            reset      => phy_reset,
+            pix_clk    => pclk,
+            phy_clk    => pclk_phy,
+            b          =>b,
+            din        => r_p10,
+            tmds_out_p => tmds_r_out_p,
+            tmds_out_n => tmds_r_out_n
             );
 
 
     phy_g : entity work.tmds_phy_artix7
         port map (
-            reset        => phy_reset,
-            pix_clk      => pclk,
-            phy_clk      => pclk_phy,
-	b=>b,
-            din          => g_p10,
-            tmds_out_p   => tmds_g_out_p,
-            tmds_out_n   => tmds_g_out_n
+            reset      => phy_reset,
+            pix_clk    => pclk,
+            phy_clk    => pclk_phy,
+            b          =>b,
+            din        => g_p10,
+            tmds_out_p => tmds_g_out_p,
+            tmds_out_n => tmds_g_out_n
             );
 
 
     phy_b : entity work.tmds_phy_artix7
         port map (
-            reset        => phy_reset,
-            pix_clk      => pclk,
-            phy_clk      => pclk_phy,
-	b=>b,
-            din          => b_p10,
-            tmds_out_p   => tmds_b_out_p,
-            tmds_out_n   => tmds_b_out_n
+            reset      => phy_reset,
+            pix_clk    => pclk,
+            phy_clk    => pclk_phy,
+            b          =>b,
+            din        => b_p10,
+            tmds_out_p => tmds_b_out_p,
+            tmds_out_n => tmds_b_out_n
             );
 
 
diff --git a/fpga/hp_lcd_driver_a7/source/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver_a7/source/tmds_phy_artix7.vhdl
index 295f8b6..8c8106e 100644
--- a/fpga/hp_lcd_driver_a7/source/tmds_phy_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/tmds_phy_artix7.vhdl
@@ -2,17 +2,17 @@ library ieee;
 use ieee.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 
-Library UNISIM;
+library UNISIM;
 use UNISIM.vcomponents.all;
 
 
 entity tmds_phy_artix7 is
     port (
-        reset  : in  std_logic;
-        pix_clk   : in  std_logic;
-        phy_clk   : in  std_logic;
+        reset      : in  std_logic;
+        pix_clk    : in  std_logic;
+        phy_clk    : in  std_logic;
         din        : in  std_logic_vector(9 downto 0);
-	b:	in natural;
+        b          : in  natural;
         tmds_out_p : out std_logic;
         tmds_out_n : out std_logic
         );
@@ -24,24 +24,24 @@ architecture beh of tmds_phy_artix7 is
     signal ld : std_logic_vector(9 downto 0);
     signal sr : std_logic_vector(9 downto 0);
 
-signal s:std_logic;
+    signal s : std_logic;
 
 begin
 
 
-   process(pix_clk)
-   begin
-      if rising_edge(pix_clk) then 
+    process(pix_clk)
+    begin
+        if rising_edge(pix_clk) then
             ld <= din;
-      end if;
-   end process;
+        end if;
+    end process;
 
 
 -- Using ODDR
 --   process(phy_clk)
 --   begin
 --      if rising_edge(phy_clk) then 
---	 if b=0 then
+--       if b=0 then
 --              sr<= ld;
 --         else
 --            sr(7 downto 0) <= sr  (9 downto 2);
@@ -66,20 +66,20 @@ begin
 
 
 -- Using a shift register
-   process(phy_clk)
-   begin
-      if rising_edge(phy_clk) then 
-	 if b=0 then
-            sr<= ld;
-         else
-            sr(8 downto 0) <= sr  (9 downto 1);
-            s<=sr(0);
-         end if;
-      end if;
-   end process;
+    process(phy_clk)
+    begin
+        if rising_edge(phy_clk) then
+            if b = 0 then
+                sr <= ld;
+            else
+                sr(8 downto 0) <= sr (9 downto 1);
+                s              <=sr(0);
+            end if;
+        end if;
+    end process;
 
 
 
-   od :OBUFDS port map (O=>tmds_out_p, OB=>tmds_out_n,I=>s);
+    od : OBUFDS port map (O => tmds_out_p, OB => tmds_out_n, I => s);
 
 end beh;
diff --git a/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl b/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl
index d2d1c3c..82186e1 100644
--- a/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl
@@ -23,10 +23,10 @@ begin
 
     wr_en_v(0) <= wr_en;
 
-    bmg0: entity work.blk_mem_gen_0
+    bmg0 : entity work.blk_mem_gen_0
         port map (
-		ena => '1',
-		enb=>'1',
+            ena   => '1',
+            enb   => '1',
             clka  => wr_clk,
             wea   => wr_en_v,
             addra => wr_addr,