somewhat working on a7

14 files changed, 436 insertions, 207 deletions

diff --git a/fpga/hp_lcd_driver_a7/Makefile b/fpga/hp_lcd_driver_a7/Makefile
index 9a297c2..f2a4ee9 100644
--- a/fpga/hp_lcd_driver_a7/Makefile
+++ b/fpga/hp_lcd_driver_a7/Makefile
@@ -24,6 +24,7 @@ BUILD=build-${BOARD}
 #endif
 
 IP= \
+	source/ip/blk_mem_gen_0.tcl \
 	source/ip/mmcm_0.tcl \
 	source/ip/mmcm_1.tcl 
 
diff --git a/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl b/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl
index c115478..f2bb7b6 100644
--- a/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl
@@ -19,10 +19,11 @@ entity clkgen is
 end clkgen;
 architecture Behavioural of clkgen is
 
-    signal clk_200m   : std_logic;
+    signal clk_240m   : std_logic;
     signal clk_78_571m    : std_logic;
-    signal clk_40m    : std_logic;
-    signal clk_20m    : std_logic;
+    signal clk_80m    : std_logic;
+    signal clk_24m    : std_logic;
+    signal clk_48m    : std_logic;
     signal clk_50m : std_logic;
 
     signal reset : std_logic;
@@ -34,11 +35,13 @@ begin
         I => clk_in,
         O => clk_50m);
 
+
     mmcm_0_i : mmcm_0 port map (
         clk_in1  => clk_50m,
-        clk_out1 => clk_200m,
-        clk_out2 => clk_40m,
-        clk_out3 => clk_20m,
+        clk_out1 => clk_240m,
+        clk_out2 => clk_80m,
+        clk_out3 => clk_48m,
+        clk_out4 => clk_24m,
         reset    => reset,
 	locked   => locked
         );
@@ -49,9 +52,9 @@ begin
         reset    => reset
         );
 
-    o_clk_phy <= clk_200m;
-    o_clk<= clk_20m;
-    o_clk_x2<= clk_40m;
+    o_clk_phy <= clk_240m;
+    o_clk<= clk_24m;
+    o_clk_x2<= clk_48m;
     i_clk<=clk_78_571m;
 
 
diff --git a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl
index 4c9231d..b244449 100644
--- a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl
+++ b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl
@@ -22,7 +22,7 @@ read_xdc $early_xdc
 read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ]
 
 set generics {}
-#append generics { } "CLOCKS=\"A${aclk}_S${sclk}\""
+append generics { } "video_width=6"
 append generics { } "BOARD=\"$board\""
 #append generics { } "LA_ADDR_WIDTH=$LA_ADDR_WIDTH" 
 #append generics { } "MEM_DATA_WIDTH=$MEM_DATA_WIDTH"
@@ -34,6 +34,7 @@ append generics { } "BOARD=\"$board\""
 set_property generic "$generics" [current_fileset]
 puts $generics
 
+read_ip $ip_dir/blk_mem_gen_0/blk_mem_gen_0.xci
 read_ip $ip_dir/mmcm_0/mmcm_0.xci
 read_ip $ip_dir/mmcm_1/mmcm_1.xci
 #read_ip $ip_dir/dma_block_0/dma_block_0.xci
diff --git a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl
index 087e475..fb4f194 100644
--- a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl
@@ -15,12 +15,13 @@ entity hp_lcd_driver is
              addr_width     : natural := 18;
              phase_slip     : natural := 320;
              i_clk_multiple : natural := 4;
-             target         : string  := "spartan6");
+             target         : string  := "artix7");
     port (clk_50m   : in  std_logic;
-          sys_rst_n : in  std_logic;
-          video     : in  std_logic_vector(video_width-1 downto 0);
+--          sys_rst_n : in  std_logic;
+          video     : in  std_logic_vector(video_width -1 downto 0);
           hsync_in  : in  std_logic;
           vsync_in  : in  std_logic;
+          pclk_in   : in std_logic;
           r_out     : out std_logic;
           b_out     : out std_logic;
           g_out     : out std_logic;
@@ -34,12 +35,16 @@ entity hp_lcd_driver is
           hdmi_g_n  : out std_logic;
           hdmi_b_p  : out std_logic;
           hdmi_b_n  : out std_logic;
-          i_clk_out : out std_logic);
+	  hdmi_vcc: out std_logic;
+          i_clk_out : out std_logic;
+	  led_0: out std_logic;
+	  led_1: out std_logic);
 
 end hp_lcd_driver;
 
 architecture Behavioral of hp_lcd_driver is
 
+    signal sys_rst_n:std_logic;
     signal wr_addr : std_logic_vector(addr_width-1 downto 0);
     signal wr_data : std_logic_vector(video_width-1 downto 0);
     signal wr_en   : std_logic;
@@ -70,10 +75,14 @@ architecture Behavioral of hp_lcd_driver is
     signal v : natural;
 
 
+signal c:natural;
+signal t:std_logic;
 
 begin
 
 
+sys_rst_n <='1';
+
 -- clocking:
 -- i_clk is 4*(nominal) 20MHz to give us 4 choices of sampling position
 -- o_clk is the output pixel clock
@@ -152,6 +161,7 @@ begin
             sys_rst_n => sys_rst_n,
             clk       => i_clk,
             video_in  => video,
+		pclk_in => pclk_in,
             hsync_in  => not hsync_in,
             vsync_in  => not vsync_in,
 
@@ -205,12 +215,16 @@ begin
 
 	
 
-   r<=x"00";
-   b<=x"00";
+--   r<=x"00";
+--   b<=x"00";
+
+    r <= rd_data(1 downto 0) & "000000";
+    g <= rd_data(3 downto 2) & "000000";
+    b <= rd_data(5 downto 4) & "000000";
 
-    g <= x"ff" when rd_data(1) = '1' else
-         x"80" when rd_data(0) = '1' else
-	x"00";
+--"ff" when rd_data(1) = '1' else
+--         x"80" when rd_data(0) = '1' else
+--	ix"00";
 
 
 
@@ -262,17 +276,20 @@ begin
             h_stride     => 1,
             v_stride     => 384
 
---            h_active     => 800,
---            h_sync_start => 832,
---            h_sync_end   => 912,
---            h_total      => 1024,
---            v_active     => 600,
---            v_sync_start => 601,
---            v_sync_end   => 604,
---            v_total      => 622,
---            h_stride     => 1,
---            v_stride     => 384
+--		h_active	=> 640,
+--		h_sync_start=>656,
+--		h_sync_end =>752,
+--		h_total=>800,
+--
+--		v_active =>480,
+--		v_sync_start=>490,
+--		v_sync_end=>492,
+--		v_total=>525,
+--		h_stride=>1,
+--		v_stride=>384
+
             )
+
         port map(
             clk_locked => clk_locked,
             clk        => o_clk,
@@ -299,6 +316,22 @@ begin
             hdmi_b_n   => hdmi_b_n
             );
 
+process (clk_50m,c) begin
+if rising_edge(clk_50m) then
+
+if c<19999999  then
+        c<=c+1;
+else
+        c<=0;
+        t<=not t;
+end if;
+end if;
+end process;
+
+
+led_0<=t;
+led_1<=not t;
+
 
 end Behavioral;
 
diff --git a/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl b/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl
index f3bd434..f50f6e5 100644
--- a/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl
@@ -23,6 +23,7 @@ entity input_formatter is
             clk       : in  std_logic;
             hsync     : in  std_logic;
             vsync     : in  std_logic;
+	    pclk      : in  std_logic;
             addr_out  : out std_logic_vector(addr_width-1 downto 0);
             wren_out  : out std_logic;
             h_grid    : out std_logic;
@@ -38,6 +39,9 @@ architecture beh of input_formatter is
     signal addr     : std_logic_vector(addr_width-1 downto 0);
     signal wren     : std_logic;
 
+    signal pclk_ne : std_logic;
+    signal pclk_pe : std_logic;
+
     signal hsync_ne : std_logic;
     signal hsync_pe : std_logic;
 
@@ -45,9 +49,9 @@ architecture beh of input_formatter is
     signal v_active_counter : natural;
     signal h_fp_counter     : natural;
     signal h_active_counter : natural;
-    signal h_div            : natural;
 
-    signal phase_accum : natural;
+--    signal h_div            : natural;
+--    signal phase_accum : natural;
 
 
 begin
@@ -62,6 +66,14 @@ begin
             pe  => hsync_pe);
 
 
+    pclk_ed : entity work.edge_det
+        port map(
+            clk => clk,
+            sig => pclk,
+            e   => pclk_ne,
+            pe  => pclk_pe);
+
+
 
 
     addr_out <= addr;
@@ -72,12 +84,12 @@ begin
         if sys_rst_n = '0' then
             row_addr         <= (others => '0');
             addr             <= (others => '0');
-            h_div            <= 0;
+            --h_div            <= 0;
             h_active_counter <= 0;
             h_fp_counter     <= 0;
             v_active_counter <= 0;
             v_fp_counter     <= 0;
-            phase_accum      <= 0;
+            --phase_accum      <= 0;
         elsif rising_edge(clk) then
             if hsync_pe = '1' then
                 --if v_active_counter = 0 and v_fp_counter=0 then
@@ -92,8 +104,8 @@ begin
 
                     h_fp_counter     <= h_front_porch * clk_multiple + phase;
                     h_active_counter <= h_active;
-                    phase_accum      <= phase_slip;
-                    h_div            <= 0;
+                    --phase_accum      <= phase_slip;
+                    --h_div            <= 0;
 
                     addr     <= row_addr;
                     row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
@@ -102,22 +114,23 @@ begin
                 h_fp_counter <= h_fp_counter -1;
             elsif h_active_counter /= 0 then
 
-                if h_div = 0 then
+--                if h_div = 0 then
+                if pclk_pe = '1' then
                     wren <= '1';
-                    if phase_accum = 0 then
-                        phase_accum <= phase_slip;
-                        h_div       <= clk_multiple;
-                    else
-                        phase_accum <= phase_accum-1;
-                        h_div       <= clk_multiple-1;
-                    end if;
+--                    if phase_accum = 0 then
+--                        phase_accum <= phase_slip;
+--                        h_div       <= clk_multiple;
+--                    else
+--                        phase_accum <= phase_accum-1;
+--                        h_div       <= clk_multiple-1;
+--                    end if;
                 else
                     if wren = '1' then
                         wren             <= '0';
                         h_active_counter <= h_active_counter -1;
                         addr             <= std_logic_vector(unsigned(addr)+h_stride);
                     end if;
-                    h_div <= h_div -1;
+                    --h_div <= h_div -1;
                 end if;
             end if;
         end if;
diff --git a/fpga/hp_lcd_driver_a7/source/input_stage.vhdl b/fpga/hp_lcd_driver_a7/source/input_stage.vhdl
index 9355a93..028c5d6 100644
--- a/fpga/hp_lcd_driver_a7/source/input_stage.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/input_stage.vhdl
@@ -24,6 +24,7 @@ entity input_stage is
 
             video_in : in std_logic_vector(video_width -1 downto 0);
 
+	    pclk_in : in std_logic;
             hsync_in : in std_logic;
             vsync_in : in std_logic;
 
@@ -36,6 +37,9 @@ end input_stage;
 
 architecture beh of input_stage is
 
+    signal s_pclk : std_logic;
+    signal d_pclk : std_logic;
+
     signal s_hsync : std_logic;
     signal d_hsync : std_logic;
 
@@ -65,6 +69,13 @@ begin
     end generate;
 
 
+    pclk_sync : entity work.synchronizer
+        generic map(stages => sync_stages)
+        port map (
+            clk => clk,
+            i   => pclk_in,
+            o   => s_pclk
+            );
 
     hsync_sync : entity work.synchronizer
         generic map(stages => sync_stages)
@@ -82,6 +93,14 @@ begin
             o   => s_vsync
             );
 
+ 
+    pclk_debounce : entity work.debounce
+        generic map(stages => debounce_stages)
+        port map(
+            clk => clk,
+            i   => s_pclk,
+            o   => d_pclk);
+
     hsync_debounce : entity work.debounce
         generic map(stages => debounce_stages)
         port map(
@@ -89,8 +108,6 @@ begin
             i   => s_hsync,
             o   => d_hsync);
 
-
-
     vsync_debounce : entity work.debounce
         generic map(stages => debounce_stages)
         port map(
@@ -116,6 +133,7 @@ begin
         port map (
             sys_rst_n => sys_rst_n,
             clk       => clk,
+	    pclk      => d_pclk,
             hsync     => d_hsync,
             vsync     => d_vsync,
             addr_out  => addr,
diff --git a/fpga/hp_lcd_driver_a7/source/ip/blk_mem_gen_0.tcl b/fpga/hp_lcd_driver_a7/source/ip/blk_mem_gen_0.tcl
new file mode 100644
index 0000000..0c94aab
--- /dev/null
+++ b/fpga/hp_lcd_driver_a7/source/ip/blk_mem_gen_0.tcl
@@ -0,0 +1,33 @@
+
+
+set source_dir [file dirname [file dirname [file normalize [info script]]]]
+
+source $source_dir/config.tcl
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name blk_mem_gen_0 -dir $ip_dir
+
+set_property -dict [list \
+	CONFIG.Memory_Type {Simple_Dual_Port_RAM} \
+	CONFIG.Enable_32bit_Address {false} \
+	CONFIG.Use_Byte_Write_Enable {false} \
+	CONFIG.Byte_Size {9} \
+	CONFIG.Write_Width_A {6} \
+	CONFIG.Write_Depth_A {245760} \
+	CONFIG.Read_Width_A {6} \
+	CONFIG.Operating_Mode_A {NO_CHANGE} \
+	CONFIG.Write_Width_B {6} \
+	CONFIG.Read_Width_B {6} \
+	CONFIG.Enable_B {Use_ENB_Pin} \
+	CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+	CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \
+	CONFIG.Use_RSTB_Pin {false} \
+	CONFIG.Port_B_Clock {22} \
+	CONFIG.Port_B_Enable_Rate {22} \
+	CONFIG.Disable_Collision_Warnings {false} \
+	CONFIG.EN_SAFETY_CKT {false} \
+	] [get_ips blk_mem_gen_0]
+
+generate_target all [get_ips]
+
+synth_ip [get_ips]
+
diff --git a/fpga/hp_lcd_driver_a7/source/ip/mmcm_0.tcl b/fpga/hp_lcd_driver_a7/source/ip/mmcm_0.tcl
index 2dc3648..70fc435 100644
--- a/fpga/hp_lcd_driver_a7/source/ip/mmcm_0.tcl
+++ b/fpga/hp_lcd_driver_a7/source/ip/mmcm_0.tcl
@@ -9,28 +9,27 @@ set_property -dict [list \
 	CONFIG.CLKOUT2_USED {true} \
 	CONFIG.CLKOUT3_USED {true} \
 	CONFIG.CLKOUT4_USED {true} \
-	CONFIG.CLKOUT5_USED {false} \
-	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200} \
-	CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {40} \
-	CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
-	CONFIG.USE_SAFE_CLOCK_STARTUP {false} \
-	CONFIG.CLKIN1_JITTER_PS {100.0} \
-	CONFIG.CLKOUT1_DRIVES {BUFG} \
-	CONFIG.CLKOUT2_DRIVES {BUFG} \
-	CONFIG.CLKOUT3_DRIVES {BUFG} \
-	CONFIG.CLKOUT4_DRIVES {BUFG} \
-	CONFIG.CLKOUT5_DRIVES {BUFG} \
-	CONFIG.CLKOUT6_DRIVES {BUFG} \
-	CONFIG.CLKOUT7_DRIVES {BUFG} \
-	CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
-	CONFIG.MMCM_DIVCLK_DIVIDE {1} \
-	CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \
+	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {240} \
+	CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {80} \
+	CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {48} \
+	CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {24} \
+	CONFIG.CLKIN1_JITTER_PS {200.0} \
+	CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \
 	CONFIG.MMCM_CLKIN1_PERIOD {20.000} \
-	CONFIG.MMCM_CLKIN2_PERIOD {20.000} \
-	CONFIG.MMCM_CLKOUT0_DIVIDE_F {1} \
-	CONFIG.MMCM_CLKOUT1_DIVIDE {5} \
-	CONFIG.MMCM_CLKOUT2_DIVIDE {10} \
-	CONFIG.NUM_OUT_CLKS {3} \
+	CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
+	CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
+	CONFIG.MMCM_CLKOUT1_DIVIDE {15} \
+	CONFIG.MMCM_CLKOUT2_DIVIDE {25} \
+	CONFIG.MMCM_CLKOUT3_DIVIDE {50} \
+	CONFIG.NUM_OUT_CLKS {4} \
+	CONFIG.CLKOUT1_JITTER {120.627} \
+	CONFIG.CLKOUT1_PHASE_ERROR {154.678} \
+	CONFIG.CLKOUT2_JITTER {146.190} \
+	CONFIG.CLKOUT2_PHASE_ERROR {154.678} \
+	CONFIG.CLKOUT3_JITTER {165.425} \
+	CONFIG.CLKOUT3_PHASE_ERROR {154.678} \
+	CONFIG.CLKOUT4_JITTER {202.151} \
+	CONFIG.CLKOUT4_PHASE_ERROR {154.678} \
 	] [get_ips mmcm_0]
 
 generate_target all [get_ips]
diff --git a/fpga/hp_lcd_driver_a7/source/output_stage.vhdl b/fpga/hp_lcd_driver_a7/source/output_stage.vhdl
index e02d8ce..56f4ae4 100644
--- a/fpga/hp_lcd_driver_a7/source/output_stage.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/output_stage.vhdl
@@ -140,15 +140,17 @@ begin
 --            o   => grid_d
 --            );
 
---    r <= r_in;
+    r <= r_in;
     g <= g_in;
---    b <= b_in;
+    b <= b_in;
 
-    b<=x"00" when v_grid='0'
-          else x"ff";
 
-    r<=x"00" when h_grid='0'
-          else x"ff";
+
+--    b<=x"00" when v_grid='0'
+--          else x"ff";
+
+--    r<=x"00" when h_grid='0'
+--          else x"ff";
 
 --    b<=x"00" when v_grid='0' and h_grid='0'
 --          else x"ff";
diff --git a/fpga/hp_lcd_driver_a7/source/rando_a7.tcl b/fpga/hp_lcd_driver_a7/source/rando_a7.tcl
index c29c369..6d652e1 100644
--- a/fpga/hp_lcd_driver_a7/source/rando_a7.tcl
+++ b/fpga/hp_lcd_driver_a7/source/rando_a7.tcl
@@ -1,5 +1,5 @@
 #
-set part_num "xc7a35tfgg484-2L"
+set part_num "xc7a35tfgg484-2"
 set early_xdc "../source/rando_a7_early.xdc"
 set normal_xdc "../source/rando_a7.xdc"
 #set MEM_DATA_WIDTH 0
diff --git a/fpga/hp_lcd_driver_a7/source/rando_a7.xdc b/fpga/hp_lcd_driver_a7/source/rando_a7.xdc
index b851836..e6460b8 100644
--- a/fpga/hp_lcd_driver_a7/source/rando_a7.xdc
+++ b/fpga/hp_lcd_driver_a7/source/rando_a7.xdc
@@ -1,49 +1,91 @@
 # "Normal" constraints file- not early not late
 
 
-###############################################################################
-# DDR
-###############################################################################
-# Note: Most of the pins are set in the constraints file created by MIG
-#set_property IOSTANDARD LVDS_25 [get_ports sys_clk_clk_p]
-#set_property IOSTANDARD LVDS_25 [get_ports sys_clk_clk_n]
-
-###############################################################################
-# LEDs (4)
-###############################################################################
-
-#set_property PACKAGE_PIN G3 [get_ports led_d0]
-#set_property IOSTANDARD LVCMOS33 [get_ports led_d0]
-#set_property PULLUP true [get_ports led_d0]
-#set_property DRIVE 8 [get_ports led_d0]
-#
-#set_property PACKAGE_PIN H3 [get_ports led_d1]
-#set_property IOSTANDARD LVCMOS33 [get_ports led_d1]
-#set_property PULLUP true [get_ports led_d1]
-#set_property DRIVE 8 [get_ports led_d1]
-#
-#set_property PACKAGE_PIN G4 [get_ports {led_d2}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {led_d2}]
-#set_property PULLUP true [get_ports {led_d2}]
-#set_property DRIVE 8 [get_ports {led_d2}]
-#
-#set_property PACKAGE_PIN H4 [get_ports {led_d3}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {led_d3}]
-#set_property PULLUP true [get_ports {led_d3}]
-#set_property DRIVE 8 [get_ports {led_d3}]
-#
-#
-# Timing Constraints
-###############################################################################
-
-#create_clock -period 10.000 -name pcie_clkin [get_ports pcie_clkin_p]
-
-###############################################################################
-# Physical Constraints
-###############################################################################
-
-#create_clock -period 10.000 -name clk_100m [get_ports pci_exp_ref_clk_p]
-
+set_property IOSTANDARD LVCMOS33 [get_ports clk_50m]
+set_property PACKAGE_PIN R4 [get_ports clk_50m]
+
+set_property PACKAGE_PIN U1 [get_ports {led_0}]
+set_property PACKAGE_PIN T1 [get_ports {led_1}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led_0}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led_1}]
+
+set_property PACKAGE_PIN R3 [get_ports {hdmi_r_p}]
+set_property PACKAGE_PIN R2 [get_ports {hdmi_r_n}]
+set_property PACKAGE_PIN R6 [get_ports {hdmi_g_p}]
+set_property PACKAGE_PIN T6 [get_ports {hdmi_g_n}]
+set_property PACKAGE_PIN U3 [get_ports {hdmi_b_p}]
+set_property PACKAGE_PIN V3 [get_ports {hdmi_b_n}]
+set_property PACKAGE_PIN Y3 [get_ports {hdmi_c_p}]
+set_property PACKAGE_PIN AA3 [get_ports {hdmi_c_n}]
+
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_p}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_n}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_p}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}]
+
+#set_property DRIVE 16 [get_ports {hdmi_c_p}]
+#set_property DRIVE 16 [get_ports {hdmi_c_n}]
+#set_property DRIVE 16 [get_ports {hdmi_r_p}]
+#set_property DRIVE 16 [get_ports {hdmi_r_n}]
+#set_property DRIVE 16 [get_ports {hdmi_g_p}]
+#set_property DRIVE 16 [get_ports {hdmi_g_n}]
+#set_property DRIVE 16 [get_ports {hdmi_b_p}]
+
+set_property PACKAGE_PIN W1 [get_ports {hdmi_vcc}]
+set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}]
+
+ 
+#set_property PACKAGE_PIN P20 [get_ports rxd]
+#set_property PACKAGE_PIN T20 [get_ports txd]
+#set_property IOSTANDARD LVCMOS33 [get_ports rxd]
+#set_property IOSTANDARD LVCMOS33 [get_ports txd]
+
+#set_property PACKAGE_PIN T3 [get_ports key]
+#set_property IOSTANDARD LVCMOS33 [get_ports key]
+
+set_property PACKAGE_PIN N22 [get_ports {video[0]}]
+set_property PACKAGE_PIN N20 [get_ports {video[1]}]
+set_property PACKAGE_PIN N18 [get_ports {video[2]}]
+set_property PACKAGE_PIN K18 [get_ports {video[3]}]
+set_property PACKAGE_PIN M18 [get_ports {video[4]}]
+set_property PACKAGE_PIN M15 [get_ports {video[5]}]
+#set_property PACKAGE_PIN U20 [get_ports {video[6]}]
+#set_property PACKAGE_PIN T21 [get_ports {video[7]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
+
+set_property PACKAGE_PIN W19 [get_ports {pclk_in}]
+set_property PACKAGE_PIN R18 [get_ports {vsync_in}]
+set_property PACKAGE_PIN Y18 [get_ports {hsync_in}]
+set_property PACKAGE_PIN P16 [get_ports {r_out}]
+set_property PACKAGE_PIN V18 [get_ports {g_out}]
+set_property PACKAGE_PIN P15 [get_ports {b_out}]
+set_property PACKAGE_PIN P14 [get_ports {i_clk_out}]
+set_property PACKAGE_PIN V17 [get_ports {hsync_out}]
+set_property PACKAGE_PIN N13 [get_ports {vsync_out}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vsync_in}]
+set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}]
+set_property IOSTANDARD LVCMOS33 [get_ports {r_out}]
+set_property IOSTANDARD LVCMOS33 [get_ports {g_out}]
+set_property IOSTANDARD LVCMOS33 [get_ports {b_out}]
+set_property IOSTANDARD LVCMOS33 [get_ports {i_clk_out}]
+set_property IOSTANDARD LVCMOS33 [get_ports {hsync_out}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vsync_out}]
+		
+create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m]
 #set_false_path -from [get_ports pci_exp_rst_n]
 
 
diff --git a/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl b/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl
index 10f064c..9a7ee7d 100644
--- a/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl
@@ -34,95 +34,82 @@ end tmds_output;
 
 architecture beh of tmds_output is
 
+signal phy_reset : std_logic;
+    signal b : natural := 0;
 
-    signal phy_reset    : std_logic;
-    signal upper        : std_logic;
-    signal pll_locked   : std_logic;
-    signal ioclk        : std_logic;
-    signal serdesstrobe : std_logic;
 
 begin
---    phy_reset <= not sys_rst_n or not pll_locked;
---
---    process (pclk_x2, phy_reset)
---    begin
---        if phy_reset = '1' then
---            upper <= '1';
---        elsif rising_edge(pclk_x2) then
---            upper <= not upper;
---        end if;
---    end process;
---
---
---    ioclk_buf : BUFPLL generic map (DIVIDE => 5)
---        port map (
---            PLLIN        => pclk_phy,
---            GCLK         => pclk_x2,
---            LOCKED       => pclk_locked,
---            IOCLK        => ioclk,
---            SERDESSTROBE => serdesstrobe,
---            LOCK         => pll_locked);
---
---
---    phy_c : entity work.tmds_phy_spartan6
---        port map (
---            reset        => phy_reset,
---            pclk_x2      => pclk_x2,
---            serdesstrobe => serdesstrobe,
---            ioclk        => ioclk,
---            upper        => upper,
---            din          => c_p10,
---            tmds_out_p   => tmds_c_out_p,
---            tmds_out_n   => tmds_c_out_n
---            );
---
---    phy_r : entity work.tmds_phy_spartan6
---        port map (
---            reset        => phy_reset,
---            pclk_x2      => pclk_x2,
---            serdesstrobe => serdesstrobe,
---            ioclk        => ioclk,
---            upper        => upper,
---            din          => r_p10,
---            tmds_out_p   => tmds_r_out_p,
---            tmds_out_n   => tmds_r_out_n
---            );
---
---
---    phy_g : entity work.tmds_phy_spartan6
---        port map (
---            reset        => phy_reset,
---            pclk_x2      => pclk_x2,
---            serdesstrobe => serdesstrobe,
---            ioclk        => ioclk,
---            upper        => upper,
---            din          => g_p10,
---            tmds_out_p   => tmds_g_out_p,
---            tmds_out_n   => tmds_g_out_n
---            );
---
---
---    phy_b : entity work.tmds_phy_spartan6
---        port map (
---            reset        => phy_reset,
---            pclk_x2      => pclk_x2,
---            serdesstrobe => serdesstrobe,
---            ioclk        => pclk_phy,
---            upper        => upper,
---            din          => b_p10,
---            tmds_out_p   => tmds_b_out_p,
---            tmds_out_n   => tmds_b_out_n
---            );
---
---
-        tmds_c_out_p <= '0';
-        tmds_c_out_n <= '0';
-        tmds_r_out_p <= '0';
-        tmds_r_out_n <= '0';
-        tmds_g_out_p <= '0';
-        tmds_g_out_n <= '0';
-        tmds_b_out_p <= '0';
-        tmds_b_out_n <= '0';
-     
+    phy_reset <= not sys_rst_n; -- or not pll_locked;
+
+    process (pclk_phy, b, sys_rst_n)
+    begin
+        if sys_rst_n = '0' then
+            b <= 0;
+        elsif rising_edge(pclk_phy) then
+            if b = 9 then
+                b <= 0;
+            else
+                b <= b+1;
+            end if;
+        end if;
+    end process;
+
+
+    phy_c : entity work.tmds_phy_artix7
+        port map (
+            reset        => phy_reset,
+            pix_clk      => pclk,
+            phy_clk      => pclk_phy,
+	b=>b,
+            din          => c_p10,
+            tmds_out_p   => tmds_c_out_p,
+            tmds_out_n   => tmds_c_out_n
+            );
+
+    phy_r : entity work.tmds_phy_artix7
+        port map (
+            reset        => phy_reset,
+            pix_clk      => pclk,
+            phy_clk      => pclk_phy,
+	b=>b,
+            din          => r_p10,
+            tmds_out_p   => tmds_r_out_p,
+            tmds_out_n   => tmds_r_out_n
+            );
+
+
+    phy_g : entity work.tmds_phy_artix7
+        port map (
+            reset        => phy_reset,
+            pix_clk      => pclk,
+            phy_clk      => pclk_phy,
+	b=>b,
+            din          => g_p10,
+            tmds_out_p   => tmds_g_out_p,
+            tmds_out_n   => tmds_g_out_n
+            );
+
+
+    phy_b : entity work.tmds_phy_artix7
+        port map (
+            reset        => phy_reset,
+            pix_clk      => pclk,
+            phy_clk      => pclk_phy,
+	b=>b,
+            din          => b_p10,
+            tmds_out_p   => tmds_b_out_p,
+            tmds_out_n   => tmds_b_out_n
+            );
+
+
+--        tmds_c_out_p <= '0';
+--        tmds_c_out_n <= '0';
+--        tmds_r_out_p <= '0';
+--        tmds_r_out_n <= '0';
+--        tmds_g_out_p <= '0';
+--        tmds_g_out_n <= '0';
+--        tmds_b_out_p <= '0';
+--        tmds_b_out_n <= '0';
+--     
 
 end beh;
diff --git a/fpga/hp_lcd_driver_a7/source/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver_a7/source/tmds_phy_artix7.vhdl
new file mode 100644
index 0000000..295f8b6
--- /dev/null
+++ b/fpga/hp_lcd_driver_a7/source/tmds_phy_artix7.vhdl
@@ -0,0 +1,85 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity tmds_phy_artix7 is
+    port (
+        reset  : in  std_logic;
+        pix_clk   : in  std_logic;
+        phy_clk   : in  std_logic;
+        din        : in  std_logic_vector(9 downto 0);
+	b:	in natural;
+        tmds_out_p : out std_logic;
+        tmds_out_n : out std_logic
+        );
+end tmds_phy_artix7;
+
+
+architecture beh of tmds_phy_artix7 is
+
+    signal ld : std_logic_vector(9 downto 0);
+    signal sr : std_logic_vector(9 downto 0);
+
+signal s:std_logic;
+
+begin
+
+
+   process(pix_clk)
+   begin
+      if rising_edge(pix_clk) then 
+            ld <= din;
+      end if;
+   end process;
+
+
+-- Using ODDR
+--   process(phy_clk)
+--   begin
+--      if rising_edge(phy_clk) then 
+--	 if b=0 then
+--              sr<= ld;
+--         else
+--            sr(7 downto 0) <= sr  (9 downto 2);
+--         end if;
+--      end if;
+--   end process;
+--
+--ODDR_inst : ODDR
+--generic map(
+--   DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+--   INIT => '0',   -- Initial value for Q port ('1' or '0')
+--   SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
+--port map (
+--   Q => s,   -- 1-bit DDR output
+--   C => phy_clk,    -- 1-bit clock input
+--   CE => '1',  -- 1-bit clock enable input
+--   D1 => sr(0),  -- 1-bit data input (positive edge)
+--   D2 => sr(1),  -- 1-bit data input (negative edge)
+--   R => '0',    -- 1-bit reset input
+--   S => '0'     -- 1-bit set input
+--);
+
+
+-- Using a shift register
+   process(phy_clk)
+   begin
+      if rising_edge(phy_clk) then 
+	 if b=0 then
+            sr<= ld;
+         else
+            sr(8 downto 0) <= sr  (9 downto 1);
+            s<=sr(0);
+         end if;
+      end if;
+   end process;
+
+
+
+   od :OBUFDS port map (O=>tmds_out_p, OB=>tmds_out_n,I=>s);
+
+end beh;
diff --git a/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl b/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl
index 79af3e6..d2d1c3c 100644
--- a/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl
@@ -3,8 +3,8 @@ use ieee.std_logic_1164.all;
 
 entity vram is
     generic (
-        addr_width  : natural := 17;
-        video_width : natural := 2
+        addr_width  : natural := 18;
+        video_width : natural := 6
         );
     port (
         wr_clk  : in  std_logic;
@@ -21,6 +21,18 @@ architecture beh of vram is
     signal wr_en_v : std_logic_vector(0 downto 0);
 begin
 
-rd_data <= (others =>'0');
+    wr_en_v(0) <= wr_en;
 
+    bmg0: entity work.blk_mem_gen_0
+        port map (
+		ena => '1',
+		enb=>'1',
+            clka  => wr_clk,
+            wea   => wr_en_v,
+            addra => wr_addr,
+            dina  => wr_data,
+            clkb  => rd_clk,
+            doutb => rd_data,
+            addrb => rd_addr
+            );
 end beh;