move a7 up a directory

26 files changed, 62 insertions, 90 deletions

diff --git a/fpga/hp_lcd_driver_a7/Makefile b/fpga/hp_lcd_driver_a7/Makefile
index f2a4ee9..aa94c04 100644
--- a/fpga/hp_lcd_driver_a7/Makefile
+++ b/fpga/hp_lcd_driver_a7/Makefile
@@ -12,45 +12,38 @@ endif
 
 BUILD=build-${BOARD}
 
-#ifeq (${BOARD},rando_a7) 
-#S=200
-#A=125
-#else ifeq (${BOARD},litefury)
-#S=200
-#A=125
-#else ifeq (${BOARD},sitlinv_7k325)
-#S=333
-#A=125
-#endif
-
 IP= \
-	source/ip/blk_mem_gen_0.tcl \
-	source/ip/mmcm_0.tcl \
-	source/ip/mmcm_1.tcl 
+	artix7_ip/blk_mem_gen_0.tcl \
+	artix7_ip/mmcm_0.tcl \
+	artix7_ip/mmcm_1.tcl 
 
-#
-#
-#
-#
-#	source/ip/f_11x512_ft.tcl \
-#	source/ip/fa_19x512_ft_${S}_${A}.tcl \
-#	source/ip/fa_32x8k_ft_${S}_${A}.tcl \
-#	source/ip/fa_64x8k_ft_${S}_${A}.tcl \
-#	source/ip/fa_8x4k_ft_${A}_${S}.tcl \
-#	source/ip/fa_8x4k_ft_${S}_${A}.tcl \
-#	source/ip/mmcm_0.tcl \
-#	source/ip/dma_block_0.tcl \
-#	source/ip/axi_crossbar_2_1_MDW_LAW.tcl \
-#	source/ip/axi_dwidth_converter_128_MDW_LAW_4.tcl \
-#	source/ip/axi_protocol_converter_lite_full_64_LAW.tcl \
-#	source/ip/axi_dwidth_converter_64_MDW_LAW_1.tcl \
-#	source/ip/axi_clock_converter_MDW_MAW_4.tcl \
-#	source/ip/mig_7series_${BOARD}.tcl \
 
 BIT=${BUILD}/out/hp_lcd_driver.bit
 
-IP_STAMP=${IP:source/ip/%.tcl=${BUILD}/ip/%/stamp}
-SRCS=$(shell find source -type f -print ) 
+IP_STAMP=${IP:artix7_ip/%.tcl=${BUILD}/ip/%/stamp}
+SRCS= ${IP} \
+	artix7_config.tcl \
+	artix7_hp_lcd_driver.tcl \
+	rando_a7.tcl \
+	rando_a7.xdc \
+	clkgen_artix7.vhdl \
+	debounce.vhdl \
+	delay.vhdl \
+	edge_det.vhdl \
+	hp_lcd_driver.vhdl \
+	input_formatter.vhdl \
+	input_stage.vhdl \
+	output_analog.vhdl \
+	output_formatter.vhdl \
+	output_stage.vhdl \
+	synchronizer.vhdl \
+	tmds_encoder.vhdl \
+	tmds_encode.vhdl \
+	tmds_output_artix7.vhdl \
+	tmds_phy_artix7.vhdl \
+	vram_artix7.vhdl
+
+
 
 OPENOCD=openocd -f openocd/${BOARD}.cfg
 
@@ -58,17 +51,16 @@ default:  ${BUILD}/build.stamp
 
 ${BUILD}/build.stamp:${SRCS} ${IP_STAMP}
 	mkdir -p ${BUILD}
-	(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch  -source ../source/hp_lcd_driver.tcl)
+	(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch  -source ../artix7_hp_lcd_driver.tcl)
 	touch $@
 
-${BUILD}/ip/%/stamp:source/ip/%.tcl
+${BUILD}/ip/%/stamp:artix7_ip/%.tcl
 	mkdir -p ${BUILD}/ip
 	/bin/rm -rf $(dir $@)
 	(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../$<) && touch $@
 
 
 clean:
-	${MAKE} -C proxy clean
 	/bin/rm -rf build-*
 	
 
diff --git a/fpga/hp_lcd_driver_a7/artix7_config.tcl b/fpga/hp_lcd_driver_a7/artix7_config.tcl
new file mode 100644
index 0000000..65628b6
--- /dev/null
+++ b/fpga/hp_lcd_driver_a7/artix7_config.tcl
@@ -0,0 +1,26 @@
+#
+set board $::env(BOARD)
+set board_tcl $source_dir/$board.tcl
+set build_dir .
+set ip_dir $build_dir/ip
+set bd_dir $build_dir/bd
+set ipl_dir $build_dir/ip_library
+set output_dir $build_dir/out
+source $board_tcl
+create_project -in_memory  -part $part_num
+
+file mkdir $build_dir
+file mkdir $bd_dir
+file mkdir $ip_dir
+file mkdir $ipl_dir
+file mkdir $output_dir
+
+#WARNING: [Vivado 12-13651] The IP file '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0/mmcm_0.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands.
+set_msg_config -id 12-13651 -suppress
+
+
+
+#WARNING: [Synth 8-3848] Net dma_axi_awid in module/entity pcie_tpm_widget does not have driver. [/root/projects/tpm_interposer/logic_analyzer/source/pcie_tpm_widget.vhdl:88]
+#set_msg_config -id 8-3848 -new_severity ERROR
+
+
diff --git a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl b/fpga/hp_lcd_driver_a7/artix7_hp_lcd_driver.tcl
index 618895f..684e493 100644
--- a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl
+++ b/fpga/hp_lcd_driver_a7/artix7_hp_lcd_driver.tcl
@@ -1,7 +1,7 @@
 #
 set source_dir [file dirname [file normalize [info script]]]
 
-source $source_dir/config.tcl
+source $source_dir/artix7_config.tcl
 
 file mkdir $output_dir
 
@@ -19,8 +19,8 @@ if {[llength $files] != 0} {
 #read_xdc $early_xdc
 
 #read_verilog [ glob ../source/*.v ]
-read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ]
-#read_vhdl -vhdl2008 -library work { clkgen_artix7.vhdl debounce.vhdl delay.vhdl edge_det.vhdl hp_lcd_driver.vhdl input_formatter.vhdl input_stage.vhdl output_analog.vhdl output_formatter.vhdl output_stage.vhdl synchronizer.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_output_artix7.vhdl tmds_phy_artix7.vhdl vram_artix7.vhdl }
+#read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ]
+read_vhdl -vhdl2008 -library work { ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../hp_lcd_driver.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl }
 
 set generics {}
 append generics { } "video_width=$video_width"
diff --git a/fpga/hp_lcd_driver_a7/source/ip/blk_mem_gen_0.tcl b/fpga/hp_lcd_driver_a7/artix7_ip/blk_mem_gen_0.tcl
index 0c94aab..84626aa 100644
--- a/fpga/hp_lcd_driver_a7/source/ip/blk_mem_gen_0.tcl
+++ b/fpga/hp_lcd_driver_a7/artix7_ip/blk_mem_gen_0.tcl
@@ -2,7 +2,7 @@
 
 set source_dir [file dirname [file dirname [file normalize [info script]]]]
 
-source $source_dir/config.tcl
+source $source_dir/artix7_config.tcl
 
 create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name blk_mem_gen_0 -dir $ip_dir
 
diff --git a/fpga/hp_lcd_driver_a7/source/ip/mmcm_0.tcl b/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_0.tcl
index 70fc435..a49c8f2 100644
--- a/fpga/hp_lcd_driver_a7/source/ip/mmcm_0.tcl
+++ b/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_0.tcl
@@ -1,6 +1,6 @@
 set source_dir [file dirname [file dirname [file normalize [info script]]]]
 
-source $source_dir/config.tcl
+source $source_dir/artix7_config.tcl
 
 create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_0 -dir $ip_dir
 
diff --git a/fpga/hp_lcd_driver_a7/source/ip/mmcm_1.tcl b/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_1.tcl
index dba6201..eb2143d 100644
--- a/fpga/hp_lcd_driver_a7/source/ip/mmcm_1.tcl
+++ b/fpga/hp_lcd_driver_a7/artix7_ip/mmcm_1.tcl
@@ -1,6 +1,6 @@
 set source_dir [file dirname [file dirname [file normalize [info script]]]]
 
-source $source_dir/config.tcl
+source $source_dir/artix7_config.tcl
 
 create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_1 -dir $ip_dir
 
diff --git a/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl b/fpga/hp_lcd_driver_a7/clkgen_artix7.vhdl
index f7f8971..f7f8971 100644
--- a/fpga/hp_lcd_driver_a7/source/clkgen_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/clkgen_artix7.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/debounce.vhdl b/fpga/hp_lcd_driver_a7/debounce.vhdl
index 286367d..286367d 100644
--- a/fpga/hp_lcd_driver_a7/source/debounce.vhdl
+++ b/fpga/hp_lcd_driver_a7/debounce.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/delay.vhdl b/fpga/hp_lcd_driver_a7/delay.vhdl
index 66c5c5d..66c5c5d 100644
--- a/fpga/hp_lcd_driver_a7/source/delay.vhdl
+++ b/fpga/hp_lcd_driver_a7/delay.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/edge_det.vhdl b/fpga/hp_lcd_driver_a7/edge_det.vhdl
index 2a592a5..2a592a5 100644
--- a/fpga/hp_lcd_driver_a7/source/edge_det.vhdl
+++ b/fpga/hp_lcd_driver_a7/edge_det.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver_a7/hp_lcd_driver.vhdl
index 755c422..755c422 100644
--- a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver_a7/hp_lcd_driver.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl b/fpga/hp_lcd_driver_a7/input_formatter.vhdl
index 35916f5..35916f5 100644
--- a/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl
+++ b/fpga/hp_lcd_driver_a7/input_formatter.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/input_stage.vhdl b/fpga/hp_lcd_driver_a7/input_stage.vhdl
index c124a59..c124a59 100644
--- a/fpga/hp_lcd_driver_a7/source/input_stage.vhdl
+++ b/fpga/hp_lcd_driver_a7/input_stage.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/output_analog.vhdl b/fpga/hp_lcd_driver_a7/output_analog.vhdl
index af9eb71..af9eb71 100644
--- a/fpga/hp_lcd_driver_a7/source/output_analog.vhdl
+++ b/fpga/hp_lcd_driver_a7/output_analog.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/output_formatter.vhdl b/fpga/hp_lcd_driver_a7/output_formatter.vhdl
index 558c222..558c222 100644
--- a/fpga/hp_lcd_driver_a7/source/output_formatter.vhdl
+++ b/fpga/hp_lcd_driver_a7/output_formatter.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/output_stage.vhdl b/fpga/hp_lcd_driver_a7/output_stage.vhdl
index 56f4ae4..56f4ae4 100644
--- a/fpga/hp_lcd_driver_a7/source/output_stage.vhdl
+++ b/fpga/hp_lcd_driver_a7/output_stage.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/rando_a7.tcl b/fpga/hp_lcd_driver_a7/rando_a7.tcl
index a596e1e..cfaa74d 100644
--- a/fpga/hp_lcd_driver_a7/source/rando_a7.tcl
+++ b/fpga/hp_lcd_driver_a7/rando_a7.tcl
@@ -1,5 +1,5 @@
 #
 set part_num "xc7a35tfgg484-2"
-set normal_xdc "../source/rando_a7.xdc"
+set normal_xdc "../rando_a7.xdc"
 set use_pclk 1
 set video_width 6
diff --git a/fpga/hp_lcd_driver_a7/source/rando_a7.xdc b/fpga/hp_lcd_driver_a7/rando_a7.xdc
index e6460b8..e6460b8 100644
--- a/fpga/hp_lcd_driver_a7/source/rando_a7.xdc
+++ b/fpga/hp_lcd_driver_a7/rando_a7.xdc
diff --git a/fpga/hp_lcd_driver_a7/source/config.tcl b/fpga/hp_lcd_driver_a7/source/config.tcl
deleted file mode 100644
index 238781a..0000000
--- a/fpga/hp_lcd_driver_a7/source/config.tcl
+++ /dev/null
@@ -1,42 +0,0 @@
-#
-#set LA_ADDR_WIDTH 34
-
-set board $::env(BOARD)
-set board_tcl $source_dir/$board.tcl
-set build_dir .
-set ip_dir $build_dir/ip
-set bd_dir $build_dir/bd
-set ipl_dir $build_dir/ip_library
-set output_dir $build_dir/out
-source $board_tcl
-create_project -in_memory  -part $part_num
-
-file mkdir $build_dir
-file mkdir $bd_dir
-file mkdir $ip_dir
-file mkdir $ipl_dir
-file mkdir $output_dir
-
-#WARNING: [Vivado 12-13651] The IP file '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0/mmcm_0.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands.
-set_msg_config -id 12-13651 -suppress
-
-
-
-#WARNING: [Vivado 12-584] No ports matched 'spi_mosi'. [/root/projects/tpm_interposer/logic_analyzer/source/sitlinv-7k325.xdc:215]
-#set_msg_config -id 12-584 -suppress
-
-#WARNING: [Synth 8-3917] design pcie_tpm_widget has port led_d1 driven by constant 0
-#set_msg_config -id 8-3917 -suppress
-
-#WARNING: [Vivado 12-13651] The IP file '/root/projects/tpm_interposer/logic_analyzer/build-sitlinv-7k325/ip/xdma_0/xdma_0.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/root/projects/tpm_interposer/logic_analyzer/build-sitlinv-7k325/ip/xdma_0'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands.
-#set_msg_config -id 12-13651 -suppress
-
-#WARNING: [Synth 8-2551] possible infinite loop; process does not have a wait statement [/root/projects/tpm_interposer/logic_analyzer/source/pcie.vhdl:123]
-#set_msg_config -id 8-2551 -suppress
-
-#WARNING: [Synth 8-3848] Net dma_axi_awid in module/entity pcie_tpm_widget does not have driver. [/root/projects/tpm_interposer/logic_analyzer/source/pcie_tpm_widget.vhdl:88]
-#set_msg_config -id 8-3848 -new_severity ERROR
-
-#CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'la_i/fifo_to_axi_i/axi_bready_reg/Q' [/root/projects/tpm_interposer/pcie-tpm-emulator/source/fifo_to_axi.vhdl:46]
-#set_msg_config -id 8-6859 -new_severity ERROR
-
diff --git a/fpga/hp_lcd_driver_a7/source/rando_a7_early.xdc b/fpga/hp_lcd_driver_a7/source/rando_a7_early.xdc
deleted file mode 100644
index e234ae6..0000000
--- a/fpga/hp_lcd_driver_a7/source/rando_a7_early.xdc
+++ /dev/null
@@ -1,4 +0,0 @@
-# "Early" constraints file
-# Evaluated before integrated IP
-
-
diff --git a/fpga/hp_lcd_driver_a7/source/synchronizer.vhdl b/fpga/hp_lcd_driver_a7/synchronizer.vhdl
index 302cef9..302cef9 100644
--- a/fpga/hp_lcd_driver_a7/source/synchronizer.vhdl
+++ b/fpga/hp_lcd_driver_a7/synchronizer.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/tmds_encode.vhdl b/fpga/hp_lcd_driver_a7/tmds_encode.vhdl
index fe69a56..fe69a56 100644
--- a/fpga/hp_lcd_driver_a7/source/tmds_encode.vhdl
+++ b/fpga/hp_lcd_driver_a7/tmds_encode.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/tmds_encoder.vhdl b/fpga/hp_lcd_driver_a7/tmds_encoder.vhdl
index 40f8dd4..40f8dd4 100644
--- a/fpga/hp_lcd_driver_a7/source/tmds_encoder.vhdl
+++ b/fpga/hp_lcd_driver_a7/tmds_encoder.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl b/fpga/hp_lcd_driver_a7/tmds_output_artix7.vhdl
index 7370bb7..7370bb7 100644
--- a/fpga/hp_lcd_driver_a7/source/tmds_output_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/tmds_output_artix7.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver_a7/tmds_phy_artix7.vhdl
index 8c8106e..8c8106e 100644
--- a/fpga/hp_lcd_driver_a7/source/tmds_phy_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/tmds_phy_artix7.vhdl
diff --git a/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl b/fpga/hp_lcd_driver_a7/vram_artix7.vhdl
index 82186e1..82186e1 100644
--- a/fpga/hp_lcd_driver_a7/source/vram_artix7.vhdl
+++ b/fpga/hp_lcd_driver_a7/vram_artix7.vhdl