add common module

12 files changed, 442 insertions, 332 deletions

diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index d7b3eca..8c0c55d 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -1,4 +1,4 @@
-TARGETS= ebaz4205 #rando_a7 #smh-ac415b  #spartan6 #ep4ce6 smh-ac415
+TARGETS= ebaz4205 rando_a7 #smh-ac415b  #spartan6 #ep4ce6 smh-ac415
 #fish:smh-ac415
 
 #better_default: build_rando_a7/hp_lcd_driver.svf
diff --git a/fpga/hp_lcd_driver/artix7.mk b/fpga/hp_lcd_driver/artix7.mk
index 8c3245b..218797c 100644
--- a/fpga/hp_lcd_driver/artix7.mk
+++ b/fpga/hp_lcd_driver/artix7.mk
@@ -19,6 +19,7 @@ SRCS= ${IP} \
 	debounce.vhdl \
 	delay.vhdl \
 	edge_det.vhdl \
+	common.vhdl \
 	hp_lcd_driver.vhdl \
 	input_formatter.vhdl \
 	input_stage.vhdl \
diff --git a/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl
index 3859382..f1558ac 100644
--- a/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl
+++ b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl
@@ -20,7 +20,7 @@ if {[llength $files] != 0} {
 
 #read_verilog [ glob ../source/*.v ]
 #read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ]
-read_vhdl -vhdl2008 -library work { ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../hp_lcd_driver.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl }
+read_vhdl -vhdl2008 -library work { ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../hp_lcd_driver.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl ../common.vhdl }
 
 set generics {}
 append generics { } "video_width=$video_width"
diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl
new file mode 100644
index 0000000..f796421
--- /dev/null
+++ b/fpga/hp_lcd_driver/common.vhdl
@@ -0,0 +1,379 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+use work.all;
+
+-- on the cyclone iv
+-- i_clk/4 = 19.676158
+-- the scope's pixel clock is 19.66080
+-- (p-0.25)*19.66080 = p * 19.676158
+--p=1/[4*(1-(19.676158/19.66080))]=320.04
+
+
+entity common is
+    generic (input_video_width    : natural := 2;
+	     video_width : natural :=2;
+             addr_width     : natural := 18;
+             phase_slip     : natural := 320;
+             i_clk_multiple : natural := 4;
+             use_pclk       : natural := 0;
+             target         : string  := "artix7");
+    port (clk_50m   : in  std_logic;
+          sys_rst_n : in  std_logic;
+          video     : in  std_logic_vector(input_video_width -1 downto 0);
+          hsync_in  : in  std_logic;
+          vsync_in  : in  std_logic;
+          pclk_in   : in  std_logic;
+          r_out     : out std_logic;
+          b_out     : out std_logic;
+          g_out     : out std_logic;
+          hsync_out : out std_logic;
+          vsync_out : out std_logic;
+          hdmi_c_p  : out std_logic;
+          hdmi_c_n  : out std_logic;
+          hdmi_r_p  : out std_logic;
+          hdmi_r_n  : out std_logic;
+          hdmi_g_p  : out std_logic;
+          hdmi_g_n  : out std_logic;
+          hdmi_b_p  : out std_logic;
+          hdmi_b_n  : out std_logic;
+          hdmi_vcc  : out std_logic;
+          i_clk_out : out std_logic;
+          led       : out std_logic;
+	  video_out_data : out std_logic_vector(wideo_width-1 downto 0);
+	  video_out_valid: out std_logic;
+	  video_out_clk : out std_logic;
+	  video_out_index :out std_logic
+);
+
+end common;
+
+architecture Behavioral of common is
+
+    signal video_lut : std_logic_vector (video_width-1 downto 0);
+    signal wr_addr : std_logic_vector(addr_width-1 downto 0);
+    signal wr_data : std_logic_vector(video_width-1 downto 0);
+    signal wr_data_b : std_logic_vector(video_width-1 downto 0);
+    signal wr_en   : std_logic;
+
+    signal rd_addr : std_logic_vector(addr_width-1 downto 0);
+    signal rd_data : std_logic_vector(video_width-1 downto 0);
+
+    signal r : std_logic_vector(7 downto 0);
+    signal g : std_logic_vector(7 downto 0);
+    signal b : std_logic_vector(7 downto 0);
+
+
+    signal clk_locked : std_logic;
+
+    signal i_clk : std_logic;
+
+    signal o_clk     : std_logic;
+    signal o_clk_x2  : std_logic;
+    signal o_clk_phy : std_logic;
+    signal sys_rst   : std_logic;
+
+    signal pa  : natural;
+    signal epk : std_logic;
+    signal ic  : natural;
+
+
+    signal h : natural;
+    signal v : natural;
+
+
+    signal c : natural;
+    signal t : std_logic;
+
+begin
+
+
+-- clocking:
+-- i_clk is 4*(nominal) 20MHz to give us 4 choices of sampling position
+-- o_clk is the output pixel clock
+-- o_clk_x2 is used by the spartan serdes
+-- o_clk_phy is used the the hdmi phy (cylone4 it's o_clk x5, spartan 6 it's o_clk x 10)
+
+    clkgen : entity work.clkgen
+        port map (
+            sys_rst_n => sys_rst_n,
+            clk_in    => clk_50m,
+            i_clk     => i_clk,
+            o_clk     => o_clk,
+            o_clk_x2  => o_clk_x2,
+            o_clk_phy => o_clk_phy,
+            locked    => clk_locked
+            );
+
+
+video_lut <= "1111" when video(0)='1' else
+	     "1011" when video(1)='1' else
+	     "1100" when video(2)='1' else
+	     "1010" when video(3)='1' else
+	     "0011" when video(4)='1' else
+	     "1110" when video(5)='1' else
+	     "1001" when video(6)='1' else
+	     "1101" when video(7)='1' else
+	     "0000";
+
+hdmi_vcc <='1';
+
+
+    process (i_clk, sys_rst_n)
+    begin
+        if sys_rst_n = '0' then
+            ic  <= 0;
+            pa  <= phase_slip;
+            epk <= '0';
+        elsif rising_edge(i_clk) then
+
+            if ic = 0 then
+                epk <= '1';
+                if pa = 0 then
+                    pa <= phase_slip;
+                    ic <= i_clk_multiple;
+                else
+                    ic <= i_clk_multiple-1;
+                    pa <= pa -1;
+                end if;
+            else
+                if epk = '1' then
+                    epk <= '0';
+                end if;
+                ic <= ic-1;
+            end if;
+        end if;
+    end process;
+
+
+    i_clk_out <= epk;
+
+
+    input0 : entity work.input_stage
+        generic map(
+            video_width   => video_width,
+            addr_width    => addr_width,
+            clk_multiple  => i_clk_multiple,
+-- HP54502A
+--            phase         => 1,
+--            h_front_porch => 200,
+--            h_active      => 592,
+--            v_front_porch => 1,
+--            v_active      => 384,
+--            frame_start   => 383,
+--            h_stride      => 384,
+--            v_stride      => 262143,
+-- HP54522A
+            phase         => 1,
+            h_front_porch => 190,
+            h_active      => 640,
+            v_front_porch => 22,
+            v_active      => 384,
+            frame_start   => 383,
+            h_stride      => 384,
+            v_stride      => 524287,
+            phase_slip    => phase_slip,
+            use_pclk      => use_pclk
+            )
+        port map (
+            sys_rst_n => sys_rst_n,
+            clk       => i_clk,
+            video_in  => video_lut,
+            pclk_in   => pclk_in,
+            hsync_in  => not hsync_in,
+            vsync_in  => not vsync_in,
+
+            video_out => wr_data,
+            addr_out  => wr_addr,
+            wren_out  => wr_en,
+	    index_out => wr_index
+            );
+
+video_out_data <= wr_data;
+video_out_valid <= wr_en;
+video_out_index <= wr_index;
+video_out_clk <=i_clk;
+
+
+
+--
+--    process (i_clk) begin
+--      if sys_rst_n='0' then
+--              h<=0;
+--              v<=0;
+--              wr_addr <=(others =>'0');
+--      elsif rising_edge(i_clk) then
+--              if h /= 383 then
+--                      h<=h+1;
+--                      wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
+--              else
+--                      h<=0;
+--                      if v /= 591 then
+--                      v<=v+1;
+--                      wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
+--                      else
+--                      v<=0;
+--                      wr_addr <=(others =>'0');
+--                      end if;
+--              end if;
+--      end if;
+--     end process;
+--
+--    wr_en <= '1';
+--      
+--    wr_data <="01" when (h=0) or (h=383) or (v=0) or (v=591)
+--              else "00";
+--
+
+    vram0 : entity work.vram
+        generic map (
+            video_width => video_width,
+            addr_width  => addr_width
+            )
+        port map (
+            wr_clk  => i_clk,
+            wr_en   => wr_en,
+            wr_addr => wr_addr,
+            wr_data => wr_data,
+            rd_clk  => o_clk,
+            rd_addr => rd_addr,
+            rd_data => rd_data
+            );
+
+
+
+--   r<=x"00";
+--   b<=x"00";
+
+
+
+
+    r<=x"ff" when rd_data(0)='1' else
+	 x"00";
+
+--    r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else
+--	 x"80" when rd_data(0)='1' else
+--	 x"00";
+
+    g<=x"ff" when rd_data(1)='1' and rd_data(3)='1' else
+	 x"80" when rd_data(1)='1' else
+	 x"00";
+    b<=x"ff" when rd_data(2)='1' and rd_data(3)='1' else
+	 x"80" when rd_data(2)='1' else
+	 x"00";
+
+    
+
+--"ff" when rd_data(1) = '1' else
+--         x"80" when rd_data(0) = '1' else
+--      ix"00";
+
+
+
+
+    output0 : entity work.output_stage
+
+-- didn't work for me from this thing, only from mac, works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
+--  Modeline "384x592_80.00"  25.40  384 408 448 512  592 593 596 620  -HSync +Vsync
+
+        generic map (
+            target     => target,
+            addr_width => addr_width,
+--            h_active     => 384,
+--            h_sync_start => 400,
+--            h_sync_end   => 440,
+--            h_total      => 640,
+--            v_active     => 592,
+--            v_sync_start => 593,
+--            v_sync_end   => 596,
+--            v_total      => 613,
+--            h_stride     => 1,
+--            v_stride     => 384
+
+-- HP54502A
+--            h_active     => 384,
+--            h_sync_start => 400,
+--            h_sync_end   => 440,
+--            h_total      => 660,
+--            v_active     => 592,
+--            v_sync_start => 593,
+--            v_sync_end   => 596,
+--            v_total      => 613,
+--            h_stride     => 1,
+--            v_stride     => 384
+
+-- HP54522A
+            h_active     => 384,
+            h_sync_start => 400,
+            h_sync_end   => 456,
+            h_total      => 660,
+--            h_active     => 417,
+--            h_sync_start => 440,
+--            h_sync_end   => 480,
+--            h_total      => 660,
+            v_active     => 640,
+            v_sync_start => 641,
+            v_sync_end   => 644,
+            v_total      => 650,
+            h_stride     => 1,
+            v_stride     => 384
+
+--              h_active        => 640,
+--              h_sync_start=>656,
+--              h_sync_end =>752,
+--              h_total=>800,
+--
+--              v_active =>480,
+--              v_sync_start=>490,
+--              v_sync_end=>492,
+--              v_total=>525,
+--              h_stride=>1,
+--              v_stride=>384
+
+            )
+
+        port map(
+            clk_locked => clk_locked,
+            clk        => o_clk,
+            clk_x2     => o_clk_x2,
+            clk_phy    => o_clk_phy,
+            sys_rst_n  => sys_rst_n,
+            vsync_in   => not vsync_in,
+            r_in       => r,
+            g_in       => g,
+            b_in       => b,
+            addr_out   => rd_addr,
+            r_out      => r_out,
+            g_out      => g_out,
+            b_out      => b_out,
+            hsync_out  => hsync_out,
+            vsync_out  => vsync_out,
+            hdmi_c_p   => hdmi_c_p,
+            hdmi_c_n   => hdmi_c_n,
+            hdmi_r_p   => hdmi_r_p,
+            hdmi_r_n   => hdmi_r_n,
+            hdmi_g_p   => hdmi_g_p,
+            hdmi_g_n   => hdmi_g_n,
+            hdmi_b_p   => hdmi_b_p,
+            hdmi_b_n   => hdmi_b_n
+            );
+
+    process (clk_50m, c)
+    begin
+        if rising_edge(clk_50m) then
+
+            if c < 19999999 then
+                c <=c+1;
+            else
+                c <=0;
+                t <=not t;
+            end if;
+        end if;
+    end process;
+
+
+    led <= t;
+
+
+end Behavioral;
+
diff --git a/fpga/hp_lcd_driver/ep4ce15f23c8.mk b/fpga/hp_lcd_driver/ep4ce15f23c8.mk
index 7597aad..33a825b 100644
--- a/fpga/hp_lcd_driver/ep4ce15f23c8.mk
+++ b/fpga/hp_lcd_driver/ep4ce15f23c8.mk
@@ -6,7 +6,7 @@ BUILD=build_${BOARD}
 OF=output_files
 
 PROJECT = hp_lcd_driver
-VSRCS =delay.vhdl synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl  output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl
+VSRCS =delay.vhdl synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl  output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl common.vhdl hp_lcd_driver.vhdl common.vhdl
 IPS= vram_cyclone4_impl.vhdl  clkgen_cyclone4_a_impl.vhdl clkgen_cyclone4_b_impl.vhdl 
 
 DESIGN_NAME=${TOP}
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index d55c34d..2320b26 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -3,13 +3,6 @@ use IEEE.STD_LOGIC_1164.all;
 use IEEE.NUMERIC_STD.all;
 use work.all;
 
--- on the cyclone iv
--- i_clk/4 = 19.676158
--- the scope's pixel clock is 19.66080
--- (p-0.25)*19.66080 = p * 19.676158
---p=1/[4*(1-(19.676158/19.66080))]=320.04
-
-
 entity hp_lcd_driver is
     generic (input_video_width    : natural := 2;
 	     video_width : natural :=2;
@@ -45,322 +38,43 @@ end hp_lcd_driver;
 
 architecture Behavioral of hp_lcd_driver is
 
-    signal video_lut : std_logic_vector (video_width-1 downto 0);
-    signal wr_addr : std_logic_vector(addr_width-1 downto 0);
-    signal wr_data : std_logic_vector(video_width-1 downto 0);
-    signal wr_data_b : std_logic_vector(video_width-1 downto 0);
-    signal wr_en   : std_logic;
-
-    signal rd_addr : std_logic_vector(addr_width-1 downto 0);
-    signal rd_data : std_logic_vector(video_width-1 downto 0);
-
-    signal r : std_logic_vector(7 downto 0);
-    signal g : std_logic_vector(7 downto 0);
-    signal b : std_logic_vector(7 downto 0);
-
-
-    signal clk_locked : std_logic;
-
-    signal i_clk : std_logic;
-
-    signal o_clk     : std_logic;
-    signal o_clk_x2  : std_logic;
-    signal o_clk_phy : std_logic;
-    signal sys_rst   : std_logic;
-
-    signal pa  : natural;
-    signal epk : std_logic;
-    signal ic  : natural;
-
-
-    signal h : natural;
-    signal v : natural;
-
-
-    signal c : natural;
-    signal t : std_logic;
-
 begin
 
-
--- clocking:
--- i_clk is 4*(nominal) 20MHz to give us 4 choices of sampling position
--- o_clk is the output pixel clock
--- o_clk_x2 is used by the spartan serdes
--- o_clk_phy is used the the hdmi phy (cylone4 it's o_clk x5, spartan 6 it's o_clk x 10)
-
-    clkgen : entity work.clkgen
-        port map (
-            sys_rst_n => sys_rst_n,
-            clk_in    => clk_50m,
-            i_clk     => i_clk,
-            o_clk     => o_clk,
-            o_clk_x2  => o_clk_x2,
-            o_clk_phy => o_clk_phy,
-            locked    => clk_locked
-            );
-
-
-video_lut <= "1111" when video(0)='1' else
-	     "1011" when video(1)='1' else
-	     "1100" when video(2)='1' else
-	     "1010" when video(3)='1' else
-	     "0011" when video(4)='1' else
-	     "1110" when video(5)='1' else
-	     "1001" when video(6)='1' else
-	     "1101" when video(7)='1' else
-	     "0000";
-
-hdmi_vcc <='1';
-
-
-    process (i_clk, sys_rst_n)
-    begin
-        if sys_rst_n = '0' then
-            ic  <= 0;
-            pa  <= phase_slip;
-            epk <= '0';
-        elsif rising_edge(i_clk) then
-
-            if ic = 0 then
-                epk <= '1';
-                if pa = 0 then
-                    pa <= phase_slip;
-                    ic <= i_clk_multiple;
-                else
-                    ic <= i_clk_multiple-1;
-                    pa <= pa -1;
-                end if;
-            else
-                if epk = '1' then
-                    epk <= '0';
-                end if;
-                ic <= ic-1;
-            end if;
-        end if;
-    end process;
-
-
-    i_clk_out <= epk;
-
-
-    input0 : entity work.input_stage
-        generic map(
-            video_width   => video_width,
-            addr_width    => addr_width,
-            clk_multiple  => i_clk_multiple,
--- HP54502A
---            phase         => 1,
---            h_front_porch => 200,
---            h_active      => 592,
---            v_front_porch => 1,
---            v_active      => 384,
---            frame_start   => 383,
---            h_stride      => 384,
---            v_stride      => 262143,
--- HP54522A
-            phase         => 1,
-            h_front_porch => 190,
-            h_active      => 640,
-            v_front_porch => 22,
-            v_active      => 384,
-            frame_start   => 383,
-            h_stride      => 384,
-            v_stride      => 524287,
-            phase_slip    => phase_slip,
-            use_pclk      => use_pclk
-            )
-        port map (
-            sys_rst_n => sys_rst_n,
-            clk       => i_clk,
-            video_in  => video_lut,
-            pclk_in   => pclk_in,
-            hsync_in  => not hsync_in,
-            vsync_in  => not vsync_in,
-
-            video_out => wr_data,
-            addr_out  => wr_addr,
-            wren_out  => wr_en
-            );
-
---
---    process (i_clk) begin
---      if sys_rst_n='0' then
---              h<=0;
---              v<=0;
---              wr_addr <=(others =>'0');
---      elsif rising_edge(i_clk) then
---              if h /= 383 then
---                      h<=h+1;
---                      wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
---              else
---                      h<=0;
---                      if v /= 591 then
---                      v<=v+1;
---                      wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
---                      else
---                      v<=0;
---                      wr_addr <=(others =>'0');
---                      end if;
---              end if;
---      end if;
---     end process;
---
---    wr_en <= '1';
---      
---    wr_data <="01" when (h=0) or (h=383) or (v=0) or (v=591)
---              else "00";
---
-
-    vram0 : entity work.vram
-        generic map (
-            video_width => video_width,
-            addr_width  => addr_width
-            )
-        port map (
-            wr_clk  => i_clk,
-            wr_en   => wr_en,
-            wr_addr => wr_addr,
-            wr_data => wr_data,
-            rd_clk  => o_clk,
-            rd_addr => rd_addr,
-            rd_data => rd_data
-            );
-
-
-
---   r<=x"00";
---   b<=x"00";
-
-
-
-
-    r<=x"ff" when rd_data(0)='1' else
-	 x"00";
-
---    r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else
---	 x"80" when rd_data(0)='1' else
---	 x"00";
-
-    g<=x"ff" when rd_data(1)='1' and rd_data(3)='1' else
-	 x"80" when rd_data(1)='1' else
-	 x"00";
-    b<=x"ff" when rd_data(2)='1' and rd_data(3)='1' else
-	 x"80" when rd_data(2)='1' else
-	 x"00";
-
-    
-
---"ff" when rd_data(1) = '1' else
---         x"80" when rd_data(0) = '1' else
---      ix"00";
-
-
-
-
-    output0 : entity work.output_stage
-
--- didn't work for me from this thing, only from mac, works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
---  Modeline "384x592_80.00"  25.40  384 408 448 512  592 593 596 620  -HSync +Vsync
-
-        generic map (
-            target     => target,
-            addr_width => addr_width,
---            h_active     => 384,
---            h_sync_start => 400,
---            h_sync_end   => 440,
---            h_total      => 640,
---            v_active     => 592,
---            v_sync_start => 593,
---            v_sync_end   => 596,
---            v_total      => 613,
---            h_stride     => 1,
---            v_stride     => 384
-
--- HP54502A
---            h_active     => 384,
---            h_sync_start => 400,
---            h_sync_end   => 440,
---            h_total      => 660,
---            v_active     => 592,
---            v_sync_start => 593,
---            v_sync_end   => 596,
---            v_total      => 613,
---            h_stride     => 1,
---            v_stride     => 384
-
--- HP54522A
-            h_active     => 384,
-            h_sync_start => 400,
-            h_sync_end   => 456,
-            h_total      => 660,
---            h_active     => 417,
---            h_sync_start => 440,
---            h_sync_end   => 480,
---            h_total      => 660,
-            v_active     => 640,
-            v_sync_start => 641,
-            v_sync_end   => 644,
-            v_total      => 650,
-            h_stride     => 1,
-            v_stride     => 384
-
---              h_active        => 640,
---              h_sync_start=>656,
---              h_sync_end =>752,
---              h_total=>800,
---
---              v_active =>480,
---              v_sync_start=>490,
---              v_sync_end=>492,
---              v_total=>525,
---              h_stride=>1,
---              v_stride=>384
-
-            )
-
-        port map(
-            clk_locked => clk_locked,
-            clk        => o_clk,
-            clk_x2     => o_clk_x2,
-            clk_phy    => o_clk_phy,
-            sys_rst_n  => sys_rst_n,
-            vsync_in   => not vsync_in,
-            r_in       => r,
-            g_in       => g,
-            b_in       => b,
-            addr_out   => rd_addr,
-            r_out      => r_out,
-            g_out      => g_out,
-            b_out      => b_out,
-            hsync_out  => hsync_out,
-            vsync_out  => vsync_out,
-            hdmi_c_p   => hdmi_c_p,
-            hdmi_c_n   => hdmi_c_n,
-            hdmi_r_p   => hdmi_r_p,
-            hdmi_r_n   => hdmi_r_n,
-            hdmi_g_p   => hdmi_g_p,
-            hdmi_g_n   => hdmi_g_n,
-            hdmi_b_p   => hdmi_b_p,
-            hdmi_b_n   => hdmi_b_n
-            );
-
-    process (clk_50m, c)
-    begin
-        if rising_edge(clk_50m) then
-
-            if c < 19999999 then
-                c <=c+1;
-            else
-                c <=0;
-                t <=not t;
-            end if;
-        end if;
-    end process;
-
-
-    led <= t;
-
-
+    common_i : entity work.common
+    generic_map (
+input_video_width => input_video_width,
+video_width => video_width,
+addr_width => addr_width,
+phase_slip => phase_slip,
+i_clk_multiple => i_clk_multiple,
+use_pclk => use_pclk,
+target => target) 
+port map (clk_50m => clk_50m,
+sys_rst_n => sys_rst_n,
+video => video,
+hsync_in => hsync_in,
+vsync_in => vsync_in,
+pclk_in => pclk_in,
+r_out => r_out,
+b_out => b_out,
+g_out => g_out,
+hsync_out => hsync_out,
+vsync_out => vsync_out,
+hdmi_c_p => hdmi_c_p,
+hdmi_c_n => hdmi_c_n,
+hdmi_r_p => hdmi_r_p,
+hdmi_r_n => hdmi_r_n,
+hdmi_g_p => hdmi_g_p,
+hdmi_g_n => hdmi_g_n,
+hdmi_b_p => hdmi_b_p,
+hdmi_b_n => hdmi_b_n,
+hdmi_vcc => hdmi_vcc,
+i_clk_out => i_clk_out,
+led => led,
+video_out_clkd => open,
+video_out_index =>open,
+video_out_data=>open,
+video_out_valid => open
+);
 end Behavioral;
 
diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl
index f8b27c2..b2fa3c9 100644
--- a/fpga/hp_lcd_driver/input_formatter.vhdl
+++ b/fpga/hp_lcd_driver/input_formatter.vhdl
@@ -28,6 +28,7 @@ entity input_formatter is
             pclk      : in  std_logic;
             addr_out  : out std_logic_vector(addr_width-1 downto 0);
             wren_out  : out std_logic;
+	    index_out : out std_logic;
             h_grid    : out std_logic;
             v_grid    : out std_logic
             );
@@ -46,6 +47,7 @@ architecture beh of input_formatter is
 
     signal hsync_ne : std_logic;
     signal hsync_pe : std_logic;
+    signal index:std_logic;
 
     signal v_fp_counter     : natural;
     signal v_active_counter : natural;
@@ -99,6 +101,7 @@ begin
                     row_addr         <= std_logic_vector(to_unsigned(frame_start, addr_width));
                     v_fp_counter     <= v_front_porch;
                     v_active_counter <= v_active;
+		    index<='1';
                 elsif v_fp_counter /= 0 then
                     v_fp_counter <= v_fp_counter -1;
                 elsif v_active_counter /= 0 then
@@ -115,7 +118,6 @@ begin
             elsif h_fp_counter /= 0 then
                 h_fp_counter <= h_fp_counter -1;
             elsif h_active_counter /= 0 then
-
                 if use_pclk = 0 then
                     if h_div = 0 then
                         wren <= '1';
@@ -137,6 +139,7 @@ begin
                 if wren = '1' then
                     h_active_counter <= h_active_counter -1;
                     addr             <= std_logic_vector(unsigned(addr)+h_stride);
+		    index<='0';
                 end if;
             end if;
         end if;
@@ -144,6 +147,7 @@ begin
 
     addr_out <= addr;
     wren_out <= wren;
+    index_out <= index;
 
 
     h_grid <= '1' when ((h_active_counter mod 16) = (h_active mod 16)) or (h_Active_counter = 1)
diff --git a/fpga/hp_lcd_driver/input_stage.vhdl b/fpga/hp_lcd_driver/input_stage.vhdl
index 1316b6e..8434da8 100644
--- a/fpga/hp_lcd_driver/input_stage.vhdl
+++ b/fpga/hp_lcd_driver/input_stage.vhdl
@@ -31,7 +31,8 @@ entity input_stage is
 
             video_out : out std_logic_vector(video_width-1 downto 0);
             addr_out  : out std_logic_vector(addr_width - 1 downto 0);
-            wren_out  : out std_logic
+            wren_out  : out std_logic;
+            index_out  : out std_logic
             );
 end input_stage;
 
@@ -133,6 +134,7 @@ begin
             vsync     => d_vsync,
             addr_out  => addr,
             wren_out  => wren,
+	    index_out => index_out,
             h_grid    => h_grid,
             v_grid    => v_grid
             );
diff --git a/fpga/hp_lcd_driver/spartan6.mk b/fpga/hp_lcd_driver/spartan6.mk
index 6ea10d9..147e10f 100644
--- a/fpga/hp_lcd_driver/spartan6.mk
+++ b/fpga/hp_lcd_driver/spartan6.mk
@@ -5,7 +5,7 @@ export XILINXD_LICENSE_FILE
 PART=xc6slx9-2-tqg144
 TOP=hp_lcd_driver
 BUILD=build_spartan6
-VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1_spartan6.vhdl tmds_encoder.vhdl tmds_phy_spartan6.vhdl tmds_encode.vhdl tmds_output_spartan6.vhdl  vram_spartan6.vhdl output_stage.vhdl clkgen_spartan6.vhdl hp_lcd_driver.vhdl
+VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1_spartan6.vhdl tmds_encoder.vhdl tmds_phy_spartan6.vhdl tmds_encode.vhdl tmds_output_spartan6.vhdl  vram_spartan6.vhdl output_stage.vhdl clkgen_spartan6.vhdl hp_lcd_driver.vhdl common.vhdl
 UCF=hp_lcd_driver.ucf
 UT=hp_lcd_driver.ut
 IPSRCS=vram_spartan6_impl.xco 
diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk
index 1cfaa1d..9d1652f 100644
--- a/fpga/hp_lcd_driver/zynq7.mk
+++ b/fpga/hp_lcd_driver/zynq7.mk
@@ -21,7 +21,7 @@ SRCS= ${IP} \
 	debounce.vhdl \
 	delay.vhdl \
 	edge_det.vhdl \
-	hp_lcd_driver.vhdl \
+	common.vhdl \
 	input_formatter.vhdl \
 	input_stage.vhdl \
 	output_analog.vhdl \
diff --git a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
index 465656e..3a82e7b 100644
--- a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
+++ b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
@@ -20,7 +20,7 @@ if {[llength $files] != 0} {
 
 #read_verilog [ glob ../source/*.v ]
 #read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ]
-read_vhdl -vhdl2008 -library work { ../zynq_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_zynq7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../hp_lcd_driver.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl }
+read_vhdl -vhdl2008 -library work { ../zynq_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_zynq7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../common.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl }
 
 set generics {}
 append generics { } "video_width=$video_width"
diff --git a/fpga/hp_lcd_driver/zynq_wrapper.vhdl b/fpga/hp_lcd_driver/zynq_wrapper.vhdl
index 8e3bcf4..65961d2 100644
--- a/fpga/hp_lcd_driver/zynq_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq_wrapper.vhdl
@@ -142,13 +142,18 @@ signal eth0_mdio_mdio_t:std_logic;
 signal clk_50m:std_logic;
 signal sys_rst_n:std_logic;
 
+signal vnc_clk:std_logic;
+signal vnc_valid:std_logic;
+signal vnc_data:std_logic_vector(video_width-1 downto 0);
+signal vnc_index:std_logic;
+
 
 begin
 
 
 clk_50m <= hp0_aclk;
 
-hp_lcd_driver_i: entity work.hp_lcd_driver 
+common_i: entity work.common 
     generic map (
 	input_video_width => input_video_width,
 	video_width => video_width,
@@ -178,7 +183,12 @@ hp_lcd_driver_i: entity work.hp_lcd_driver
           hdmi_b_n => hdmi_b_n,
           hdmi_vcc => hdmi_vcc,
           i_clk_out => open,
-	led =>open);
+	led =>open,
+video_out_clk => vnc_clk,
+video_out_valid => vnc_valid,
+video_out_data => vnc_data,
+video_out_index => vnc_index
+);
 
   processing_system7_0_i : entity work.processing_system7_0
     port map (