drop gp bus speed to 50MHz

6 files changed, 13 insertions, 9 deletions

diff --git a/fpga/hp_lcd_driver/fb_hw.vhdl b/fpga/hp_lcd_driver/fb_hw.vhdl
index d3e20a5..5f2df26 100644
--- a/fpga/hp_lcd_driver/fb_hw.vhdl
+++ b/fpga/hp_lcd_driver/fb_hw.vhdl
@@ -97,7 +97,7 @@ begin
             clka  => fb_ps_clk,
             ena   => fb_ps_en,
             wea   => fb_ps_we,
-            addra => fb_ps_addr (15 downto 2),
+            addra => fb_ps_addr (16 downto 2),
             dina  => fb_ps_wrdata,
             douta => fb_ps_rddata,
             clkb  => overlay_clk,
diff --git a/fpga/hp_lcd_driver/kbd_uarts.vhdl b/fpga/hp_lcd_driver/kbd_uarts.vhdl
index a0188f0..c5e583e 100644
--- a/fpga/hp_lcd_driver/kbd_uarts.vhdl
+++ b/fpga/hp_lcd_driver/kbd_uarts.vhdl
@@ -216,7 +216,7 @@ begin
             m_axi_rready  => uc_axi_rready
             );
 
-
+-- JMM we dont gate the interrupt with out1
 
 
     axi_uart16550_0_i0 : entity work.axi_uart16550_0
diff --git a/fpga/hp_lcd_driver/zynq7_ip/axi_bram_ctrl_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/axi_bram_ctrl_0.tcl
index 1933b91..eebb7cc 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/axi_bram_ctrl_0.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/axi_bram_ctrl_0.tcl
@@ -14,7 +14,7 @@ set_property -dict [list \
 	CONFIG.MEM_DEPTH {262144} \
 	CONFIG.PROTOCOL {AXI4} \
 	CONFIG.RD_CMD_OPTIMIZATION {0} \
-	CONFIG.READ_LATENCY {2} \
+	CONFIG.READ_LATENCY {1} \
 	CONFIG.SINGLE_PORT_BRAM {1} \
 	CONFIG.SUPPORTS_NARROW_BURST {0} \
 	CONFIG.USE_ECC {0} \
diff --git a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl
index 588d624..90c426d 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl
@@ -22,8 +22,8 @@ set_property -dict [list  \
 	CONFIG.Enable_B {Always_Enabled}  \
 	CONFIG.Register_PortA_Output_of_Memory_Primitives {true}  \
 	CONFIG.Register_PortB_Output_of_Memory_Primitives {true}  \
-	CONFIG.Port_B_Clock {100}  \
-	CONFIG.Port_B_Write_Rate {50}  \
+	CONFIG.Port_B_Clock {50}  \
+	CONFIG.Port_B_Write_Rate {100}  \
 	CONFIG.Port_B_Enable_Rate {100} \
 	] [get_ips blk_mem_gen_1]
 
diff --git a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
index 4e0b618..2ffe709 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
@@ -13,13 +13,13 @@ set_property -dict [list \
 	CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
 	CONFIG.PCW_USE_M_AXI_GP0 {1} \
         CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
-	CONFIG.PCW_M_AXI_GP0_FREQMHZ {100} \
+	CONFIG.PCW_M_AXI_GP0_FREQMHZ {50} \
 	CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
 	CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
 	CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
 	CONFIG.PCW_USE_M_AXI_GP1 {1} \
         CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
-	CONFIG.PCW_M_AXI_GP1_FREQMHZ {100} \
+	CONFIG.PCW_M_AXI_GP1_FREQMHZ {50} \
 	CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
 	CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
 	CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
index 7f7fdf0..6fb89d6 100644
--- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
@@ -289,6 +289,7 @@ begin
                   video_in_b      => overlay_b
                   );
 
+
     processing_system7_0_i : entity work.processing_system7_0
         port map (
             DDR_Addr      => ddr_addr_io,
@@ -307,10 +308,10 @@ begin
             DDR_DRSTB     => ddr_reset_n_io,
             DDR_WEB       => ddr_we_n_io,
             FCLK_CLK0     => eth0_clk_o,
-            FCLK_CLK1     => gp01_aclk,
+            FCLK_CLK1     => open,
             FCLK_CLK2     => hp0_aclk,
             FCLK_CLK3     => clk_50m_ps,
-            FCLK_RESET1_N => gp01_nrst,
+            FCLK_RESET1_N => open,
             FCLK_RESET2_N => hp0_nrst,
             FCLK_RESET3_N => sys_rst_n,
 
@@ -465,6 +466,9 @@ begin
             IRQ_F2P => pl_irqs
             );
 
+    gp01_aclk <= clk_50m_ps;
+    gp01_nrst <= sys_rst_n;
+
     eth0_mdio_mdio_iobuf : IOBUF
         port map (
             I  => eth0_mdio_mdio_o,