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authorroot <root@new-fish.medaka.james.internal>2025-08-04 15:42:10 +0100
committerroot <root@new-fish.medaka.james.internal>2025-08-04 15:42:10 +0100
commit1a6dbe19eeccc13abef14bb19aad7750a9e901e0 (patch)
tree50a3831ca69416ee1568e8f5c3c8dbd68bb5e2e8 /fpga/hp_lcd_driver
parente55943bbfffaf72968589589a572d3171fba50de (diff)
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Diffstat (limited to 'fpga/hp_lcd_driver')
-rw-r--r--fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl12
-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.vhdl47
-rw-r--r--fpga/hp_lcd_driver/output_formatter.vhdl8
-rw-r--r--fpga/hp_lcd_driver/output_stage.vhdl12
-rw-r--r--fpga/hp_lcd_driver/quartus.mk2
-rw-r--r--fpga/hp_lcd_driver/spartan6.mk10
-rw-r--r--fpga/hp_lcd_driver/vram_spartan6_impl.xco2
7 files changed, 60 insertions, 33 deletions
diff --git a/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl b/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl
index a5bcb9d..9a4bafa 100644
--- a/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl
+++ b/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl
@@ -140,9 +140,9 @@ BEGIN
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
- clk0_divide_by => 50000000,
+ clk0_divide_by => 25,
clk0_duty_cycle => 50,
- clk0_multiply_by => 78642359,
+ clk0_multiply_by => 44,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
@@ -227,7 +227,7 @@ END SYN;
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "78.642357"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "88.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -252,7 +252,7 @@ END SYN;
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "78.64235900"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "88.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -291,9 +291,9 @@ END SYN;
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50000000"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "78642359"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "44"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index 8d1635f..087e475 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -128,22 +128,32 @@ begin
video_width => video_width,
addr_width => addr_width,
clk_multiple => i_clk_multiple,
+-- HP54502A
+-- phase => 1,
+-- h_front_porch => 210,
+-- h_active => 592,
+-- v_front_porch => 1,
+-- v_active => 384,
+-- frame_start => 383,
+-- h_stride => 384,
+-- v_stride => 262143,
+-- HP54522A
phase => 1,
- h_front_porch => 210,
- h_active => 592,
- v_front_porch => 1,
+ h_front_porch => 213,
+ h_active => 640,
+ v_front_porch => 22,
v_active => 384,
frame_start => 383,
h_stride => 384,
- v_stride => 262143,
+ v_stride => 524287,
phase_slip => phase_slip
)
port map (
sys_rst_n => sys_rst_n,
clk => i_clk,
video_in => video,
- hsync_in => hsync_in,
- vsync_in => vsync_in,
+ hsync_in => not hsync_in,
+ vsync_in => not vsync_in,
video_out => wr_data,
addr_out => wr_addr,
@@ -224,14 +234,31 @@ begin
-- h_stride => 1,
-- v_stride => 384
+-- HP54502A
+-- h_active => 384,
+-- h_sync_start => 400,
+-- h_sync_end => 440,
+-- h_total => 660,
+-- v_active => 592,
+-- v_sync_start => 593,
+-- v_sync_end => 596,
+-- v_total => 613,
+-- h_stride => 1,
+-- v_stride => 384
+
+-- HP54522A
h_active => 384,
h_sync_start => 400,
h_sync_end => 440,
h_total => 660,
- v_active => 592,
- v_sync_start => 593,
- v_sync_end => 596,
- v_total => 613,
+-- h_active => 417,
+-- h_sync_start => 440,
+-- h_sync_end => 480,
+-- h_total => 660,
+ v_active => 640,
+ v_sync_start => 641,
+ v_sync_end => 644,
+ v_total => 650,
h_stride => 1,
v_stride => 384
diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl
index d11a8a1..3e26515 100644
--- a/fpga/hp_lcd_driver/output_formatter.vhdl
+++ b/fpga/hp_lcd_driver/output_formatter.vhdl
@@ -122,12 +122,12 @@ begin
end if;
end process;
--- h_grid <= '1' when (h mod 8) = 0
- h_grid <= '1' when (h = 0) or (h = (h_active-1))
+ h_grid <= '1' when (h mod 32) = 0
+-- h_grid <= '1' when (h = 0) or (h = (h_active-1))
else '0';
--- v_grid <= '1' when (v mod 8) = 0
- v_grid <= '1' when (v = 0) or (v = (v_active-1))
+ v_grid <= '1' when (v mod 32) = 0
+-- v_grid <= '1' when (v = 0) or (v = (v_active-1))
else '0';
diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl
index 984c7c5..e02d8ce 100644
--- a/fpga/hp_lcd_driver/output_stage.vhdl
+++ b/fpga/hp_lcd_driver/output_stage.vhdl
@@ -140,15 +140,15 @@ begin
-- o => grid_d
-- );
- r <= r_in;
+-- r <= r_in;
g <= g_in;
- b <= b_in;
+-- b <= b_in;
--- b<=x"00" when grid_d='0'
--- else x"ff";
+ b<=x"00" when v_grid='0'
+ else x"ff";
--- r<=x"00" when h_grid='0'
--- else x"ff";
+ r<=x"00" when h_grid='0'
+ else x"ff";
-- b<=x"00" when v_grid='0' and h_grid='0'
-- else x"ff";
diff --git a/fpga/hp_lcd_driver/quartus.mk b/fpga/hp_lcd_driver/quartus.mk
index 9d1cd0c..21e3f56 100644
--- a/fpga/hp_lcd_driver/quartus.mk
+++ b/fpga/hp_lcd_driver/quartus.mk
@@ -15,7 +15,7 @@ CDF=${BUILD}/${OF}/${PROJECT}.cdf
SVF=${BUILD}/${PROJECT}.svf
PSVF=${BUILD}/${PROJECT}-p.svf
-default:${SVF} ${PSVF}
+default:${SVF} #${PSVF}
echo ${PSVF}
diff --git a/fpga/hp_lcd_driver/spartan6.mk b/fpga/hp_lcd_driver/spartan6.mk
index 0d0f90e..6ea10d9 100644
--- a/fpga/hp_lcd_driver/spartan6.mk
+++ b/fpga/hp_lcd_driver/spartan6.mk
@@ -89,11 +89,11 @@ ${BIT}:${NCD} ${UT}
${SVF}:${BIT}
( cd ${BUILD} && \
- echo -e "setMode -bs \n\
- setCable -p svf -file \"$(call relpath,${SVF},${BUILD})\" \n\
- addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\" \n\
- program -p 1 \n\
- quit \n" > impact.run &&\
+ echo "setMode -bs" > impact.run && \
+ echo "setCable -p svf -file \"$(call relpath,${SVF},${BUILD})\"" >> impact.run && \
+ echo "addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\"" >> impact.run && \
+ echo "program -p 1" >> impact.run && \
+ echo "quit" >> impact.run && \
${ISE_BINDIR_64}/impact -batch impact.run)
diff --git a/fpga/hp_lcd_driver/vram_spartan6_impl.xco b/fpga/hp_lcd_driver/vram_spartan6_impl.xco
index 131955a..9316c77 100644
--- a/fpga/hp_lcd_driver/vram_spartan6_impl.xco
+++ b/fpga/hp_lcd_driver/vram_spartan6_impl.xco
@@ -97,7 +97,7 @@ CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
-CSET write_depth_a=228096
+CSET write_depth_a=266880
CSET write_width_a=2
CSET write_width_b=2
# END Parameters
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-23 12:19:37 +0000