ebaz4205 working with generic build system

1 files changed, 56 insertions, 0 deletions

diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk
new file mode 100644
index 0000000..d04e7ec
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq7.mk
@@ -0,0 +1,56 @@
+BUILD=build_${BOARD}
+
+IP= \
+	zynq7_ip/blk_mem_gen_0.tcl \
+	zynq7_ip/processing_system7_0.tcl 
+
+
+BIT=${BUILD}/out/hp_lcd_driver.bit
+BIN=${BUILD}/out/hp_lcd_driver.bin
+
+IP_STAMP=${IP:zynq7_ip/%.tcl=${BUILD}/ip/%/stamp}
+SRCS= ${IP} \
+	zynq7_config.tcl \
+	zynq7_hp_lcd_driver.tcl \
+	${BOARD}.tcl \
+	${BOARD}.xdc \
+	clkgen_zynq7.vhdl \
+	debounce.vhdl \
+	delay.vhdl \
+	edge_det.vhdl \
+	hp_lcd_driver.vhdl \
+	input_formatter.vhdl \
+	input_stage.vhdl \
+	output_analog.vhdl \
+	output_formatter.vhdl \
+	output_stage.vhdl \
+	synchronizer.vhdl \
+	tmds_encoder.vhdl \
+	tmds_encode.vhdl \
+	tmds_output_artix7.vhdl \
+	tmds_phy_artix7.vhdl \
+	vram_artix7.vhdl \
+	zynq_wrapper.vhdl \
+	fifo_to_axi.vhdl
+
+
+
+OPENOCD=openocd -f openocd/${BOARD}.cfg
+
+default:  ${BUILD}/build.stamp 
+
+${BIN} ${BIT}:${BUILD}/build.stamp
+
+${BUILD}/build.stamp:${SRCS} ${IP_STAMP}
+	mkdir -p ${BUILD}
+	(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch  -source ../zynq7_hp_lcd_driver.tcl)
+	#scripts/xilinx_bit_to_bin.pl ${BIT} ${BIN}
+	touch $@
+
+${BUILD}/ip/%/stamp:zynq7_ip/%.tcl
+	mkdir -p ${BUILD}/ip
+	/bin/rm -rf $(dir $@)
+	(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../$<) && touch $@
+
+
+${BIT}: ${BUILD}/build.stamp