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| author | root <root@new-fish.medaka.james.internal> | 2025-11-11 18:40:48 +0000 |
|---|---|---|
| committer | root <root@new-fish.medaka.james.internal> | 2025-11-11 18:40:48 +0000 |
| commit | 328509b343b38f6479b0006962c1513fb3bc157d (patch) | |
| tree | c58503ae1c607ec42ee80a7ce21561da466403c6 /fpga/hp_lcd_driver/common.vhdl | |
| parent | 9e32cbe9174f2bccda8b85bc1efc92b9a44caecc (diff) | |
| download | hp_instrument_lcds-328509b343b38f6479b0006962c1513fb3bc157d.tar.gz hp_instrument_lcds-328509b343b38f6479b0006962c1513fb3bc157d.tar.bz2 hp_instrument_lcds-328509b343b38f6479b0006962c1513fb3bc157d.zip | |
wip
Diffstat (limited to 'fpga/hp_lcd_driver/common.vhdl')
| -rw-r--r-- | fpga/hp_lcd_driver/common.vhdl | 41 |
1 files changed, 24 insertions, 17 deletions
diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl index 7275184..08895d8 100644 --- a/fpga/hp_lcd_driver/common.vhdl +++ b/fpga/hp_lcd_driver/common.vhdl @@ -43,7 +43,10 @@ entity common is video_out_data : out std_logic_vector(video_width-1 downto 0); video_out_valid : out std_logic; video_out_clk : out std_logic; - video_out_index : out std_logic + video_out_index : out std_logic; + video_in_addr : out std_logic_vector(addr_width-1 downto 0); + video_in_clk : out std_logic; + video_in_data : in std_logic_vector(1 downto 0) ); end common; @@ -62,6 +65,9 @@ architecture Behavioral of common is signal r : std_logic_vector(7 downto 0); signal g : std_logic_vector(7 downto 0); signal b : std_logic_vector(7 downto 0); + signal r_s : std_logic_vector(7 downto 0); + signal g_s : std_logic_vector(7 downto 0); + signal b_s : std_logic_vector(7 downto 0); signal clk_locked : std_logic; @@ -242,34 +248,35 @@ begin rd_data => rd_data ); + video_in_addr <= rd_addr; + video_in_clk <= o_clk; --- r<=x"00"; --- b<=x"00"; - - - - r <= x"ff" when rd_data(0) = '1' else + r_s <= x"ff" when rd_data(0) = '1' else x"00"; - --- r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else --- x"80" when rd_data(0)='1' else --- x"00"; - - g <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else + g_s <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else x"80" when rd_data(1) = '1' else x"00"; - b <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else + b_s <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else x"80" when rd_data(2) = '1' else x"00"; ---"ff" when rd_data(1) = '1' else --- x"80" when rd_data(0) = '1' else --- ix"00"; +-- r <= r_s when video_in_data(1) = '0' else +-- x"00" when video_in_data(0)='0' else +-- x"ff"; +-- g <= g_s when video_in_data(1) = '0' else +-- x"00" when video_in_data(0)='0' else +-- x"ff"; +-- b <= b_s when video_in_data(1) = '0' else +-- x"00" when video_in_data(0)='0' else +-- x"ff"; +r<=r_s; +g<=g_s; +b<=b_s; |
