possibly working both

4 files changed, 109 insertions, 108 deletions

diff --git a/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl b/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl
index 7869b01..0c5b28f 100644
--- a/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl
@@ -26,30 +26,30 @@ architecture Behavioural of clkgen is
     signal reset : std_logic;
 begin
 
-clkgen_impl0: entity work.clkgen_cyclone4_impl 
-	port map (
-		areset	=> not sys_rst_n,
-		inclk0 => clk_in,
-		c0 => clk_100m,
-		c1 => clk_80m,
-		c2 => clk_40m,
-		c3 => clk_20m,
-		locked => pll_locked);
-
-	o_clk <= clk_20m;
+    clkgen_impl0 : entity work.clkgen_cyclone4_impl
+        port map (
+            areset => not sys_rst_n,
+            inclk0 => clk_in,
+            c0     => clk_100m,
+            c1     => clk_80m,
+            c2     => clk_40m,
+            c3     => clk_20m,
+            locked => pll_locked);
+
+    o_clk <= clk_20m;
 --    o_clk_buf : BUFG port map (
 --        I => clk_20m,
 --        O => o_clk);
 --
 
-	o_clk_x2 <= clk_40m;
+    o_clk_x2 <= clk_40m;
 
 --    o_clk_x2_buf : BUFG port map (
 --        I => clk_40m,
 --        O => o_clk_x2);
 --
 
-	i_clk <= clk_80m;
+    i_clk <= clk_80m;
 --    i_clk_buf : BUFG port map (
 --        I => clk_80m,
 --        O => i_clk);
diff --git a/spartan6/hp_lcd_driver/clkgen_cyclone4_impl.vhdl b/spartan6/hp_lcd_driver/clkgen_cyclone4_impl.vhdl
index b3e747c..f9c4797 100644
--- a/spartan6/hp_lcd_driver/clkgen_cyclone4_impl.vhdl
+++ b/spartan6/hp_lcd_driver/clkgen_cyclone4_impl.vhdl
@@ -166,7 +166,7 @@ BEGIN
 		bandwidth_type => "AUTO",
 		clk0_divide_by => 1,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 4,
+		clk0_multiply_by => 2,
 		clk0_phase_shift => "0",
 		clk1_divide_by => 5,
 		clk1_duty_cycle => 50,
@@ -269,7 +269,7 @@ END SYN;
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "80.000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "20.000000"
@@ -306,7 +306,7 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
 -- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "200.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "80.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "20.00000000"
@@ -371,7 +371,7 @@ END SYN;
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
diff --git a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
index 3ea07fe..fe3f850 100644
--- a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
@@ -30,65 +30,66 @@ end tmds_output;
 
 architecture beh of tmds_output is
 
-    signal b: natural;
+    signal b : natural;
 
 begin
 
 
 
-    process (pclk_phy,b,sys_rst_n)  begin
-	if sys_rst_n='1' then
-	b<=0;
-	elsif rising_edge(pclk_phy) then
-	 if b=5 then
-		b<=0;
-	 else
-		b<=b+1;
-	end if;
-	end if;
+    process (pclk_phy, b, sys_rst_n)
+    begin
+        if sys_rst_n = '1' then
+            b <=0;
+        elsif rising_edge(pclk_phy) then
+            if b = 5 then
+                b <=0;
+            else
+                b <=b+1;
+            end if;
+        end if;
     end process;
 
 
-    phy_c : entity work.tmds_phy_cyclone4	
+    phy_c : entity work.tmds_phy_cyclone4
         port map (
-            sys_rst_n	=> sys_rst_n,
-            pclk_phy      => pclk_phy,
-	    b =>b,
-            din          => c_p10,
-            tmds_out_p   => tmds_c_out_p,
-            tmds_out_n   => tmds_c_out_n
+            sys_rst_n  => sys_rst_n,
+            pclk_phy   => pclk_phy,
+            b          => b,
+            din        => c_p10,
+            tmds_out_p => tmds_c_out_p,
+            tmds_out_n => tmds_c_out_n
             );
 
     phy_r : entity work.tmds_phy_cyclone4
         port map (
-            sys_rst_n	=> sys_rst_n,
-            pclk_phy      => pclk_phy,
-	    b =>b,
-            din          => r_p10,
-            tmds_out_p   => tmds_r_out_p,
-            tmds_out_n   => tmds_r_out_n
+            sys_rst_n  => sys_rst_n,
+            pclk_phy   => pclk_phy,
+            b          => b,
+            din        => r_p10,
+            tmds_out_p => tmds_r_out_p,
+            tmds_out_n => tmds_r_out_n
             );
 
 
     phy_g : entity work.tmds_phy_cyclone4
         port map (
-            sys_rst_n	=> sys_rst_n,
-            pclk_phy      => pclk_phy,
-	    b =>b,
-            din          => g_p10,
-            tmds_out_p   => tmds_g_out_p,
-            tmds_out_n   => tmds_g_out_n
+            sys_rst_n  => sys_rst_n,
+            pclk_phy   => pclk_phy,
+            b          => b,
+            din        => g_p10,
+            tmds_out_p => tmds_g_out_p,
+            tmds_out_n => tmds_g_out_n
             );
 
 
     phy_b : entity work.tmds_phy_cyclone4
         port map (
-            sys_rst_n	=> sys_rst_n,
-            pclk_phy      => pclk_phy,
-	    b =>b,
-            din          => b_p10,
-            tmds_out_p   => tmds_b_out_p,
-            tmds_out_n   => tmds_b_out_n
+            sys_rst_n  => sys_rst_n,
+            pclk_phy   => pclk_phy,
+            b          => b,
+            din        => b_p10,
+            tmds_out_p => tmds_b_out_p,
+            tmds_out_n => tmds_b_out_n
             );
 
 end beh;
diff --git a/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl b/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl
index 495f2f1..d4801c5 100644
--- a/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl
@@ -2,82 +2,82 @@ library ieee;
 use ieee.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
+library altera_mf;
+use altera_mf.altera_mf_components.all;
 
 entity tmds_phy_cyclone4 is
     port (
-	sys_rst_n : in std_logic;
-        pclk_phy      : in  std_logic;
-        b            : natural;
-        din          : in  std_logic_vector(9 downto 0);
-        tmds_out_p   : out std_logic;
-        tmds_out_n   : out std_logic
+        sys_rst_n  : in  std_logic;
+        pclk_phy   : in  std_logic;
+        b          :     natural;
+        din        : in  std_logic_vector(9 downto 0);
+        tmds_out_p : out std_logic;
+        tmds_out_n : out std_logic
         );
 end tmds_phy_cyclone4;
 
 
 architecture beh of tmds_phy_cyclone4 is
 
-    signal d_rise  : std_logic_vector(4 downto 0);
-    signal d_fall  : std_logic_vector(4 downto 0);
+    signal d_rise : std_logic_vector(4 downto 0);
+    signal d_fall : std_logic_vector(4 downto 0);
 
-    signal out_p:std_logic_vector(0 downto 0);
-    signal out_n:std_logic_vector(0 downto 0);
+    signal out_p : std_logic_vector(0 downto 0);
+    signal out_n : std_logic_vector(0 downto 0);
 
 begin
 
     process (pclk_phy)
     begin
         if rising_edge(pclk_phy) then
-	    if b=5 then
-		d_rise <= (4=> din(8), 3=> din(6), 2=> din(4), 1=> din(2), 0=> din(0));
-		d_fall <= (4=> din(9), 3=> din(7), 2=> din(5), 1=> din(3), 0=> din(1));
-	    else 
-		d_rise(3 downto 0)<=d_rise(4 downto 1);
-		d_fall(3 downto 0)<=d_fall(4 downto 1);
-	    end if;
+            if b = 5 then
+                d_rise <= (4 => din(8), 3 => din(6), 2 => din(4), 1 => din(2), 0 => din(0));
+                d_fall <= (4 => din(9), 3 => din(7), 2 => din(5), 1 => din(3), 0 => din(1));
+            else
+                d_rise(3 downto 0) <= d_rise(4 downto 1);
+                d_fall(3 downto 0) <= d_fall(4 downto 1);
+            end if;
         end if;
     end process;
 
     obuf_p : ALTDDIO_OUT
-GENERIC MAP (
-extend_oe_disable => "OFF",
-intended_device_family => "Cyclone IV E",
-invert_output => "OFF",
-lpm_hint => "UNUSED",
-lpm_type => "altddio_out",
-oe_reg => "UNREGISTERED",
-power_up_high => "OFF",
-width => 1
-)	
- PORT MAP (
-aclr => not sys_rst_n,
-datain_h => d_rise(0 downto 0),
-datain_l => d_fall(0 downto 0),
-outclock => not pclk_phy,
-dataout => out_p
-);
-tmds_out_p<=out_p(0);
+        generic map (
+            extend_oe_disable      => "OFF",
+            intended_device_family => "Cyclone IV E",
+            invert_output          => "OFF",
+            lpm_hint               => "UNUSED",
+            lpm_type               => "altddio_out",
+            oe_reg                 => "UNREGISTERED",
+            power_up_high          => "OFF",
+            width                  => 1
+            )
+        port map (
+            aclr     => not sys_rst_n,
+            datain_h => d_rise(0 downto 0),
+            datain_l => d_fall(0 downto 0),
+            outclock => not pclk_phy,
+            dataout  => out_p
+            );
+    tmds_out_p <= out_p(0);
 
     obuf_n : ALTDDIO_OUT
-GENERIC MAP (
-extend_oe_disable => "OFF",
-intended_device_family => "Cyclone IV E",
-invert_output => "OFF",
-lpm_hint => "UNUSED",
-lpm_type => "altddio_out",
-oe_reg => "UNREGISTERED",
-power_up_high => "OFF",
-width => 1
-)	
-PORT MAP (
-aclr => not sys_rst_n,
-datain_h => not d_rise(0 downto 0),
-datain_l => not d_fall(0 downto 0),
-outclock => not pclk_phy,
-dataout =>out_n
-);
-tmds_out_n<=out_n(0);
+        generic map (
+            extend_oe_disable      => "OFF",
+            intended_device_family => "Cyclone IV E",
+            invert_output          => "OFF",
+            lpm_hint               => "UNUSED",
+            lpm_type               => "altddio_out",
+            oe_reg                 => "UNREGISTERED",
+            power_up_high          => "OFF",
+            width                  => 1
+            )
+        port map (
+            aclr     => not sys_rst_n,
+            datain_h => not d_rise(0 downto 0),
+            datain_l => not d_fall(0 downto 0),
+            outclock => not pclk_phy,
+            dataout  => out_n
+            );
+    tmds_out_n <= out_n(0);
 
 end beh;