add phase slip tidy

7 files changed, 104 insertions, 106 deletions

diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
index d8a8de3..a8cf948 100644
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -6,7 +6,7 @@ use work.all;
 entity hp_lcd_driver is
     generic (video_width : natural := 2;
              addr_width  : natural := 18;
-	     phase_slip : natural :=320;
+             phase_slip  : natural := 320;
              target      : string  := "spartan6");
     port (clk_50m   : in  std_logic;
           sys_rst_n : in  std_logic;
@@ -26,7 +26,7 @@ entity hp_lcd_driver is
           hdmi_g_n  : out std_logic;
           hdmi_b_p  : out std_logic;
           hdmi_b_n  : out std_logic;
-	  i_clk_out : out std_logic);
+          i_clk_out : out std_logic);
 
 end hp_lcd_driver;
 
@@ -53,10 +53,10 @@ architecture Behavioral of hp_lcd_driver is
     signal o_clk_phy : std_logic;
     signal sys_rst   : std_logic;
 
-    signal pa: natural;
-    signal epk: std_logic;
-    signal ic: natural;
-  
+    signal pa  : natural;
+    signal epk : std_logic;
+    signal ic  : natural;
+
 
 
 begin
@@ -70,39 +70,40 @@ begin
 
     i_clkgen : entity work.input_pll
         port map (
-                areset        => open,
-                inclk0        => clk_50m,
-                c0            => i_clk,
-                locked         => open);
-
-
-    process (i_clk,sys_rst_n) begin
-	if sys_rst_n='0' then
-		ic<=0;
-		pa<=phase_slip;
-		epk<='0';
-	elsif rising_edge(i_clk) then
-
-		if ic =0 then
-			epk<='1';
-			if pa = 0 then
-			    pa<= phase_slip;
-			    ic <= 4;
-			else
-			    ic <=3;
-				pa <= pa -1;
-			end if;
-		else
-			if epk='1' then
-			epk<='0';
-			end if;
-			ic<=ic-1;
-		end if;
-	end if;
-	end process;
-		
-
-i_clk_out <= epk;
+            areset => open,
+            inclk0 => clk_50m,
+            c0     => i_clk,
+            locked => open);
+
+
+    process (i_clk, sys_rst_n)
+    begin
+        if sys_rst_n = '0' then
+            ic  <= 0;
+            pa  <= phase_slip;
+            epk <= '0';
+        elsif rising_edge(i_clk) then
+
+            if ic = 0 then
+                epk <= '1';
+                if pa = 0 then
+                    pa <= phase_slip;
+                    ic <= 4;
+                else
+                    ic <= 3;
+                    pa <= pa -1;
+                end if;
+            else
+                if epk = '1' then
+                    epk <= '0';
+                end if;
+                ic <= ic-1;
+            end if;
+        end if;
+    end process;
+
+
+    i_clk_out <= epk;
 
     clkgen : entity work.clkgen
         port map (
@@ -115,22 +116,22 @@ i_clk_out <= epk;
             locked    => clk_locked
             );
 
-	--i_clk_out <= i_clk;
+    --i_clk_out <= i_clk;
 
     input0 : entity work.input_stage
         generic map(
             video_width   => video_width,
             addr_width    => addr_width,
             clk_multiple  => 4,
-            phase         => 2,
+            phase         => 3,
             h_front_porch => 208,
             h_active      => 592,
             v_front_porch => 2,
             v_active      => 384,
-	    frame_start   => 380,
+            frame_start   => 380,
             h_stride      => 384,
             v_stride      => 262143,
-	    phase_slip    => phase_slip
+            phase_slip    => phase_slip
             )
         port map (
             sys_rst_n => sys_rst_n,
@@ -138,9 +139,7 @@ i_clk_out <= epk;
             video_in  => video,
             hsync_in  => hsync_in,
             vsync_in  => vsync_in,
-            --hsync_in  => '0',
-            --vsync_in  => '0',
-	 
+
             video_out => wr_data,
             addr_out  => wr_addr,
             wren_out  => wr_en);
diff --git a/spartan6/hp_lcd_driver/input_formatter.vhdl b/spartan6/hp_lcd_driver/input_formatter.vhdl
index 6f8af72..9c04493 100644
--- a/spartan6/hp_lcd_driver/input_formatter.vhdl
+++ b/spartan6/hp_lcd_driver/input_formatter.vhdl
@@ -18,10 +18,10 @@ entity input_formatter is
         h_active      : natural := 592;
         v_front_porch : natural := 2;
         v_active      : natural := 384;
-	frame_start   : natural := 0;
+        frame_start   : natural := 0;
         h_stride      : natural := 384;
         v_stride      : natural := 1;
-        phase_slip      : natural := 320);
+        phase_slip    : natural := 320);
     port
         (
             sys_rst_n : in  std_logic;
@@ -30,8 +30,8 @@ entity input_formatter is
             vsync     : in  std_logic;
             addr_out  : out std_logic_vector(addr_width-1 downto 0);
             wren_out  : out std_logic;
-	    h_grid    : out std_logic;
-	    v_grid    : out std_logic
+            h_grid    : out std_logic;
+            v_grid    : out std_logic
             );
 
 end input_formatter;
@@ -52,7 +52,7 @@ architecture beh of input_formatter is
     signal h_active_counter : natural;
     signal h_div            : natural;
 
-    signal phase_accum      : natural;
+    signal phase_accum : natural;
 
 
 begin
@@ -82,12 +82,12 @@ begin
             h_fp_counter     <= 0;
             v_active_counter <= 0;
             v_fp_counter     <= 0;
-	    phase_accum <= 0;
+            phase_accum      <= 0;
         elsif rising_edge(clk) then
             if hsync_pe = '1' then
-		--if v_active_counter = 0 and v_fp_counter=0 then
+                --if v_active_counter = 0 and v_fp_counter=0 then
                 if vsync = '1' then
-                    row_addr         <= std_logic_vector(to_unsigned(frame_start,addr_width));
+                    row_addr         <= std_logic_vector(to_unsigned(frame_start, addr_width));
                     v_fp_counter     <= v_front_porch;
                     v_active_counter <= v_active;
                 elsif v_fp_counter /= 0 then
@@ -97,7 +97,7 @@ begin
 
                     h_fp_counter     <= h_front_porch * clk_multiple + phase;
                     h_active_counter <= h_active;
-	    	    phase_accum <= phase_slip;
+                    phase_accum      <= phase_slip;
                     h_div            <= 0;
 
                     addr     <= row_addr;
@@ -108,22 +108,21 @@ begin
             elsif h_active_counter /= 0 then
 
                 if h_div = 0 then
-                    wren  <= '1';
-		    if phase_accum = 0 then
-			phase_accum <= phase_slip;
-                    	h_div <= clk_multiple ;
-                    else 
-		        phase_accum <= phase_accum-1;
-                        h_div <= clk_multiple -1;
-   		    end if;
-
-                else 
-		   if wren = '1' then
-                    wren             <= '0';
-                    h_active_counter <= h_active_counter -1;
-                    addr             <= std_logic_vector(unsigned(addr)+h_stride);
-			end if;
-                    h_div            <= h_div -1;
+                    wren <= '1';
+                    if phase_accum = 0 then
+                        phase_accum <= phase_slip;
+                        h_div       <= clk_multiple;
+                    else
+                        phase_accum <= phase_accum-1;
+                        h_div       <= clk_multiple -1;
+                    end if;
+                else
+                    if wren = '1' then
+                        wren             <= '0';
+                        h_active_counter <= h_active_counter -1;
+                        addr             <= std_logic_vector(unsigned(addr)+h_stride);
+                    end if;
+                    h_div <= h_div -1;
                 end if;
             end if;
         end if;
@@ -133,11 +132,11 @@ begin
     wren_out <= wren;
 
 
-    h_grid <='1' when (h_active_counter mod 8)=0
-		else '0';
+    h_grid <= '1' when (h_active_counter mod 8) = 0
+              else '0';
 
-    v_grid <='1' when (v_active_counter mod 8)=0
-		else '0';
+    v_grid <= '1' when (v_active_counter mod 8) = 0
+              else '0';
 
 
 end beh;
diff --git a/spartan6/hp_lcd_driver/input_stage.vhdl b/spartan6/hp_lcd_driver/input_stage.vhdl
index 0658abb..e9a7549 100644
--- a/spartan6/hp_lcd_driver/input_stage.vhdl
+++ b/spartan6/hp_lcd_driver/input_stage.vhdl
@@ -13,10 +13,10 @@ entity input_stage is
              h_active        : natural := 592;
              v_front_porch   : natural := 2;
              v_active        : natural := 384;
-             frame_start        : natural := 0;
+             frame_start     : natural := 0;
              h_stride        : natural := 384;
              v_stride        : natural := 1;
-		phase_slip:natural := 320);
+             phase_slip      : natural := 320);
     port
         (
             clk       : in std_logic;
@@ -47,8 +47,8 @@ architecture beh of input_stage is
     signal addr : std_logic_vector(addr_width - 1 downto 0);
     signal wren : std_logic;
 
-    signal h_grid: std_logic;
-    signal v_grid: std_logic;
+    signal h_grid : std_logic;
+    signal v_grid : std_logic;
 
     signal addr_test : std_logic_vector(addr_width - 1 downto 0);
 
@@ -109,10 +109,10 @@ begin
             h_active      => h_active,
             v_front_porch => v_front_porch,
             v_active      => v_active,
-	    frame_start => frame_start,
+            frame_start   => frame_start,
             h_stride      => h_stride,
             v_stride      => v_stride,
-		phase_slip => phase_slip)
+            phase_slip    => phase_slip)
         port map (
             sys_rst_n => sys_rst_n,
             clk       => clk,
@@ -120,8 +120,8 @@ begin
             vsync     => d_vsync,
             addr_out  => addr,
             wren_out  => wren,
-	    h_grid => h_grid,
-	    v_grid => v_grid
+            h_grid    => h_grid,
+            v_grid    => v_grid
             );
 
 
diff --git a/spartan6/hp_lcd_driver/output_formatter.vhdl b/spartan6/hp_lcd_driver/output_formatter.vhdl
index d34bc06..96964ed 100644
--- a/spartan6/hp_lcd_driver/output_formatter.vhdl
+++ b/spartan6/hp_lcd_driver/output_formatter.vhdl
@@ -26,8 +26,8 @@ entity output_formatter is
         blank_out : out std_logic;
         vsync_out : out std_logic;
         hsync_out : out std_logic;
-        h_grid : out std_logic;
-        v_grid : out std_logic
+        h_grid    : out std_logic;
+        v_grid    : out std_logic
         );
 end output_formatter;
 
@@ -119,11 +119,11 @@ begin
         end if;
     end process;
 
-    h_grid <='1' when (h mod 8)=0
-		else '0';
+    h_grid <= '1' when (h mod 8) = 0
+              else '0';
 
-    v_grid <='1' when (v mod 8)=0
-		else '0';
+    v_grid <= '1' when (v mod 8) = 0
+              else '0';
 
 
     addr_out  <= addr;
diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl
index ae1b2bd..831e9f8 100644
--- a/spartan6/hp_lcd_driver/output_stage.vhdl
+++ b/spartan6/hp_lcd_driver/output_stage.vhdl
@@ -71,8 +71,8 @@ architecture beh of output_stage is
     signal g : std_logic_vector(7 downto 0);
     signal b : std_logic_vector(7 downto 0);
 
-signal            h_grid    : std_logic;
-signal            v_grid  : std_logic;
+    signal h_grid : std_logic;
+    signal v_grid : std_logic;
 
     signal r_p10 : std_logic_vector(9 downto 0);
     signal g_p10 : std_logic_vector(9 downto 0);
@@ -112,7 +112,7 @@ begin
             v_total      => v_total,
             h_stride     => h_stride,
             v_stride     => v_stride
-	)
+            )
         port map (
             sys_rst_n => sys_rst_n,
             clk       => clk,
@@ -121,24 +121,24 @@ begin
             blank_out => blank,
             vsync_out => vsync,
             hsync_out => hsync,
-	    h_grid	 => h_grid,
-	    v_grid	 => v_grid
+            h_grid    => h_grid,
+            v_grid    => v_grid
             );
 
 
     addr_out <= addr;
 
 
-    r<=r_in;
-    g<=g_in;
-    b<=b_in;
+    r <=r_in;
+    g <=g_in;
+    b <=b_in;
 
 
 --    r<=x"00" when h_grid='0'
---	    else x"ff";
+--          else x"ff";
 
 --    g<=x"00" when v_grid='0'
---	    else x"ff";
+--          else x"ff";
 
 
 
diff --git a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
index 1421211..8d71bd8 100644
--- a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
@@ -30,7 +30,7 @@ end tmds_output;
 
 architecture beh of tmds_output is
 
-    signal b : natural:=0;
+    signal b : natural := 0;
 
 begin
 
@@ -39,12 +39,12 @@ begin
     process (pclk_phy, b, sys_rst_n)
     begin
         if sys_rst_n = '0' then
-            b <=0;
+            b <= 0;
         elsif rising_edge(pclk_phy) then
             if b = 4 then
-                b <=0;
+                b <= 0;
             else
-                b <=b+1;
+                b <= b+1;
             end if;
         end if;
     end process;
diff --git a/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl b/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl
index bd4835e..6160636 100644
--- a/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl
@@ -26,7 +26,7 @@ architecture beh of tmds_phy_cyclone4 is
     signal out_p : std_logic_vector(0 downto 0);
     signal out_n : std_logic_vector(0 downto 0);
 
-signal bb:natural;
+    signal bb : natural;
 
 begin
 
@@ -37,8 +37,8 @@ begin
             if b = 4 then
                 d_rise <= (4 => din(8), 3 => din(6), 2 => din(4), 1 => din(2), 0 => din(0));
                 d_fall <= (4 => din(9), 3 => din(7), 2 => din(5), 1 => din(3), 0 => din(1));
-                --d_rise <= (4 => din(1), 3 => din(3), 2 => din(5), 1 => din(7), 0 => din(9));
-                --d_fall <= (4 => din(0), 3 => din(2), 2 => din(4), 1 => din(6), 0 => din(8));
+            --d_rise <= (4 => din(1), 3 => din(3), 2 => din(5), 1 => din(7), 0 => din(9));
+            --d_fall <= (4 => din(0), 3 => din(2), 2 => din(4), 1 => din(6), 0 => din(8));
             else
                 d_rise(3 downto 0) <= d_rise(4 downto 1);
                 d_fall(3 downto 0) <= d_fall(4 downto 1);