tidy

3 files changed, 44 insertions, 44 deletions

diff --git a/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl b/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl
index 6caaa8d..e1a9c58 100644
--- a/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/clkgen_cyclone4.vhdl
@@ -69,11 +69,11 @@ begin
 
 
 
-i_clk <= clk_in;
-o_clk <= clk_in;
-o_clk_x2 <= clk_in;
-o_clk_x10 <= clk_in;
-locked <= '1';
+    i_clk     <= clk_in;
+    o_clk     <= clk_in;
+    o_clk_x2  <= clk_in;
+    o_clk_x10 <= clk_in;
+    locked    <= '1';
 
 
 
diff --git a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
index 401c4ec..60ddb6d 100644
--- a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
@@ -113,13 +113,13 @@ begin
 --
 --
 
-        tmds_c_out_p <= '1';
-        tmds_c_out_n <= '0';
-        tmds_r_out_p <= '1';
-        tmds_r_out_n <= '0';
-        tmds_g_out_p <= '1';
-        tmds_g_out_n <= '0';
-        tmds_b_out_p <= '1';
-        tmds_b_out_n <= '0';
- 
+    tmds_c_out_p <= '1';
+    tmds_c_out_n <= '0';
+    tmds_r_out_p <= '1';
+    tmds_r_out_n <= '0';
+    tmds_g_out_p <= '1';
+    tmds_g_out_n <= '0';
+    tmds_b_out_p <= '1';
+    tmds_b_out_n <= '0';
+
 end beh;
diff --git a/spartan6/hp_lcd_driver/vram_cyclone4.vhdl b/spartan6/hp_lcd_driver/vram_cyclone4.vhdl
index 4ccfc73..bafb6b5 100644
--- a/spartan6/hp_lcd_driver/vram_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/vram_cyclone4.vhdl
@@ -1,35 +1,35 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
 
-ENTITY vram IS
-  generic (
-	addr_width:natural :=17;
-	video_width:natural :=2
-  );
-  PORT (
-    wr_clk: in std_logic;
-    wr_en : in std_logic;
-    wr_addr : in STD_LOGIC_VECTOR(addr_width-1 downto 0);
-    wr_data : in std_logic_vector(video_width-1 downto 0);
-    rd_clk : in std_logic;
-    rd_addr : in STD_LOGIC_VECTOR(addr_width-1 downto 0);
-    rd_data : out std_logic_vector(video_width-1 downto 0)
-  );
-END vram;
+entity vram is
+    generic (
+        addr_width  : natural := 17;
+        video_width : natural := 2
+        );
+    port (
+        wr_clk  : in  std_logic;
+        wr_en   : in  std_logic;
+        wr_addr : in  std_logic_vector(addr_width-1 downto 0);
+        wr_data : in  std_logic_vector(video_width-1 downto 0);
+        rd_clk  : in  std_logic;
+        rd_addr : in  std_logic_vector(addr_width-1 downto 0);
+        rd_data : out std_logic_vector(video_width-1 downto 0)
+        );
+end vram;
 
-ARCHITECTURE beh OF vram IS
-BEGIN
+architecture beh of vram is
+begin
 
 
 
-vram_impl0: entity work.vram_cyclone4_impl 
-	port map (
-		wrclock => wr_clk,
-		wren => wr_en,
-		wraddress => wr_addr,
-		data => wr_data,
-		rdclock => rd_clk,
-		q => rd_data,
-		rdaddress => rd_addr
-	);
-END beh;
+    vram_impl0 : entity work.vram_cyclone4_impl
+        port map (
+            wrclock   => wr_clk,
+            wren      => wr_en,
+            wraddress => wr_addr,
+            data      => wr_data,
+            rdclock   => rd_clk,
+            q         => rd_data,
+            rdaddress => rd_addr
+            );
+end beh;