cloud-email/mitmproxy - clone of mitm proxy

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mitmproxy/builtins/clientplayback.py

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mitmproxy/console/master.py

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mitmproxy/console/window.py

3 files changed, 13 insertions, 16 deletions

/* * internal execution defines for qemu * * Copyright (c) 2003 Fabrice Bellard * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* allow to see translation results - the slowdown should be negligible, so we leave it */ #define DEBUG_DISAS #ifndef glue #define xglue(x, y) x ## y #define glue(x, y) xglue(x, y) #define stringify(s) tostring(s) #define tostring(s) #s #endif #if GCC_MAJOR < 3 #define __builtin_expect(x, n) (x) #endif #ifdef __i386__ #define REGPARM(n) __attribute((regparm(n))) #else #define REGPARM(n) #endif /* is_jmp field values */ #define DISAS_NEXT 0 /* next instruction can be analyzed */ #define DISAS_JUMP 1 /* only pc was modified dynamically */ #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ #define DISAS_TB_JUMP 3 /* only pc was modified statically */ struct TranslationBlock; /* XXX: make safe guess about sizes */ #define MAX_OP_PER_INSTR 32 #define OPC_BUF_SIZE 512 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) extern uint16_t gen_opc_buf[OPC_BUF_SIZE]; extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE]; extern uint32_t gen_opc_pc[OPC_BUF_SIZE]; extern uint32_t gen_opc_npc[OPC_BUF_SIZE]; extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; typedef void (GenOpFunc)(void); typedef void (GenOpFunc1)(long); typedef void (GenOpFunc2)(long, long); typedef void (GenOpFunc3)(long, long, long); #if defined(TARGET_I386) void optimize_flags_init(void); #endif extern FILE *logfile; extern int loglevel; int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, int max_code_size, int *gen_code_size_ptr); int cpu_restore_state(struct TranslationBlock *tb, CPUState *env, unsigned long searched_pc, void *puc); int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, int max_code_size, int *gen_code_size_ptr); int cpu_restore_state_copy(struct TranslationBlock *tb, CPUState *env, unsigned long searched_pc, void *puc); void cpu_resume_from_signal(CPUState *env1, void *puc); void cpu_exec_init(void); int page_unprotect(unsigned long address, unsigned long pc, void *puc); void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, int is_cpu_write_access); void tb_invalidate_page_range(target_ulong start, target_ulong end); void tlb_flush_page(CPUState *env, target_ulong addr); void tlb_flush(CPUState *env, int flush_global); int tlb_set_page(CPUState *env, target_ulong vaddr, target_phys_addr_t paddr, int prot, int is_user, int is_softmmu); #define CODE_GEN_MAX_SIZE 65536 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ #define CODE_GEN_HASH_BITS 15 #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) #define CODE_GEN_PHYS_HASH_BITS 15 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) /* maximum total translate dcode allocated */ /* NOTE: the translated code area cannot be too big because on some archs the range of "fast" function calls is limited. Here is a summary of the ranges: i386 : signed 32 bits arm : signed 26 bits ppc : signed 24 bits sparc : signed 32 bits alpha : signed 23 bits */ #if defined(__alpha__) #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) #elif defined(__powerpc__) #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) #else #define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024) #endif //#define CODE_GEN_BUFFER_SIZE (128 * 1024) /* estimated block size for TB allocation */ /* XXX: use a per code average code fragment size and modulate it according to the host CPU */ #if defined(CONFIG_SOFTMMU) #define CODE_GEN_AVG_BLOCK_SIZE 128 #else #define CODE_GEN_AVG_BLOCK_SIZE 64 #endif #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE) #if defined(__powerpc__) #define USE_DIRECT_JUMP #endif #if defined(__i386__) && !defined(_WIN32) #define USE_DIRECT_JUMP #endif typedef struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ target_ulong cs_base; /* CS base for this block */ unsigned int flags; /* flags defining in which context the code was generated */ uint16_t size; /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ uint16_t cflags; /* compile flags */ #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ uint8_t *tc_ptr; /* pointer to the translated code */ struct TranslationBlock *hash_next; /* next matching tb for virtual address */ /* next matching tb for physical address. */ struct TranslationBlock *phys_hash_next; /* first and second physical page containing code. The lower bit of the pointer tells the index in page_next[] */ struct TranslationBlock *page_next[2]; target_ulong page_addr[2]; /* the following data are used to directly call another TB from the code of this one. */ uint16_t tb_next_offset[2]; /* offset of original jump target */ #ifdef USE_DIRECT_JUMP uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ #else uint32_t tb_next[2]; /* address of jump generated code */ #endif /* list of TBs jumping to this one. This is a circular list using the two least significant bits of the pointers to tell what is the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = jmp_first */ struct TranslationBlock *jmp_next[2]; struct TranslationBlock *jmp_first; } TranslationBlock; static inline unsigned int tb_hash_func(unsigned long pc) { return pc & (CODE_GEN_HASH_SIZE - 1); } static inline unsigned int tb_phys_hash_func(unsigned long pc) { return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); } TranslationBlock *tb_alloc(unsigned long pc); void tb_flush(CPUState *env); void tb_link(TranslationBlock *tb); void tb_link_phys(TranslationBlock *tb, target_ulong phys_pc, target_ulong phys_page2); extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE]; extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE]; extern uint8_t *code_gen_ptr; /* find a translation block in the translation cache. If not found, return NULL and the pointer to the last element of the list in pptb */ static inline TranslationBlock *tb_find(TranslationBlock ***pptb, target_ulong pc, target_ulong cs_base, unsigned int flags) { TranslationBlock **ptb, *tb; unsigned int h; h = tb_hash_func(pc); ptb = &tb_hash[h]; for(;;) { tb = *ptb; if (!tb) break; if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags) return tb; ptb = &tb->hash_next; } *pptb = ptb; return NULL; } #if defined(USE_DIRECT_JUMP) #if defined(__powerpc__) static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) { uint32_t val, *ptr; /* patch the branch destination */ ptr = (uint32_t *)jmp_addr; val = *ptr; val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); *ptr = val; /* flush icache */ asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); asm volatile ("sync" : : : "memory"); asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); asm volatile ("sync" : : : "memory");


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