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# This file is dual licensed under the terms of the Apache License, Version
# 2.0, and the BSD License. See the LICENSE file in the root of this repository
# for complete details.

from __future__ import absolute_import, division, print_function

INCLUDES = """
#if !defined(OPENSSL_NO_CMAC)
#include <openssl/cmac.h>
#endif
"""

TYPES = """
static const int Cryptography_HAS_CMAC;
typedef ... CMAC_CTX;
"""

FUNCTIONS = """
CMAC_CTX *CMAC_CTX_new(void);
int CMAC_Init(CMAC_CTX *, const void *, size_t, const EVP_CIPHER *, ENGINE *);
int CMAC_Update(CMAC_CTX *, const void *, size_t);
int CMAC_Final(CMAC_CTX *, unsigned char *, size_t *);
int CMAC_CTX_copy(CMAC_CTX *, const CMAC_CTX *);
void CMAC_CTX_free(CMAC_CTX *);
"""

CUSTOMIZATIONS = """
static const long Cryptography_HAS_CMAC = 1;
"""
ot; YOSYS_NAMESPACE_BEGIN struct AigerReader { RTLIL::Design *design; std::istream &f; RTLIL::IdString clk_name; RTLIL::Module *module; std::string map_filename; bool wideports; const int aiger_autoidx; unsigned M, I, L, O, A; unsigned B, C, J, F; // Optional in AIGER 1.9 unsigned line_count; uint32_t piNum, flopNum; std::vector<RTLIL::Wire*> inputs; std::vector<RTLIL::Wire*> latches; std::vector<RTLIL::Wire*> outputs; std::vector<RTLIL::Wire*> bad_properties; std::vector<RTLIL::Cell*> boxes; std::vector<int> mergeability, initial_state; AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports); void parse_aiger(); void parse_xaiger(); void parse_aiger_ascii(); void parse_aiger_binary(); void post_process(); RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal); }; YOSYS_NAMESPACE_END #endif