docs/hazmat/primitives/asymmetric/serialization.rst


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generated by cgit v1.2.3 (git 2.25.1) at 2025-09-13 09:06:46 +0000
 

/span> randaddr2;
				9: getaddr = randaddr3;
				default: begin
					getaddr = 1 << (2*n-16);
					if (!getaddr) getaddr = xorshift64_state;
				end
			endcase
		end
	endfunction

	reg [DBITS-1:0] memory [0:2**ABITS-1];
	reg [DBITS-1:0] expected_rd, expected_rd_masked;

	event error;
	reg error_ind = 0;

	integer i, j;
	initial begin
		// $dumpfile("testbench.vcd");
		// $dumpvars(0, bram1_tb);

		memory[INIT_ADDR_0] = INIT_DATA_0;
		memory[INIT_ADDR_1] = INIT_DATA_1;
		memory[INIT_ADDR_2] = INIT_DATA_2;
		memory[INIT_ADDR_3] = INIT_DATA_3;

		xorshift64_next;
		xorshift64_next;
		xorshift64_next;
		xorshift64_next;

		randaddr1 = xorshift64_state;
		xorshift64_next;

		randaddr2 = xorshift64_state;
		xorshift64_next;

		randaddr3 = xorshift64_state;
		xorshift64_next;

		clk <= 0;
		for (i = 0; i < 512; i = i+1) begin
			if (i == 0) begin
				WR_EN <= 0;
				RD_ADDR <= INIT_ADDR_0;
			end else
			if (i == 1) begin
				WR_EN <= 0;
				RD_ADDR <= INIT_ADDR_1;
			end else
			if (i == 2) begin
				WR_EN <= 0;
				RD_ADDR <= INIT_ADDR_2;
			end else
			if (i == 3) begin
				WR_EN <= 0;
				RD_ADDR <= INIT_ADDR_3;
			end else begin
				if (DBITS > 64)
					WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
				else
					WR_DATA <= xorshift64_state;
				xorshift64_next;
				WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
				xorshift64_next;
				RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
				WR_EN <= xorshift64_state[55];
				xorshift64_next;
			end

			#1; clk <= 1;
			#1; clk <= 0;

			if (TRANSP) begin
				if (WR_EN) memory[WR_ADDR] = WR_DATA;
				expected_rd = memory[RD_ADDR];
			end else begin
				expected_rd = memory[RD_ADDR];
				if (WR_EN) memory[WR_ADDR] = WR_DATA;
			end

			for (j = 0; j < DBITS; j = j+1)
				expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];

			$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR");
			if (expected_rd_masked !== RD_DATA) begin -> error; error_ind = ~error_ind; end
		end
	end
endmodule