aboutsummaryrefslogtreecommitdiffstats
path: root/docs/hazmat/backends/index.rst
blob: aec7a1e0d4bc095b713cfbd95beda1399d4937bc (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
.. hazmat::

Backends
========

Getting a backend
-----------------

.. currentmodule:: cryptography.hazmat.backends

``cryptography`` aims to support multiple backends to ensure it can provide
the widest number of supported cryptographic algorithms as well as supporting
platform specific implementations.

You can get the default backend by calling :func:`~default_backend`.

The default backend will change over time as we implement new backends and
the libraries we use in those backends changes.


.. function:: default_backend()

    :returns: An object that provides at least
        :class:`~interfaces.CipherBackend`, :class:`~interfaces.HashBackend`, and
        :class:`~interfaces.HMACBackend`.

Individual backends
-------------------

.. toctree::
    :maxdepth: 1

    openssl
    commoncrypto
    multibackend
    interfaces
hlight .vg { color: #dd7700 } /* Name.Variable.Global */ .highlight .vi { color: #3333bb } /* Name.Variable.Instance */ .highlight .vm { color: #336699 } /* Name.Variable.Magic */ .highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -305,13 +305,26 @@ void __init cns3xxx_timer_init(void)
 
 #ifdef CONFIG_CACHE_L2X0
 
-void __init cns3xxx_l2x0_init(void)
+static int cns3xxx_l2x0_enable = 1;
+
+static int __init cns3xxx_l2x0_disable(char *s)
+{
+	cns3xxx_l2x0_enable = 0;
+	return 1;
+}
+__setup("nol2x0", cns3xxx_l2x0_disable);
+
+static int __init cns3xxx_l2x0_init(void)
 {
-	void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
+	void __iomem *base;
 	u32 val;
 
+	if (!cns3xxx_l2x0_enable)
+		return 0;
+
+	base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
 	if (WARN_ON(!base))
-		return;
+		return 0;
 
 	/*
 	 * Tag RAM Control register
@@ -341,7 +354,10 @@ void __init cns3xxx_l2x0_init(void)
 
 	/* 32 KiB, 8-way, parity disable */
 	l2x0_init(base, 0x00500000, 0xfe0f0fff);
+
+	return 0;
 }
+arch_initcall(cns3xxx_l2x0_init);
 
 #endif /* CONFIG_CACHE_L2X0 */
 
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -239,8 +239,6 @@ static struct platform_device *cns3420_p
 
 static void __init cns3420_init(void)
 {
-	cns3xxx_l2x0_init();
-
 	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
 	cns3xxx_ahci_init();
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -16,12 +16,6 @@
 extern struct smp_operations cns3xxx_smp_ops;
 extern void cns3xxx_timer_init(void);
 
-#ifdef CONFIG_CACHE_L2X0
-void __init cns3xxx_l2x0_init(void);
-#else
-static inline void cns3xxx_l2x0_init(void) {}
-#endif /* CONFIG_CACHE_L2X0 */
-
 #ifdef CONFIG_PCI
 extern void __init cns3xxx_pcie_init_late(void);
 #else