# =============================================================================
#               ____ _   _ ____  _          _
#  _ __  _   _ / ___| | | |  _ \| |      __| | ___  _ __ ___
# | '_ \| | | | |  _| |_| | | | | |     / _` |/ _ \| '_ ` _ \
# | |_) | |_| | |_| |  _  | |_| | |___ | (_| | (_) | | | | | |
# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
# |_|    |___/
# =============================================================================
# Authors:
#   Patrick Lehmann
#
# Package module:   DOM: Sequential statements.
#
# License:
# ============================================================================
#  Copyright (C) 2019-2021 Tristan Gingold
#
#  This program is free software: you can redistribute it and/or modify
#  it under the terms of the GNU General Public License as published by
#  the Free Software Foundation, either version 2 of the License, or
#  (at your option) any later version.
#
#  This program is distributed in the hope that it will be useful,
#  but WITHOUT ANY WARRANTY; without even the implied warranty of
#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#  GNU General Public License for more details.
#
#  You should have received a copy of the GNU General Public License
#  along with this program.  If not, see <gnu.org/licenses>.
#
# SPDX-License-Identifier: GPL-2.0-or-later
# ============================================================================
from typing import Iterable

from pydecor import export

from pyGHDL.dom.Concurrent import (
    WaveformElement,
    ParameterAssociationItem,
)  # TODO: move out from concurrent?
from pyGHDL.dom.Range import Range
from pyVHDLModel.SyntaxModel import (
    IfBranch as VHDLModel_IfBranch,
    ElsifBranch as VHDLModel_ElsifBranch,
    ElseBranch as VHDLModel_ElseBranch,
    IfStatement as VHDLModel_IfStatement,
    IndexedChoice as VHDLModel_IndexedChoice,
    RangedChoice as VHDLModel_RangedChoice,
    OthersCase as VHDLModel_OthersCase,
    Case as VHDLModel_Case,
    CaseStatement as VHDLModel_CaseStatement,
    ForLoopStatement as VHDLModel_ForLoopStatement,
    SequentialSimpleSignalAssignment as VHDLModel_SequentialSimpleSignalAssignment,
    SequentialProcedureCall as VHDLModel_SequentialProcedureCall,
    SequentialAssertStatement as VHDLModel_SequentialAssertStatement,
    SequentialReportStatement as VHDLModel_SequentialReportStatement,
    WaitStatement as VHDLModel_WaitStatement,
    Name,
    SequentialStatement,
    ExpressionUnion,
    SequentialChoice,
    SequentialCase,
)


from pyGHDL.libghdl import Iir, utils
from pyGHDL.libghdl.vhdl import nodes
from pyGHDL.dom import DOMMixin, Position, DOMException
from pyGHDL.dom._Utils import GetNameOfNode


@export
class IfBranch(VHDLModel_IfBranch):
    def __init__(
        self,
        branchNode: Iir,
        condition: ExpressionUnion,
        statements: Iterable[SequentialStatement] = None,
    ):
        super().__init__(condition, statements)
        DOMMixin.__init__(self, branchNode)

    @classmethod
    def parse(cls, branchNode: Iir, label: str) -> "IfBranch":
        from pyGHDL.dom._Translate import (
            GetSequentialStatementsFromChainedNodes,
            GetExpressionFromNode,
        )

        condition = GetExpressionFromNode(nodes.Get_Condition(branchNode))
        statementChain = nodes.Get_Sequential_Statement_Chain(branchNode)
        statements = GetSequentialStatementsFromChainedNodes(
            statementChain, "if branch", label
        )

        return cls(branchNode, condition, statements)


@export
class ElsifBranch(VHDLModel_ElsifBranch):
    def __init__(
        self,
        branchNode: Iir,
        condition: ExpressionUnion,
        statements: Iterable[SequentialStatement] = None,
    ):
        super().__init__(condition, statements)
        DOMMixin.__init__(self, branchNode)

    @classmethod
    def parse(cls, branchNode: Iir, condition: Iir, label: str) -> "ElsifBranch":