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#include "gfx.h"

static GListener    gl;
static GHandle      ghContainer1, ghContainer2, ghContainer3;
static GHandle      ghButton1, ghButton2, ghButton3, ghButton4;
static GHandle      ghCheckbox1, ghCheckbox2, ghCheckbox3;

static void createWidgets(void) {
    GWidgetInit wi;

    // Apply some default values for GWIN
    gwinWidgetClearInit(&wi);
    wi.g.show = FALSE;

    // Container 1
    wi.g.width = 300;
    wi.g.height = 220;
    wi.g.y = 40;
    wi.g.x = 10;
    wi.text = "Container 1";
    ghContainer1 = gwinContainerCreate(0, &wi, GWIN_CONTAINER_BORDER);

    wi.g.show = TRUE;

    // Container 2
    wi.g.width = 100;
    wi.g.height = 150;
    wi.g.y = 55;
    wi.g.x = 10;
    wi.g.parent = ghContainer1;
    wi.text = "Container 2";
    ghContainer2 = gwinContainerCreate(0, &wi, GWIN_CONTAINER_BORDER);

    // Container 3
    wi.g.width = 100;
    wi.g.height = 150;
    wi.g.y = 55;
    wi.g.x = 185;
    wi.g.parent = ghContainer1;
    wi.text = "Container 3";
    ghContainer3 = gwinContainerCreate(0, &wi, GWIN_CONTAINER_BORDER);

    // Button 1    
    wi.g.width = 80;
    wi.g.height = 20;
    wi.g.y = 10;
    wi.g.x = 10;
    wi.text = "Button 1";
    wi.g.parent = ghContainer2;
    ghButton1 = gwinButtonCreate(0, &wi);

    // Button 2    
    wi.g.width = 80;
    wi.g.height = 20;
    wi.g.y = 40;
    wi.g.x = 10;
    wi.text = "Button 2";
    wi.g.parent = ghContainer2;
    ghButton2 = gwinButtonCreate(0, &wi);

    // Button 3    
    wi.g.width = 80;
    wi.g.height = 20;
    wi.g.y = 10;
    wi.g.x = 10;
    wi.text = "Button 3";
    wi.g.parent = ghContainer3;
    ghButton3 = gwinButtonCreate(0, &wi);

    // Button 4    
    wi.g.width = 80;
    wi.g.height = 20;
    wi.g.y = 40;
    wi.g.x = 10;
    wi.text = "Button 4";
    wi.g.parent = ghContainer3;
    ghButton4 = gwinButtonCreate(0, &wi);

    // Checkbox 1
    wi.g.width = 80;
    wi.g.height = 20;
    wi.g.y = 25;
    wi.g.x = 10;
    wi.text = " Visible C2";
    wi.g.parent = ghContainer1;
    ghCheckbox1 = gwinCheckboxCreate(0, &wi);

    // Checkbox 2
    wi.g.width = 80;
    wi.g.height = 20;
    wi.g.y = 25;
    wi.g.x = 185;
    wi.text = " Visible C3";
    wi.g.parent = ghContainer1;
    ghCheckbox2 = gwinCheckboxCreate(0, &wi);

    // Checkbox 3
    wi.g.width = 80;
    wi.g.height = 20;
    wi.g.y = 10;
    wi.g.x = 10;
    wi.text = " Visible C1";
    wi.g.parent = 0;
    ghCheckbox3 = gwinCheckboxCreate(0, &wi);


    // Make the container become visible - therefore all its children
    // become visible as well
    gwinShow(ghContainer1);
}

int main(void) {
    GEvent* pe;

    // Initialize the display
    gfxInit();

    // Attach the mouse input
    gwinAttachMouse(0);

    // Set the widget defaults
    gwinSetDefaultFont(gdispOpenFont("*"));
    gwinSetDefaultStyle(&WhiteWidgetStyle, FALSE);
    gdispClear(White);

    // Create the widget
    createWidgets();

    // We want to listen for widget events
    geventListenerInit(&gl);
    gwinAttachListener(&gl);

    // Set the initial state of the checkboxes
    gwinCheckboxCheck(ghCheckbox1, TRUE);
    gwinCheckboxCheck(ghCheckbox2, TRUE);
    gwinCheckboxCheck(ghCheckbox3, TRUE);

    while(1) {
        // Get an Event
        pe = geventEventWait(&gl, TIME_INFINITE);

        switch(pe->type) {
            case GEVENT_GWIN_CHECKBOX:
                if (((GEventGWinCheckbox*)pe)->checkbox == ghCheckbox1) {
                    gwinSetVisible(ghContainer2, gwinCheckboxIsChecked(ghCheckbox1));
                }
                else if (((GEventGWinCheckbox*)pe)->checkbox == ghCheckbox2) {
                    gwinSetVisible(ghContainer3, gwinCheckboxIsChecked(ghCheckbox2));
                }
                else if (((GEventGWinCheckbox*)pe)->checkbox == ghCheckbox3) {
                    gwinSetVisible(ghContainer1, gwinCheckboxIsChecked(ghCheckbox3));
                }
                break;
        }
    }

    return 0;
}
2_t saddr; saddr = (addr & INTCTLM_MAXADDR) >> 2; switch (saddr) { case 2: // clear (enable) // Force clear unused bits val &= ~0x4fb2007f; s->intregm_disabled &= ~val; DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); slavio_check_interrupts(s); break; case 3: // set (disable, clear pending) // Force clear unused bits val &= ~0x4fb2007f; s->intregm_disabled |= val; s->intregm_pending &= ~val; DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); break; case 4: s->target_cpu = val & (MAX_CPUS - 1); DPRINTF("Set master irq cpu %d\n", s->target_cpu); break; default: break; } } static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = { slavio_intctlm_mem_readl, slavio_intctlm_mem_readl, slavio_intctlm_mem_readl, }; static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = { slavio_intctlm_mem_writel, slavio_intctlm_mem_writel, slavio_intctlm_mem_writel, }; void slavio_pic_info(void *opaque) { SLAVIO_INTCTLState *s = opaque; int i; for (i = 0; i < MAX_CPUS; i++) { term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]); } term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled); } void slavio_irq_info(void *opaque) { #ifndef DEBUG_IRQ_COUNT term_printf("irq statistic code not compiled.\n"); #else SLAVIO_INTCTLState *s = opaque; int i; int64_t count; term_printf("IRQ statistics:\n"); for (i = 0; i < 32; i++) { count = s->irq_count[i]; if (count > 0) term_printf("%2d: %" PRId64 "\n", i, count); } #endif } static const uint32_t intbit_to_level[32] = { 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, }; static void slavio_check_interrupts(void *opaque) { CPUState *env; SLAVIO_INTCTLState *s = opaque; uint32_t pending = s->intregm_pending; unsigned int i, j, max = 0; pending &= ~s->intregm_disabled; if (pending && !(s->intregm_disabled & 0x80000000)) { for (i = 0; i < 32; i++) { if (pending & (1 << i)) { if (max < intbit_to_level[i]) max = intbit_to_level[i]; } } env = s->cpu_envs[s->target_cpu]; if (!env) { DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending); } else { if (env->halted) env->halted = 0; if (env->interrupt_index == 0) { DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max); #ifdef DEBUG_IRQ_COUNT s->irq_count[max]++; #endif env->interrupt_index = TT_EXTINT | max; cpu_interrupt(env, CPU_INTERRUPT_HARD); } else DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index); } } else DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled); for (i = 0; i < MAX_CPUS; i++) { max = 0; env = s->cpu_envs[i]; if (!env) continue; for (j = 17; j < 32; j++) { if (s->intreg_pending[i] & (1 << j)) { if (max < j - 16) max = j - 16; } } if (max > 0) { if (env->halted) env->halted = 0; if (env->interrupt_index == 0) { DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending); #ifdef DEBUG_IRQ_COUNT s->irq_count[max]++; #endif env->interrupt_index = TT_EXTINT | max; cpu_interrupt(env, CPU_INTERRUPT_HARD); } } } } /* * "irq" here is the bit number in the system interrupt register to * separate serial and keyboard interrupts sharing a level. */ void slavio_pic_set_irq(void *opaque, int irq, int level) { SLAVIO_INTCTLState *s = opaque; DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level); if (irq < 32) { uint32_t mask = 1 << irq; uint32_t pil = intbit_to_level[irq]; if (pil > 0) { if (level) { s->intregm_pending |= mask; s->intreg_pending[s->target_cpu] |= 1 << pil; } else { s->intregm_pending &= ~mask; s->intreg_pending[s->target_cpu] &= ~(1 << pil); } } } slavio_check_interrupts(s); } void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu) { SLAVIO_INTCTLState *s = opaque; DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level); if (cpu == (unsigned int)-1) { slavio_pic_set_irq(opaque, irq, level); return; } if (irq < 32) { uint32_t pil = intbit_to_level[irq]; if (pil > 0) { if (level) { s->intreg_pending[cpu] |= 1 << pil; } else { s->intreg_pending[cpu] &= ~(1 << pil); } } } slavio_check_interrupts(s); } static void slavio_intctl_save(QEMUFile *f, void *opaque) { SLAVIO_INTCTLState *s = opaque; int i; for (i = 0; i < MAX_CPUS; i++) { qemu_put_be32s(f, &s->intreg_pending[i]); } qemu_put_be32s(f, &s->intregm_pending); qemu_put_be32s(f, &s->intregm_disabled); qemu_put_be32s(f, &s->target_cpu); } static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id) { SLAVIO_INTCTLState *s = opaque; int i; if (version_id != 1) return -EINVAL; for (i = 0; i < MAX_CPUS; i++) { qemu_get_be32s(f, &s->intreg_pending[i]); } qemu_get_be32s(f, &s->intregm_pending); qemu_get_be32s(f, &s->intregm_disabled); qemu_get_be32s(f, &s->target_cpu); return 0; } static void slavio_intctl_reset(void *opaque) { SLAVIO_INTCTLState *s = opaque; int i; for (i = 0; i < MAX_CPUS; i++) { s->intreg_pending[i] = 0; } s->intregm_disabled = ~0xffb2007f; s->intregm_pending = 0; s->target_cpu = 0; } void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env) { SLAVIO_INTCTLState *s = opaque; s->cpu_envs[cpu] = env; } void *slavio_intctl_init(uint32_t addr, uint32_t addrg) { int slavio_intctl_io_memory, slavio_intctlm_io_memory, i; SLAVIO_INTCTLState *s; s = qemu_mallocz(sizeof(SLAVIO_INTCTLState)); if (!s) return NULL; for (i = 0; i < MAX_CPUS; i++) { slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s); cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory); } slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s); cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory); register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s); qemu_register_reset(slavio_intctl_reset, s); slavio_intctl_reset(s); return s; }