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| author | inmarket <andrewh@inmarket.com.au> | 2015-10-06 12:10:11 +1000 |
|---|---|---|
| committer | inmarket <andrewh@inmarket.com.au> | 2015-10-06 12:10:11 +1000 |
| commit | 80299276b7134693a6f02fb8fa791d0a15ed1eab (patch) | |
| tree | e1824bd6b9aa27a71372f67c6a0f96b9f625abd7 | |
| parent | 754d2e072b51bc43c72a37d46e22337d594f18dc (diff) | |
| parent | a35ee53d0a28cb0b6b61944a1ed698a0cef85839 (diff) | |
| download | uGFX-80299276b7134693a6f02fb8fa791d0a15ed1eab.tar.gz uGFX-80299276b7134693a6f02fb8fa791d0a15ed1eab.tar.bz2 uGFX-80299276b7134693a6f02fb8fa791d0a15ed1eab.zip | |
Merge branch 'master' into TextEdit
38 files changed, 3920 insertions, 3033 deletions
diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk index 9386fae0..71d820ca 100644 --- a/boards/base/STM32F746-Discovery/board.mk +++ b/boards/base/STM32F746-Discovery/board.mk @@ -1,30 +1,25 @@ -GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery +GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery \ + $(STMHAL)/Inc GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \ - $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c -GFXDEFS += STM32F746xx - + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7_i2c.c + ifeq ($(OPT_OS),raw32) - GFXSRC += $(HAL)/Src/stm32f7xx_hal.c \ - $(HAL)/Src/stm32f7xx_hal_cortex.c \ - $(HAL)/Src/stm32f7xx_hal_flash.c \ - $(HAL)/Src/stm32f7xx_hal_flash_ex.c \ - $(HAL)/Src/stm32f7xx_hal_rcc.c \ - $(HAL)/Src/stm32f7xx_hal_rcc_ex.h \ - $(HAL)/Src/stm32f7xx_hal_gpio.c \ - $(HAL)/Src/stm32f7xx_hal_pwr.c \ - $(HAL)/Src/stm32f7xx_hal_pwr_ex.c \ - $(HAL)/Src/stm32f7xx_hal_sdram.c \ - $(HAL)/Src/stm32f7xx_hal_dma.c + GFXDEFS += STM32F746xx + GFXSRC += $(STMHAL)/Src/stm32f7xx_hal.c \ + $(STMHAL)/Src/stm32f7xx_hal_cortex.c \ + $(STMHAL)/Src/stm32f7xx_hal_rcc.c \ + $(STMHAL)/Src/stm32f7xx_hal_rcc_ex.h \ + $(STMHAL)/Src/stm32f7xx_hal_gpio.c \ + $(STMHAL)/Src/stm32f7xx_hal_pwr.c \ + $(STMHAL)/Src/stm32f7xx_hal_pwr_ex.c GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s \ $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c \ $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c \ - $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c \ - $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7_i2c.c + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c GFXDEFS += GFX_OS_EXTRA_INIT_FUNCTION=Raw32OSInit GFX_OS_INIT_NO_WARNING=TRUE - SRCFLAGS+= -std=c99 GFXINC += $(CMSIS)/Device/ST/STM32F7xx/Include \ $(CMSIS)/Include \ - $(HAL)/Inc + $(STMHAL)/Inc LDSCRIPT = $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld endif diff --git a/boards/base/STM32F746-Discovery/board_STM32LTDC.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h index ffe28e02..f5011d4c 100644 --- a/boards/base/STM32F746-Discovery/board_STM32LTDC.h +++ b/boards/base/STM32F746-Discovery/board_STM32LTDC.h @@ -8,10 +8,16 @@ #ifndef _GDISP_LLD_BOARD_H #define _GDISP_LLD_BOARD_H -#include "stm32f7xx_ll_fmc.h" #include "stm32f746g_discovery_sdram.h" +#include "stm32f7xx_hal_rcc.h" +#include "stm32f7xx_hal_gpio.h" #include <string.h> +#if !GFX_USE_OS_CHIBIOS + #define AFRL AFR[0] + #define AFRH AFR[1] +#endif + static const ltdcConfig driverCfg = { 480, 272, // Width, Height (pixels) 41, 10, // Horizontal, Vertical sync (pixels) @@ -55,181 +61,181 @@ static void configureLcdPins(void) GPIOI->MODER |= GPIO_MODER_MODER15_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_15; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1; - GPIOI->AFR[1] |= (0b1110 << 4*7); + GPIOI->AFRH |= (0b1110 << 4*7); // PJ0: LCD_R1 GPIOJ->MODER |= GPIO_MODER_MODER0_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_0; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1; - GPIOJ->AFR[0] |= (0b1110 << 4*0); + GPIOJ->AFRL |= (0b1110 << 4*0); // PJ1: LCD_R2 GPIOJ->MODER |= GPIO_MODER_MODER1_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_1; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1; - GPIOJ->AFR[0] |= (0b1110 << 4*1); + GPIOJ->AFRL |= (0b1110 << 4*1); // PJ2: LCD_R3 GPIOJ->MODER |= GPIO_MODER_MODER2_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_2; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1; - GPIOJ->AFR[0] |= (0b1110 << 4*2); + GPIOJ->AFRL |= (0b1110 << 4*2); // PJ3: LCD_R4 GPIOJ->MODER |= GPIO_MODER_MODER3_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_3; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR3_0 | GPIO_OSPEEDER_OSPEEDR3_1; - GPIOJ->AFR[0] |= (0b1110 << 4*3); + GPIOJ->AFRL |= (0b1110 << 4*3); // PJ4: LCD_R5 GPIOJ->MODER |= GPIO_MODER_MODER4_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_4; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1; - GPIOJ->AFR[0] |= (0b1110 << 4*4); + GPIOJ->AFRL |= (0b1110 << 4*4); // PJ5: LCD_R6 GPIOJ->MODER |= GPIO_MODER_MODER5_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_5; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1; - GPIOJ->AFR[0] |= (0b1110 << 4*5); + GPIOJ->AFRL |= (0b1110 << 4*5); // PJ6: LCD_R7 GPIOJ->MODER |= GPIO_MODER_MODER6_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_6; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1; - GPIOJ->AFR[0] |= (0b1110 << 4*6); + GPIOJ->AFRL |= (0b1110 << 4*6); // PJ7: LCD_G0 GPIOJ->MODER |= GPIO_MODER_MODER7_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_7; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1; - GPIOJ->AFR[0] |= (0b1110 << 4*7); + GPIOJ->AFRL |= (0b1110 << 4*7); // PJ8: LCD_G1 GPIOJ->MODER |= GPIO_MODER_MODER8_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_8; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR8_1; - GPIOJ->AFR[1] |= (0b1110 << 4*0); + GPIOJ->AFRH |= (0b1110 << 4*0); // PJ9: LCD_G2 GPIOJ->MODER |= GPIO_MODER_MODER9_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_9; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1; - GPIOJ->AFR[1] |= (0b1110 << 4*1); + GPIOJ->AFRH |= (0b1110 << 4*1); // PJ10: LCD_G3 GPIOJ->MODER |= GPIO_MODER_MODER10_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_10; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1; - GPIOJ->AFR[1] |= (0b1110 << 4*2); + GPIOJ->AFRH |= (0b1110 << 4*2); // PJ11: LCD_G4 GPIOJ->MODER |= GPIO_MODER_MODER11_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_11; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR11_0 | GPIO_OSPEEDER_OSPEEDR11_1; - GPIOJ->AFR[1] |= (0b1110 << 4*3); + GPIOJ->AFRH |= (0b1110 << 4*3); // PK0: LCD_G5 GPIOK->MODER |= GPIO_MODER_MODER0_0; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_0; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1; - GPIOK->AFR[0] |= (0b1110 << 4*0); + GPIOK->AFRL |= (0b1110 << 4*0); // PK1: LCD_G6 GPIOK->MODER |= GPIO_MODER_MODER1_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_1; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1; - GPIOK->AFR[0] |= (0b1110 << 4*1); + GPIOK->AFRL |= (0b1110 << 4*1); // PK2: LCD_G7 GPIOK->MODER |= GPIO_MODER_MODER2_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_2; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1; - GPIOK->AFR[0] |= (0b1110 << 4*2); + GPIOK->AFRL |= (0b1110 << 4*2); // PE4: LCD_B0 GPIOE->MODER |= GPIO_MODER_MODER4_1; GPIOE->OTYPER &=~ GPIO_OTYPER_OT_4; GPIOE->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1; - GPIOE->AFR[0] |= (0b1110 << 4*4); + GPIOE->AFRL |= (0b1110 << 4*4); // PJ13: LCD_B1 GPIOJ->MODER |= GPIO_MODER_MODER13_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_13; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1; - GPIOJ->AFR[1] |= (0b1110 << 4*5); + GPIOJ->AFRH |= (0b1110 << 4*5); // PJ14: LCD_B2 GPIOJ->MODER |= GPIO_MODER_MODER14_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_14; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1; - GPIOJ->AFR[1] |= (0b1110 << 4*6); + GPIOJ->AFRH |= (0b1110 << 4*6); // PJ15: LCD_B3 GPIOJ->MODER |= GPIO_MODER_MODER15_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_15; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1; - GPIOJ->AFR[1] |= (0b1110 << 4*7); + GPIOJ->AFRH |= (0b1110 << 4*7); // PG12: LCD_B4 GPIOG->MODER |= GPIO_MODER_MODER12_1; GPIOG->OTYPER &=~ GPIO_OTYPER_OT_12; GPIOG->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR12_1; - GPIOG->AFR[1] |= (0b1110 << 4*4); + GPIOG->AFRH |= (0b1110 << 4*4); // PK4: LCD_B5 GPIOK->MODER |= GPIO_MODER_MODER4_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_4; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1; - GPIOK->AFR[0] |= (0b1110 << 4*4); + GPIOK->AFRL |= (0b1110 << 4*4); // PK5: LCD_B6 GPIOK->MODER |= GPIO_MODER_MODER5_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_5; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1; - GPIOK->AFR[0] |= (0b1110 << 4*5); + GPIOK->AFRL |= (0b1110 << 4*5); // PK6: LCD_B7 GPIOK->MODER |= GPIO_MODER_MODER6_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_6; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1; - GPIOK->AFR[0] |= (0b1110 << 4*6); + GPIOK->AFRL |= (0b1110 << 4*6); // PK7: LCD_DE GPIOK->MODER |= GPIO_MODER_MODER7_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_7; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1; - GPIOK->AFR[0] |= (0b1110 << 4*7); + GPIOK->AFRL |= (0b1110 << 4*7); // PI9: LCD_VSYNC GPIOI->MODER |= GPIO_MODER_MODER9_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_9; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1; - GPIOI->AFR[1] |= (0b1110 << 4*1); + GPIOI->AFRH |= (0b1110 << 4*1); // PI10: LCD_VSYNC GPIOI->MODER |= GPIO_MODER_MODER10_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_10; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1; - GPIOI->AFR[1] |= (0b1110 << 4*2); + GPIOI->AFRH |= (0b1110 << 4*2); // PI13: LCD_INT GPIOI->MODER |= GPIO_MODER_MODER13_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_13; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1; - GPIOI->AFR[1] |= (0b1110 << 4*5); + GPIOI->AFRH |= (0b1110 << 4*5); // PI14: LCD_CLK GPIOI->MODER |= GPIO_MODER_MODER14_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_14; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1; - GPIOI->AFR[1] |= (0b1110 << 4*6); + GPIOI->AFRH |= (0b1110 << 4*6); // PI8: ??? GPIOI->MODER |= GPIO_MODER_MODER8_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_8; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR8_1; - GPIOI->AFR[1] |= (0b1110 << 4*0); + GPIOI->AFRH |= (0b1110 << 4*0); // PI12: LCD_DISP_PIN GPIOI->MODER |= GPIO_MODER_MODER12_0; @@ -270,7 +276,9 @@ static inline void init_board(GDisplay *g) { // PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz // LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz #define STM32_PLLSAIN_VALUE 192 + #undef STM32_PLLSAIQ_VALUE #define STM32_PLLSAIQ_VALUE 7 + #undef STM32_PLLSAIR_VALUE #define STM32_PLLSAIR_VALUE RK043FN48H_FREQUENCY_DIVIDER #define STM32_PLLSAIR_POST STM32_SAIR_DIV4 RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24); diff --git a/boards/base/STM32F746-Discovery/example_chibios3/Makefile b/boards/base/STM32F746-Discovery/example_chibios3/Makefile new file mode 100644 index 00000000..8e6c70a5 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/Makefile @@ -0,0 +1,73 @@ +# Possible Targets: all clean Debug cleanDebug Release cleanRelease + +############################################################################################## +# Settings +# + +# General settings + # See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables + OPT_OS = chibios + OPT_THUMB = yes + OPT_LINK_OPTIMIZE = no + OPT_CPU = stm32m7 + +# uGFX settings + # See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables + GFXLIB = ../ugfx + GFXBOARD = STM32F746-Discovery + GFXDEMO = applications/combo + #GFXDRIVERS = + GFXSINGLEMAKE = no + +# ChibiOS settings +ifeq ($(OPT_OS),chibios) + # See $(GFXLIB)/tools/gmake_scripts/os_chibios_3.mk for the list of variables + CHIBIOS = ../ChibiOS-Master + CHIBIOS_VERSION = 3 + CHIBIOS_CPUCLASS = ARMCMx + CHIBIOS_PLATFORM = STM32 + CHIBIOS_DEVICE_FAMILY = STM32F7xx + CHIBIOS_STARTUP = startup_stm32f7xx + CHIBIOS_PORT = v7m + CHIBIOS_LDSCRIPT = STM32F746xG.ld + CHIBIOS_BOARD = ST_STM32F746G_DISCOVERY + #CHIBIOS_PROCESS_STACKSIZE = 0x400 + #CHIBIOS_EXCEPTIONS_STACKSIZE = 0x400 +endif + +#Special - Required for the drivers for this discovery board. +STMHAL = ../STM32/STM32F7xx_HAL_Driver + +#Special - Required for Raw32 +CMSIS = ../STM32/CMSIS + +############################################################################################## +# Set these for your project +# + +ARCH = arm-none-eabi- +SRCFLAGS = -ggdb -O1 +CFLAGS = +CXXFLAGS = -fno-rtti +ASFLAGS = +LDFLAGS = + +SRC = + +OBJS = +#DEFS = GFX_OS_HEAP_SIZE=40960 +DEFS = +LIBS = +INCPATH = + +LIBPATH = +LDSCRIPT = + +############################################################################################## +# These should be at the end +# + +include $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk +include $(GFXLIB)/tools/gmake_scripts/os_$(OPT_OS).mk +include $(GFXLIB)/tools/gmake_scripts/compiler_gcc.mk +# *** EOF *** diff --git a/boards/base/STM32F746-Discovery/example_chibios3/chconf.h b/boards/base/STM32F746-Discovery/example_chibios3/chconf.h new file mode 100644 index 00000000..c19b8b90 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/chconf.h @@ -0,0 +1,501 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_TRACE FALSE + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_VTOR_INIT 0x00200000U + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/boards/base/STM32F746-Discovery/example_chibios3/halconf.h b/boards/base/STM32F746-Discovery/example_chibios3/halconf.h new file mode 100644 index 00000000..27dd1ac9 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/halconf.h @@ -0,0 +1,334 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/boards/base/STM32F746-Discovery/example_chibios3/mcuconf.h b/boards/base/STM32F746-Discovery/example_chibios3/mcuconf.h new file mode 100644 index 00000000..068c1764 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/mcuconf.h @@ -0,0 +1,381 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 7 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +#endif /* _MCUCONF_H_ */ diff --git a/boards/base/STM32F746-Discovery/example_chibios3/openocd.cfg b/boards/base/STM32F746-Discovery/example_chibios3/openocd.cfg new file mode 100644 index 00000000..e2d732a4 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/openocd.cfg @@ -0,0 +1,94 @@ +# This is a script file for OpenOCD ?.?.? +# +# It is set up for the STM32F749-Discovery board using the ST-Link JTAG adaptor. +# +# Assuming the current directory is your project directory containing this openocd.cfg file... +# +# To program your device: +# +# openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown +# +# To debug your device: +# +# openocd +# (This will run openocd in gdb server debug mode. Leave it running in the background) +# +# gdb yourfile.elf +# (To start gdb. Then run the following commands in gdb...) +# +# target remote 127.0.0.1:3333 +# monitor Debug +# stepi +# (This last stepi resynchronizes gdb). +# +# If you want to reprogram from within gdb: +# +# monitor Burn yourfile.bin +# + +echo "" +echo "##### Loading debugger..." +source [find interface/stlink-v2-1.cfg] + +echo "" +echo "##### Loading CPU..." +source [find target/stm32f7x.cfg] + +echo "" +echo "##### Configuring..." +#reset_config srst_only srst_nogate +#cortex_m maskisr (auto|on|off) +#cortex_m vector_catch [all|none|list] +#cortex_m reset_config (srst|sysresetreq|vectreset) +#gdb_breakpoint_override hard + +proc Debug { } { + echo "" + echo "##### Debug Session Connected..." + reset init + echo "Ready..." +} + +proc Burn {file} { + echo "" + echo "##### Burning $file to device..." + halt + # Due to an issue with the combination of the ST-Link adapters and OpenOCD + # applying the stm32f2x unlock 0 command actaully applies read protection - VERY BAD! + # If this happens to you - use the ST-Link utility to set the option byte back to normal. + # If you are using a different debugger eg a FT2232 based adapter you can uncomment the line below. + #stm32f2x unlock 0 + #flash protect 0 0 last off + reset halt + flash write_image erase $file 0 elf + verify_image $file 0x0 elf + #flash protect 0 0 last on + reset + echo "Burning Complete!" +} + +echo "" +echo "##### Leaving Configuration Mode..." +init +reset init +flash probe 0 +flash banks +#flash info 0 + +echo "" +echo "##### Waiting for debug connections..." + +##### OLD ###### +#source [find interface/stlink-v2-1.cfg] +#source [find target/stm32f7x.cfg] +# +#proc flash_chip {} { +# halt +# reset halt +# flash write_image erase main.elf 0 elf +# verify_image main.elf 0 elf +# reset +# shutdown +#} +# +#init diff --git a/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h b/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..40ebe103 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h @@ -0,0 +1,418 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf.h + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +//#define HAL_SDRAM_MODULE_ENABLED +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/example_raw32/Makefile b/boards/base/STM32F746-Discovery/example_raw32/Makefile index dee0f01a..05106186 100644 --- a/boards/base/STM32F746-Discovery/example_raw32/Makefile +++ b/boards/base/STM32F746-Discovery/example_raw32/Makefile @@ -15,38 +15,38 @@ # See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables GFXLIB = ../ugfx GFXBOARD = STM32F746-Discovery - GFXDEMO = modules/gdisp/basics + GFXDEMO = applications/combo #GFXDRIVERS = + GFXSINGLEMAKE = no # ChibiOS settings -# Note: not supported by ChibiOS yet! ifeq ($(OPT_OS),chibios) - # See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables - CHIBIOS = ../ChibiOS - CHIBIOS_BOARD = ST_STM32F746_DISCOVERY - CHIBIOS_PLATFORM = STM32F7xx - CHIBIOS_PORT = GCC/ARMCMx/STM32F7xx - CHIBIOS_LDSCRIPT = STM32F746.ld - - #CHIBIOS = ../ChibiOS3 - #CHIBIOS_VERSION = 3 - #CHIBIOS_BOARD = ST_STM32F746_DISCOVERY - #CHIBIOS_CPUCLASS = ARMCMx - #CHIBIOS_PLATFORM = STM32/STM32F7xx - #CHIBIOS_PORT = stm32f7xx - #CHIBIOS_LDSCRIPT = STM32F746.ld + # See $(GFXLIB)/tools/gmake_scripts/os_chibios_3.mk for the list of variables + CHIBIOS = ../ChibiOS-Master + CHIBIOS_VERSION = 3 + CHIBIOS_CPUCLASS = ARMCMx + CHIBIOS_PLATFORM = STM32 + CHIBIOS_DEVICE_FAMILY = STM32F7xx + CHIBIOS_STARTUP = startup_stm32f7xx + CHIBIOS_PORT = v7m + CHIBIOS_LDSCRIPT = STM32F746xG.ld + CHIBIOS_BOARD = ST_STM32F746G_DISCOVERY + #CHIBIOS_PROCESS_STACKSIZE = 0x400 + #CHIBIOS_EXCEPTIONS_STACKSIZE = 0x400 endif -# Raw32 settings +#Special - Required for the drivers for this discovery board. +STMHAL = ../STM32/STM32F7xx_HAL_Driver + +#Special - Required for Raw32 CMSIS = ../STM32/CMSIS -HAL = ../STM32/STM32F7xx_HAL_Driver ############################################################################################## # Set these for your project # ARCH = arm-none-eabi- -SRCFLAGS = -ggdb -O0 +SRCFLAGS = -ggdb -O1 CFLAGS = CXXFLAGS = -fno-rtti ASFLAGS = @@ -55,7 +55,8 @@ LDFLAGS = SRC = OBJS = -DEFS = GFX_OS_HEAP_SIZE=40960 +DEFS = GFX_OS_HEAP_SIZE=40960 +#DEFS = LIBS = INCPATH = diff --git a/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h index 765e1377..40ebe103 100644 --- a/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h +++ b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h @@ -65,7 +65,7 @@ /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ -#define HAL_SDRAM_MODULE_ENABLED +//#define HAL_SDRAM_MODULE_ENABLED /* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED /* #define HAL_I2C_MODULE_ENABLED */ diff --git a/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h b/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h index 8031eca5..1e3e6877 100644 --- a/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h +++ b/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h @@ -25,6 +25,11 @@ // The FT5336 I2C slave address (including the R/W bit) #define FT5336_SLAVE_ADDR 0x70 +#if !GFX_USE_OS_CHIBIOS + #define AFRL AFR[0] + #define AFRH AFR[1] +#endif + static bool_t init_board(GMouse* m, unsigned instance) { (void)m; @@ -35,14 +40,14 @@ static bool_t init_board(GMouse* m, unsigned instance) GPIOH->MODER |= GPIO_MODER_MODER7_1; // Alternate function GPIOH->OTYPER |= GPIO_OTYPER_OT_7; // OpenDrain GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR7; // LowSpeed - GPIOH->AFR[0] |= (0b0100 << 4*7); // AF4 + GPIOH->AFRL |= (0b0100 << 4*7); // AF4 // I2C3_SDA GPIOH8, alternate, opendrain, highspeed RCC->AHB1ENR |= RCC_AHB1ENR_GPIOHEN; // Enable clock GPIOH->MODER |= GPIO_MODER_MODER8_1; // Alternate function GPIOH->OTYPER |= GPIO_OTYPER_OT_8; // OpenDrain GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR8; // LowSpeed - GPIOH->AFR[1] |= (0b0100 << 4*0); // AF4 + GPIOH->AFRH |= (0b0100 << 4*0); // AF4 // Initialize the I2C3 peripheral if (!(i2cInit(I2C3))) { diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c index bf22b342..66475b8f 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c @@ -1,147 +1,192 @@ -/** - ****************************************************************************** - * @file stm32746g_discovery_sdram.c - * @author MCD Application Team - * @version V1.0.0 - * @date 25-June-2015 - * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory - * device mounted on STM32746G-Discovery board. - @verbatim - 1. How To use this driver: - -------------------------- - - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted - on STM32746G-Discovery board. - - This driver does not need a specific component driver for the SDRAM device - to be included with. - - 2. Driver description: - --------------------- - + Initialization steps: - o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This - function includes the MSP layer hardware resources initialization and the - FMC controller configuration to interface with the external SDRAM memory. - o It contains the SDRAM initialization sequence to program the SDRAM external - device using the function BSP_SDRAM_Initialization_sequence(). Note that this - sequence is standard for all SDRAM devices, but can include some differences - from a device to another. If it is the case, the right sequence should be - implemented separately. - - + SDRAM read/write operations - o SDRAM external memory can be accessed with read/write operations once it is - initialized. - Read/write operation can be performed with AHB access using the functions - BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions - BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA(). - o The AHB access is performed with 32-bit width transaction, the DMA transfer - configuration is fixed at single (no burst) word transfer (see the - SDRAM_MspInit() static function). - o User can implement his own functions for read/write access with his desired - configurations. - o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler() - is called in IRQ handler file, to serve the generated interrupt once the DMA - transfer is complete. - o You can send a command to the SDRAM device in runtime using the function - BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between - the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. - - @endverbatim - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ #include "gfx.h" #include "stm32f746g_discovery_sdram.h" #include "stm32f7xx_hal_rcc.h" -#include "stm32f7xx_hal_rcc_ex.h" +#include "stm32f7xx_hal_dma.h" +#include "stm32f7xx_hal_gpio.h" +#include "stm32f7xx_hal_sdram.h" + +#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 +#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 +#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ +#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) + +/* DMA definitions for SDRAM DMA transfer */ +#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0 +#define SDRAM_DMAx_STREAM DMA2_Stream0 +#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn + +/* FMC SDRAM Mode definition register defines */ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshCount); +static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); +static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); +static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); +static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); + +static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) +{ + /* Check the SDRAM handle parameter */ + if(hsdram == NULL) + return; -/** @addtogroup BSP - * @{ - */ + if(hsdram->State == HAL_SDRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; + } -/** @addtogroup STM32746G_DISCOVERY - * @{ - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM - * @{ - */ + /* Initialize the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions - * @{ - */ -/** - * @} - */ + /* Initialize SDRAM control Interface */ + _FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines - * @{ - */ -/** - * @} - */ + /* Initialize SDRAM timing Interface */ + _FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros - * @{ - */ -/** - * @} - */ + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; +} -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables - * @{ - */ -static SDRAM_HandleTypeDef sdramHandle; -static FMC_SDRAM_TimingTypeDef Timing; -static FMC_SDRAM_CommandTypeDef Command; -/** - * @} - */ +static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +{ + uint32_t tmpr1 = 0; + uint32_t tmpr2 = 0; -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions - * @{ - */ + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank != FMC_SDRAM_BANK2) + { + tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ + Init->RowBitsNumber |\ + Init->MemoryDataWidth |\ + Init->InternalBankNumber |\ + Init->CASLatency |\ + Init->WriteProtection |\ + Init->SDClockPeriod |\ + Init->ReadBurst |\ + Init->ReadPipeDelay + ); + Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + } + else /* FMC_Bank2_SDRAM */ + { + tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ + Init->ReadBurst |\ + Init->ReadPipeDelay); + + tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ + Init->RowBitsNumber |\ + Init->MemoryDataWidth |\ + Init->InternalBankNumber |\ + Init->CASLatency |\ + Init->WriteProtection); + + Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; + } + + return HAL_OK; +} + +static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr1 = 0; + uint32_t tmpr2 = 0; + + /* Set SDRAM device timing parameters */ + if (Bank != FMC_SDRAM_BANK2) + { + tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + + tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + (((Timing->SelfRefreshTime)-1) << 8) |\ + (((Timing->RowCycleDelay)-1) << 12) |\ + (((Timing->WriteRecoveryTime)-1) <<16) |\ + (((Timing->RPDelay)-1) << 20) |\ + (((Timing->RCDDelay)-1) << 24)); + Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; + } + else /* FMC_Bank2_SDRAM */ + { + tmpr1 = Device->SDTR[FMC_SDRAM_BANK2]; + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + + tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + (((Timing->SelfRefreshTime)-1) << 8) |\ + (((Timing->WriteRecoveryTime)-1) <<16) |\ + (((Timing->RCDDelay)-1) << 24)); + + tmpr2 = Device->SDTR[FMC_SDRAM_BANK1]; + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ + (((Timing->RPDelay)-1) << 20)); + + Device->SDTR[FMC_SDRAM_BANK2] = tmpr1; + Device->SDTR[FMC_SDRAM_BANK1] = tmpr2; + } + + return HAL_OK; +} /** * @brief Initializes the SDRAM device. * @retval SDRAM status */ -uint8_t BSP_SDRAM_Init(void) +void BSP_SDRAM_Init(void) { - static uint8_t sdramstatus = SDRAM_ERROR; + SDRAM_HandleTypeDef sdramHandle; + FMC_SDRAM_TimingTypeDef Timing; + /* SDRAM device configuration */ sdramHandle.Instance = FMC_SDRAM_DEVICE; @@ -167,46 +212,228 @@ uint8_t BSP_SDRAM_Init(void) /* SDRAM controller initialization */ - BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ + BSP_SDRAM_MspInit(&sdramHandle); + + _HAL_SDRAM_Init(&sdramHandle, &Timing); + + /* SDRAM initialization sequence */ + BSP_SDRAM_Initialization_sequence(&sdramHandle, REFRESH_COUNT); +} + +static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Send SDRAM command */ + _FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); - if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) + /* Update the SDRAM controller state state */ + if(Command->CommandMode == FMC_SDRAM_CMD_PALL) { - sdramstatus = SDRAM_ERROR; + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; } else { - sdramstatus = SDRAM_OK; + hsdram->State = HAL_SDRAM_STATE_READY; } - - /* SDRAM initialization sequence */ - BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); - - return sdramstatus; + + return HAL_OK; +} + +static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + __IO uint32_t tmpr = 0; + systemticks_t tickstart = 0; + + /* Set command register */ + tmpr = (uint32_t)((Command->CommandMode) |\ + (Command->CommandTarget) |\ + (((Command->AutoRefreshNumber)-1) << 5) |\ + ((Command->ModeRegisterDefinition) << 9) + ); + + Device->SDCMR = tmpr; + + /* Get tick */ + tickstart = gfxSystemTicks(); + + /* wait until command is send */ + while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((gfxSystemTicks() - tickstart ) > Timeout)) + { + return HAL_TIMEOUT; + } + } + + return HAL_ERROR; + } + + return HAL_OK; +} + +static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Program the refresh rate */ + _FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +{ + /* Set the refresh rate in command register */ + Device->SDRTR |= (RefreshRate<<1); + + return HAL_OK; +} + +static HAL_StatusTypeDef _HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + + /* the FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; } /** - * @brief DeInitializes the SDRAM device. - * @retval SDRAM status + * @brief DeInitializes the DMA peripheral + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status */ -uint8_t BSP_SDRAM_DeInit(void) -{ - static uint8_t sdramstatus = SDRAM_ERROR; - /* SDRAM device de-initialization */ - sdramHandle.Instance = FMC_SDRAM_DEVICE; - - if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) +static HAL_StatusTypeDef _HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA peripheral state */ + if(hdma == NULL) { - sdramstatus = SDRAM_ERROR; + return HAL_ERROR; } - else + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) { - sdramstatus = SDRAM_OK; + return HAL_ERROR; } - - /* SDRAM controller de-initialization */ - BSP_SDRAM_MspDeInit(&sdramHandle, NULL); - - return sdramstatus; + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0; + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0; + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0; + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0; + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0; + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = (uint32_t)0x00000021; + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; } /** @@ -214,9 +441,9 @@ uint8_t BSP_SDRAM_DeInit(void) * @param RefreshCount: SDRAM refresh counter value * @retval None */ -void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) +static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshCount) { - __IO uint32_t tmpmrd = 0; + FMC_SDRAM_CommandTypeDef Command; /* Step 1: Configure a clock configuration enable command */ Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; @@ -225,11 +452,11 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) Command.ModeRegisterDefinition = 0; /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + _HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT); /* Step 2: Insert 100 us minimum delay */ /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ - HAL_Delay(1); + gfxSleepMilliseconds(1); /* Step 3: Configure a PALL (precharge all) command */ Command.CommandMode = FMC_SDRAM_CMD_PALL; @@ -238,7 +465,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) Command.ModeRegisterDefinition = 0; /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + _HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT); /* Step 4: Configure an Auto Refresh command */ Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; @@ -247,128 +474,24 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) Command.ModeRegisterDefinition = 0; /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + _HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT); /* Step 5: Program the external memory mode register */ - tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ - SDRAM_MODEREG_CAS_LATENCY_2 |\ - SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; Command.AutoRefreshNumber = 1; - Command.ModeRegisterDefinition = tmpmrd; + Command.ModeRegisterDefinition = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ + SDRAM_MODEREG_CAS_LATENCY_2 |\ + SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;; /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + _HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT); /* Step 6: Set the refresh rate counter */ /* Set the device refresh rate */ - HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); -} - -/** - * @brief Reads an amount of data from the SDRAM memory in polling mode. - * @param uwStartAddress: Read start address - * @param pData: Pointer to data to be read - * @param uwDataSize: Size of read data from the memory - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) -{ - if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Reads an amount of data from the SDRAM memory in DMA mode. - * @param uwStartAddress: Read start address - * @param pData: Pointer to data to be read - * @param uwDataSize: Size of read data from the memory - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) -{ - if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Writes an amount of data to the SDRAM memory in polling mode. - * @param uwStartAddress: Write start address - * @param pData: Pointer to data to be written - * @param uwDataSize: Size of written data from the memory - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) -{ - if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Writes an amount of data to the SDRAM memory in DMA mode. - * @param uwStartAddress: Write start address - * @param pData: Pointer to data to be written - * @param uwDataSize: Size of written data from the memory - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) -{ - if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Sends command to the SDRAM bank. - * @param SdramCmd: Pointer to SDRAM command structure - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) -{ - if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Handles SDRAM DMA transfer interrupt request. - * @retval None - */ -void BSP_SDRAM_DMA_IRQHandler(void) -{ - HAL_DMA_IRQHandler(sdramHandle.hdma); + _HAL_SDRAM_ProgramRefreshRate(hsdram, RefreshCount); } /** @@ -377,10 +500,12 @@ void BSP_SDRAM_DMA_IRQHandler(void) * @param Params * @retval None */ -__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) +static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) { static DMA_HandleTypeDef dma_handle; +#if !GFX_USE_OS_CHIBIOS GPIO_InitTypeDef gpio_init_structure; +#endif /* Enable FMC clock */ __HAL_RCC_FMC_CLK_ENABLE(); @@ -396,7 +521,8 @@ __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); - /* Common GPIO configuration */ + /* Common GPIO configuration - some are already setup by ChibiOS Init */ +#if !GFX_USE_OS_CHIBIOS gpio_init_structure.Mode = GPIO_MODE_AF_PP; gpio_init_structure.Pull = GPIO_PULLUP; gpio_init_structure.Speed = GPIO_SPEED_FAST; @@ -431,6 +557,7 @@ __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) /* GPIOH configuration */ gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; HAL_GPIO_Init(GPIOH, &gpio_init_structure); +#endif /* Configure common DMA parameters */ dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; @@ -452,51 +579,13 @@ __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) __HAL_LINKDMA(hsdram, hdma, dma_handle); /* Deinitialize the stream for new transfer */ - HAL_DMA_DeInit(&dma_handle); + _HAL_DMA_DeInit(&dma_handle); /* Configure the DMA stream */ - HAL_DMA_Init(&dma_handle); + _HAL_DMA_Init(&dma_handle); /* NVIC configuration for DMA transfer complete interrupt */ - HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); + NVIC_SetPriority(SDRAM_DMAx_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0)); + /* Enable interrupt */ + NVIC_EnableIRQ(SDRAM_DMAx_IRQn); } - -/** - * @brief DeInitializes SDRAM MSP. - * @param hsdram: SDRAM handle - * @param Params - * @retval None - */ -__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) -{ - static DMA_HandleTypeDef dma_handle; - - /* Disable NVIC configuration for DMA interrupt */ - HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); - - /* Deinitialize the stream for new transfer */ - dma_handle.Instance = SDRAM_DMAx_STREAM; - HAL_DMA_DeInit(&dma_handle); - - /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications - by surcharging this __weak function */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h index 5512f9d8..abf88291 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h @@ -44,127 +44,13 @@ extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_rcc.h" -#include "stm32f7xx_hal_rcc_ex.h" -#include "stm32f7xx_hal_dma.h" -#include "stm32f7xx_hal_gpio.h" -#include "stm32f7xx_hal_sdram.h" -#include "stm32f7xx_ll_fmc.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup STM32746G_DISCOVERY - * @{ - */ - -/** @addtogroup STM32746G_DISCOVERY_SDRAM - * @{ - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types - * @{ - */ - -/** - * @brief SDRAM status structure definition - */ -#define SDRAM_OK ((uint8_t)0x00) -#define SDRAM_ERROR ((uint8_t)0x01) - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants - * @{ - */ #define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) #define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */ -/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ -#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 - -#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 -/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ - -#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ - -#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) - -/* DMA definitions for SDRAM DMA transfer */ -#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0 -#define SDRAM_DMAx_STREAM DMA2_Stream0 -#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn -#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler -/** - * @} - */ - -/** - * @brief FMC SDRAM Mode definition register defines - */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) -/** - * @} - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro - * @{ - */ -/** - * @} - */ - -/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions - * @{ - */ -uint8_t BSP_SDRAM_Init(void); -uint8_t BSP_SDRAM_DeInit(void); -void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount); -uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd); -void BSP_SDRAM_DMA_IRQHandler(void); - -/* These functions can be modified in case the current settings (e.g. DMA stream) - need to be changed for specific application needs */ -void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params); -void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params); - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ +void BSP_SDRAM_Init(void); #ifdef __cplusplus } #endif -#endif /* __STM32746G_DISCOVERY_SDRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c index 794d3c66..73df79e8 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c +++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c @@ -1,6 +1,7 @@ #include "gfx.h" #include "stm32f7xx_hal.h" +#if !GFX_USE_OS_CHIBIOS systemticks_t gfxSystemTicks(void) { return HAL_GetTick(); @@ -10,13 +11,12 @@ systemticks_t gfxMillisecondsToTicks(delaytime_t ms) { return ms; } +#endif static void SystemClock_Config(void); static void CPU_CACHE_Enable(void); void Raw32OSInit(void) { - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - /* Enable the CPU Cache */ CPU_CACHE_Enable(); @@ -31,6 +31,7 @@ void Raw32OSInit(void) { /* Configure the system clock to 216 MHz */ SystemClock_Config(); +#if !GFX_USE_OS_CHIBIOS // LED - for testing GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_PIN_1; @@ -39,6 +40,7 @@ void Raw32OSInit(void) { GPIO_InitStruct.Speed = GPIO_SPEED_FAST; __GPIOI_CLK_ENABLE(); HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); +#endif } @@ -64,48 +66,6 @@ void Raw32OSInit(void) { */ void SystemClock_Config(void) { -#if 0 - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - HAL_StatusTypeDef ret = HAL_OK; - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 12; - RCC_OscInitStruct.PLL.PLLN = 192; // 432 - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 2; // 9 - - ret = HAL_RCC_OscConfig(&RCC_OscInitStruct); - if(ret != HAL_OK) - { - while(1) { ; } - } - - /* Activate the OverDrive to reach the 200/216 MHz Frequency */ - ret = HAL_PWREx_EnableOverDrive(); - if(ret != HAL_OK) - { - while(1) { ; } - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - - ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6); // FLASH_LATENCY_7 - if(ret != HAL_OK) - { - while(1) { ; } - } -#else - RCC_OscInitTypeDef RCC_OscInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; @@ -143,7 +103,6 @@ void SystemClock_Config(void) HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); -#endif } /** diff --git a/boards/base/STM32F746-Discovery/stm32f7_i2c.c b/boards/base/STM32F746-Discovery/stm32f7_i2c.c index b0fa8163..d1e2ed28 100644 --- a/boards/base/STM32F746-Discovery/stm32f7_i2c.c +++ b/boards/base/STM32F746-Discovery/stm32f7_i2c.c @@ -1,3 +1,4 @@ +#include "gfx.h" #include "stm32f7_i2c.h" /* @@ -119,6 +120,8 @@ void i2cWriteReg(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr, uint8_t v void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length) { + int i; + // We are currently not able to read more than 255 bytes at once if (length > 255) { return; @@ -128,7 +131,7 @@ void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length _i2cConfigTransfer(i2c, slaveAddr, length, I2C_CR2_RD_WRN | I2C_CR2_AUTOEND, I2C_CR2_START); // Transmit the whole buffer - for (int i = 0; i < length; i++) { + for (i = 0; i < length; i++) { while (!(i2c->ISR & I2C_ISR_RXNE)); data[i] = i2c->RXDR; } diff --git a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c deleted file mode 100644 index 38adbcae..00000000 --- a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c +++ /dev/null @@ -1,1123 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_fmc.c - * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 - * @brief FMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Flexible Memory Controller (FMC) peripheral memories: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### FMC peripheral features ##### - ============================================================================== - [..] The Flexible memory controller (FMC) includes three memory controllers: - (+) The NOR/PSRAM memory controller - (+) The NAND memory controller - (+) The Synchronous DRAM (SDRAM) controller - - [..] The FMC functional block makes the interface with synchronous and asynchronous static - memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol - (+) to meet the access time requirements of the external memory devices - - [..] All external memories share the addresses, data and control signals with the controller. - Each external device is accessed by means of a unique Chip Select. The FMC performs - only one access at a time to an external device. - The main features of the FMC controller are the following: - (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM) - (++) Read-only memory (ROM) - (++) NOR Flash memory/OneNAND Flash memory - (++) PSRAM (4 memory banks) - (++) 16-bit PC Card compatible devices - (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of - data - (+) Interface with synchronous DRAM (SDRAM) memories - (+) Independent Chip Select control for each memory bank - (+) Independent configuration for each memory bank - - @endverbatim - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup FMC_LL FMC Low Layer - * @brief FMC driver modules - * @{ - */ - -#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions - * @{ - */ - -/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions - * @brief NORSRAM Controller functions - * - @verbatim - ============================================================================== - ##### How to use NORSRAM device driver ##### - ============================================================================== - - [..] - This driver contains a set of APIs to interface with the FMC NORSRAM banks in order - to run the NORSRAM external devices. - - (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() - (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() - (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() - (+) FMC NORSRAM bank extended timing configuration using the function - FMC_NORSRAM_Extended_Timing_Init() - (+) FMC NORSRAM bank enable/disable write operation using the functions - FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() - - -@endverbatim - * @{ - */ - -/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NORSRAM interface - (+) De-initialize the FMC NORSRAM interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the FMC_NORSRAM device according to the specified - * control parameters in the FMC_NORSRAM_InitTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Init: Pointer to NORSRAM Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); - assert_param(IS_FMC_MUX(Init->DataAddressMux)); - assert_param(IS_FMC_MEMORY(Init->MemoryType)); - assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); - assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); - assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); - assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); - assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); - assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); - assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); - assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); - assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); - assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); - assert_param(IS_FMC_PAGESIZE(Init->PageSize)); - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Init->NSBank]; - - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ - tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ - FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ - FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \ - FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ - FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS)); - - /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->WriteBurst |\ - Init->ContinuousClock |\ - Init->PageSize |\ - Init->WriteFifo); - - if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) - { - tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; - } - - Device->BTCR[Init->NSBank] = tmpr; - - /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ - if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) - { - Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; - Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\ - Init->ContinuousClock); - } - if(Init->NSBank != FMC_NORSRAM_BANK1) - { - Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); - } - - return HAL_OK; -} - - -/** - * @brief DeInitialize the FMC_NORSRAM peripheral - * @param Device: Pointer to NORSRAM device instance - * @param ExDevice: Pointer to NORSRAM extended mode device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Disable the FMC_NORSRAM device */ - __FMC_NORSRAM_DISABLE(Device, Bank); - - /* De-initialize the FMC_NORSRAM device */ - /* FMC_NORSRAM_BANK1 */ - if(Bank == FMC_NORSRAM_BANK1) - { - Device->BTCR[Bank] = 0x000030DB; - } - /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ - else - { - Device->BTCR[Bank] = 0x000030D2; - } - - Device->BTCR[Bank + 1] = 0x0FFFFFFF; - ExDevice->BWTR[Bank] = 0x0FFFFFFF; - - return HAL_OK; -} - - -/** - * @brief Initialize the FMC_NORSRAM Timing according to the specified - * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); - assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); - assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Bank + 1]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ - FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ - FMC_BTR1_ACCMOD)); - - /* Set FMC_NORSRAM device timing parameters */ - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4) |\ - ((Timing->DataSetupTime) << 8) |\ - ((Timing->BusTurnAroundDuration) << 16) |\ - (((Timing->CLKDivision)-1) << 20) |\ - (((Timing->DataLatency)-2) << 24) |\ - (Timing->AccessMode) - ); - - Device->BTCR[Bank + 1] = tmpr; - - /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ - if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) - { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); - tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20); - Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr; - } - - return HAL_OK; -} - -/** - * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified - * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); - - /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) - { - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); - assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); - assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Get the BWTR register value */ - tmpr = Device->BWTR[Bank]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ - FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); - - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4) |\ - ((Timing->DataSetupTime) << 8) |\ - ((Timing->BusTurnAroundDuration) << 16) |\ - (Timing->AccessMode)); - - Device->BWTR[Bank] = tmpr; - } - else - { - Device->BWTR[Bank] = 0x0FFFFFFF; - } - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NORSRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NORSRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Enable write operation */ - Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Disable write operation */ - Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions - * @brief NAND Controller functions - * - @verbatim - ============================================================================== - ##### How to use NAND device driver ##### - ============================================================================== - [..] - This driver contains a set of APIs to interface with the FMC NAND banks in order - to run the NAND external devices. - - (+) FMC NAND bank reset using the function FMC_NAND_DeInit() - (+) FMC NAND bank control configuration using the function FMC_NAND_Init() - (+) FMC NAND bank common space timing configuration using the function - FMC_NAND_CommonSpace_Timing_Init() - (+) FMC NAND bank attribute space timing configuration using the function - FMC_NAND_AttributeSpace_Timing_Init() - (+) FMC NAND bank enable/disable ECC correction feature using the functions - FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() - (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() - -@endverbatim - * @{ - */ - -/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NAND interface - (+) De-initialize the FMC NAND interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FMC_NAND device according to the specified - * control parameters in the FMC_NAND_HandleTypeDef - * @param Device: Pointer to NAND device instance - * @param Init: Pointer to NAND Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Init->NandBank)); - assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); - assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); - assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); - assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - - /* Get the NAND bank 3 register value */ - tmpr = Device->PCR; - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ - FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ - FMC_PCR_TAR | FMC_PCR_ECCPS)); - /* Set NAND device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FMC_PCR_MEMORY_TYPE_NAND |\ - Init->MemoryDataWidth |\ - Init->EccComputation |\ - Init->ECCPageSize |\ - ((Init->TCLRSetupTime) << 9) |\ - ((Init->TARSetupTime) << 13)); - - /* NAND bank 3 registers configuration */ - Device->PCR = tmpr; - - return HAL_OK; - -} - -/** - * @brief Initializes the FMC_NAND Common space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get the NAND bank 3 register value */ - tmpr = Device->PMEM; - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \ - FMC_PMEM_MEMHIZ3)); - /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8) |\ - ((Timing->HoldSetupTime) << 16) |\ - ((Timing->HiZSetupTime) << 24) - ); - - /* NAND bank 3 registers configuration */ - Device->PMEM = tmpr; - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Attribute space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get the NAND bank 3 register value */ - tmpr = Device->PATT; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \ - FMC_PATT_ATTHIZ3)); - /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8) |\ - ((Timing->HoldSetupTime) << 16) |\ - ((Timing->HiZSetupTime) << 24)); - - /* NAND bank 3 registers configuration */ - Device->PATT = tmpr; - - return HAL_OK; -} - -/** - * @brief DeInitializes the FMC_NAND device - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable the NAND Bank */ - __FMC_NAND_DISABLE(Device); - - /* Set the FMC_NAND_BANK3 registers to their reset values */ - Device->PCR = 0x00000018; - Device->SR = 0x00000040; - Device->PMEM = 0xFCFCFCFC; - Device->PATT = 0xFCFCFCFC; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_FMC_NAND_Group3 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NAND Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NAND interface. - -@endverbatim - * @{ - */ - - -/** - * @brief Enables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Enable ECC feature */ - Device->PCR |= FMC_PCR_ECCEN; - - return HAL_OK; -} - - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable ECC feature */ - Device->PCR &= ~FMC_PCR_ECCEN; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param ECCval: Pointer to ECC value - * @param Bank: NAND bank number - * @param Timeout: Timeout wait value - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until FIFO is empty */ - while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Get the ECCR register value */ - *ECCval = (uint32_t)Device->ECCR; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_LL_SDRAM - * @brief SDRAM Controller functions - * - @verbatim - ============================================================================== - ##### How to use SDRAM device driver ##### - ============================================================================== - [..] - This driver contains a set of APIs to interface with the FMC SDRAM banks in order - to run the SDRAM external devices. - - (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() - (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() - (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() - (+) FMC SDRAM bank enable/disable write operation using the functions - FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() - (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() - -@endverbatim - * @{ - */ - -/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC SDRAM interface - (+) De-initialize the FMC SDRAM interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FMC_SDRAM device according to the specified - * control parameters in the FMC_SDRAM_InitTypeDef - * @param Device: Pointer to SDRAM device instance - * @param Init: Pointer to SDRAM Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) -{ - uint32_t tmpr1 = 0; - uint32_t tmpr2 = 0; - - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); - assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); - assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); - assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); - assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); - assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); - assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); - assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); - assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); - - /* Set SDRAM bank configuration parameters */ - if (Init->SDBank != FMC_SDRAM_BANK2) - { - tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ - Init->RowBitsNumber |\ - Init->MemoryDataWidth |\ - Init->InternalBankNumber |\ - Init->CASLatency |\ - Init->WriteProtection |\ - Init->SDClockPeriod |\ - Init->ReadBurst |\ - Init->ReadPipeDelay - ); - Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; - } - else /* FMC_Bank2_SDRAM */ - { - tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ - Init->ReadBurst |\ - Init->ReadPipeDelay); - - tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ - Init->RowBitsNumber |\ - Init->MemoryDataWidth |\ - Init->InternalBankNumber |\ - Init->CASLatency |\ - Init->WriteProtection); - - Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; - Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; - } - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_SDRAM device timing according to the specified - * parameters in the FMC_SDRAM_TimingTypeDef - * @param Device: Pointer to SDRAM device instance - * @param Timing: Pointer to SDRAM Timing structure - * @param Bank: SDRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr1 = 0; - uint32_t tmpr2 = 0; - - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); - assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); - assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); - assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); - assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); - assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); - assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Set SDRAM device timing parameters */ - if (Bank != FMC_SDRAM_BANK2) - { - tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ - (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ - (((Timing->SelfRefreshTime)-1) << 8) |\ - (((Timing->RowCycleDelay)-1) << 12) |\ - (((Timing->WriteRecoveryTime)-1) <<16) |\ - (((Timing->RPDelay)-1) << 20) |\ - (((Timing->RCDDelay)-1) << 24)); - Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; - } - else /* FMC_Bank2_SDRAM */ - { - tmpr1 = Device->SDTR[FMC_SDRAM_BANK2]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ - (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ - (((Timing->SelfRefreshTime)-1) << 8) |\ - (((Timing->WriteRecoveryTime)-1) <<16) |\ - (((Timing->RCDDelay)-1) << 24)); - - tmpr2 = Device->SDTR[FMC_SDRAM_BANK1]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ - (((Timing->RPDelay)-1) << 20)); - - Device->SDTR[FMC_SDRAM_BANK2] = tmpr1; - Device->SDTR[FMC_SDRAM_BANK1] = tmpr2; - } - - return HAL_OK; -} - -/** - * @brief DeInitializes the FMC_SDRAM peripheral - * @param Device: Pointer to SDRAM device instance - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* De-initialize the SDRAM device */ - Device->SDCR[Bank] = 0x000002D0; - Device->SDTR[Bank] = 0x0FFFFFFF; - Device->SDCMR = 0x00000000; - Device->SDRTR = 0x00000000; - Device->SDSR = 0x00000000; - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_SDRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC SDRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FMC_SDRAM write protection. - * @param Device: Pointer to SDRAM device instance - * @param Bank: SDRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Enable write protection */ - Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_SDRAM write protection. - * @param hsdram: FMC_SDRAM handle - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Disable write protection */ - Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; - - return HAL_OK; -} - -/** - * @brief Send Command to the FMC SDRAM bank - * @param Device: Pointer to SDRAM device instance - * @param Command: Pointer to SDRAM command structure - * @param Timing: Pointer to SDRAM Timing structure - * @param Timeout: Timeout wait value - * @retval HAL state - */ -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) -{ - __IO uint32_t tmpr = 0; - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); - assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); - assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); - assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); - - /* Set command register */ - tmpr = (uint32_t)((Command->CommandMode) |\ - (Command->CommandTarget) |\ - (((Command->AutoRefreshNumber)-1) << 5) |\ - ((Command->ModeRegisterDefinition) << 9) - ); - - Device->SDCMR = tmpr; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* wait until command is send */ - while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Program the SDRAM Memory Refresh rate. - * @param Device: Pointer to SDRAM device instance - * @param RefreshRate: The SDRAM refresh rate value. - * @retval HAL state - */ -HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); - - /* Set the refresh rate in command register */ - Device->SDRTR |= (RefreshRate<<1); - - return HAL_OK; -} - -/** - * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. - * @param Device: Pointer to SDRAM device instance - * @param AutoRefreshNumber: Specifies the auto Refresh number. - * @retval None - */ -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); - - /* Set the Auto-refresh number in command register */ - Device->SDCMR |= (AutoRefreshNumber << 5); - - return HAL_OK; -} - -/** - * @brief Returns the indicated FMC SDRAM bank mode status. - * @param Device: Pointer to SDRAM device instance - * @param Bank: Defines the FMC SDRAM bank. This parameter can be - * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. - * @retval The FMC SDRAM bank mode status, could be on of the following values: - * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or - * FMC_SDRAM_POWER_DOWN_MODE. - */ -uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Get the corresponding bank mode */ - if(Bank == FMC_SDRAM_BANK1) - { - tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); - } - else - { - tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2); - } - - /* Return the mode status */ - return tmpreg; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h deleted file mode 100644 index 85e8bedf..00000000 --- a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h +++ /dev/null @@ -1,1338 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_fmc.h - * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 - * @brief Header file of FMC HAL module. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_FMC_H -#define __STM32F7xx_LL_FMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gfx.h" -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup FMC_LL - * @{ - */ - -/** @addtogroup FMC_LL_Private_Macros - * @{ - */ -#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \ - ((BANK) == FMC_NORSRAM_BANK2) || \ - ((BANK) == FMC_NORSRAM_BANK3) || \ - ((BANK) == FMC_NORSRAM_BANK4)) - -#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) - -#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) - -#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) - -#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ - ((__MODE__) == FMC_ACCESS_MODE_B) || \ - ((__MODE__) == FMC_ACCESS_MODE_C) || \ - ((__MODE__) == FMC_ACCESS_MODE_D)) - -#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3) - -#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ - ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE)) - -#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \ - ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16)) - -#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \ - ((STATE) == FMC_NAND_ECC_ENABLE)) - -#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) - -#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ - ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ - ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32)) - -#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ - ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) - -#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ - ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ - ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) - -#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ - ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) - -#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ - ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ - ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) - -#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) - -#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ - ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ - ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) - -/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time - * @{ - */ -#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time - * @{ - */ -#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Setup_Time FMC Setup Time - * @{ - */ -#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254) -/** - * @} - */ - -/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time - * @{ - */ -#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254) -/** - * @} - */ - -/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time - * @{ - */ -#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254) -/** - * @} - */ - -/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time - * @{ - */ -#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254) -/** - * @} - */ - -#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) - -#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) - -#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) - -#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) - -#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) - -#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) - -#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) - -/** @defgroup FMC_Data_Latency FMC Data Latency - * @{ - */ -#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) -/** - * @} - */ - -#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FMC_WRITE_BURST_ENABLE)) - -#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) - - -/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time - * @{ - */ -#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ - -/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time - * @{ - */ -#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) -/** - * @} - */ - -/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time - * @{ - */ -#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) -/** - * @} - */ - -/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration - * @{ - */ -#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ - -/** @defgroup FMC_CLK_Division FMC CLK Division - * @{ - */ -#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay - * @{ - */ -#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay - * @{ - */ -#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time - * @{ - */ -#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay - * @{ - */ -#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time - * @{ - */ -#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay - * @{ - */ -#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay - * @{ - */ -#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number - * @{ - */ -#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition - * @{ - */ -#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate - * @{ - */ -#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance - * @{ - */ -#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance - * @{ - */ -#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) -/** - * @} - */ - -/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance - * @{ - */ -#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance - * @{ - */ -#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) -/** - * @} - */ - -#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \ - ((BANK) == FMC_SDRAM_BANK2)) - -#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ - ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ - ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ - ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11)) - -#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \ - ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \ - ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13)) - -#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ - ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4)) - - -#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \ - ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \ - ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3)) - -#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ - ((__SIZE__) == FMC_PAGE_SIZE_128) || \ - ((__SIZE__) == FMC_PAGE_SIZE_256) || \ - ((__SIZE__) == FMC_PAGE_SIZE_1024)) - -#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ - ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) -/** - * @} - */ - -/* Exported typedef ----------------------------------------------------------*/ -/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types - * @{ - */ -#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef -#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef -#define FMC_NAND_TypeDef FMC_Bank3_TypeDef -#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef - -#define FMC_NORSRAM_DEVICE FMC_Bank1 -#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E -#define FMC_NAND_DEVICE FMC_Bank3 -#define FMC_SDRAM_DEVICE FMC_Bank5_6 - -/** - * @brief FMC NORSRAM Configuration Structure definition - */ -typedef struct -{ - uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ - - uint32_t DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ - - uint32_t MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ - - uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ - - uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ - - uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ - - uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ - - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ - - uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ - - uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ - - uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ - - uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ - - uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ - - uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ - - uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ - -}FMC_NORSRAM_InitTypeDef; - -/** - * @brief FMC NORSRAM Timing parameters structure definition - */ -typedef struct -{ - uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between Min_Data = 1 and Max_Data = 255. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ - - uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ - - uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ -}FMC_NORSRAM_TimingTypeDef; - -/** - * @brief FMC NAND Configuration Structure definition - */ -typedef struct -{ - uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ - - uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FMC_Wait_feature */ - - uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FMC_NAND_Data_Width */ - - uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FMC_ECC */ - - uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FMC_ECC_Page_Size */ - - uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - - uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_NAND_InitTypeDef; - -/** - * @brief FMC NAND Timing parameters structure definition - */ -typedef struct -{ - uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ - - uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ - - uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command de-assertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ - - uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - data bus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ -}FMC_NAND_PCC_TimingTypeDef; - -/** - * @brief FMC SDRAM Configuration Structure definition - */ -typedef struct -{ - uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. - This parameter can be a value of @ref FMC_SDRAM_Bank */ - - uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. - This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ - - uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. - This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ - - uint32_t MemoryDataWidth; /*!< Defines the memory device width. - This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ - - uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. - This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ - - uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. - This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ - - uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. - This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ - - uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow - to disable the clock before changing frequency. - This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ - - uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read - commands during the CAS latency and stores data in the Read FIFO. - This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ - - uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. - This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ -}FMC_SDRAM_InitTypeDef; - -/** - * @brief FMC SDRAM Timing parameters structure definition - */ -typedef struct -{ - uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and - an active or Refresh command in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to - issuing the Activate command in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock - cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command - and the delay between two consecutive Refresh commands in number of - memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command - in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write - command in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ -}FMC_SDRAM_TimingTypeDef; - -/** - * @brief SDRAM command parameters structure definition - */ -typedef struct -{ - uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. - This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ - - uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. - This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ - - uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued - in auto refresh mode. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ -}FMC_SDRAM_CommandTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants - * @{ - */ - -/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller - * @{ - */ - -/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank - * @{ - */ -#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) -#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) -#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) -#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing - * @{ - */ -#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) -#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) -/** - * @} - */ - -/** @defgroup FMC_Memory_Type FMC Memory Type - * @{ - */ -#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) -#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) -#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width - * @{ - */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access - * @{ - */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode - * @{ - */ -#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) -#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity - * @{ - */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) -#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) -/** - * @} - */ - -/** @defgroup FMC_Wait_Timing FMC Wait Timing - * @{ - */ -#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) -#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) -/** - * @} - */ - -/** @defgroup FMC_Write_Operation FMC Write Operation - * @{ - */ -#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) -#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) -/** - * @} - */ - -/** @defgroup FMC_Wait_Signal FMC Wait Signal - * @{ - */ -#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) -#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) -/** - * @} - */ - -/** @defgroup FMC_Extended_Mode FMC Extended Mode - * @{ - */ -#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) -#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) -/** - * @} - */ - -/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait - * @{ - */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) -#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) -/** - * @} - */ - -/** @defgroup FMC_Page_Size FMC Page Size - * @{ - */ -#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) -#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) -#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) -#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) -/** - * @} - */ - -/** @defgroup FMC_Write_Burst FMC Write Burst - * @{ - */ -#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) -#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) -/** - * @} - */ - -/** @defgroup FMC_Continous_Clock FMC Continuous Clock - * @{ - */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) -/** - * @} - */ - -/** @defgroup FMC_Write_FIFO FMC Write FIFO - * @{ - */ -#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000) -#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS) -/** - * @} - */ - -/** @defgroup FMC_Access_Mode FMC Access Mode - * @{ - */ -#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) -#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000) -#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000) -#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller - * @{ - */ -/** @defgroup FMC_NAND_Bank FMC NAND Bank - * @{ - */ -#define FMC_NAND_BANK3 ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FMC_Wait_feature FMC Wait feature - * @{ - */ -#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) -#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) -/** - * @} - */ - -/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type - * @{ - */ -#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width - * @{ - */ -#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) -/** - * @} - */ - -/** @defgroup FMC_ECC FMC ECC - * @{ - */ -#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) -#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) -/** - * @} - */ - -/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size - * @{ - */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller - * @{ - */ -/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank - * @{ - */ -#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000) -#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number - * @{ - */ -#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000) -#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001) -#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002) -#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number - * @{ - */ -#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000) -#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004) -#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width - * @{ - */ -#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) -#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number - * @{ - */ -#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000) -#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency - * @{ - */ -#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080) -#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100) -#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection - * @{ - */ -#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000) -#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period - * @{ - */ -#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000) -#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800) -#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst - * @{ - */ -#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000) -#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay - * @{ - */ -#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000) -#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000) -#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode - * @{ - */ -#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000) -#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001) -#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002) -#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003) -#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004) -#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005) -#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target - * @{ - */ -#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 -#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 -#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status - * @{ - */ -#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000) -#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 -#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition - * @{ - */ -#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008) -#define FMC_IT_LEVEL ((uint32_t)0x00000010) -#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020) -#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000) -/** - * @} - */ - -/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition - * @{ - */ -#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) -#define FMC_FLAG_LEVEL ((uint32_t)0x00000002) -#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) -#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE -#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY -#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros - * @{ - */ - -/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros - * @brief macros to handle NOR device enable/disable and read/write operations - * @{ - */ - -/** - * @brief Enable the NORSRAM device access. - * @param __INSTANCE__: FMC_NORSRAM Instance - * @param __BANK__: FMC_NORSRAM Bank - * @retval None - */ -#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) - -/** - * @brief Disable the NORSRAM device access. - * @param __INSTANCE__: FMC_NORSRAM Instance - * @param __BANK__: FMC_NORSRAM Bank - * @retval None - */ -#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) - -/** - * @} - */ - -/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ - -/** - * @brief Enable the NAND device access. - * @param __INSTANCE__: FMC_NAND Instance - * @retval None - */ -#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) - -/** - * @brief Disable the NAND device access. - * @param __INSTANCE__: FMC_NAND Instance - * @retval None - */ -#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) - -/** - * @} - */ - -/** @defgroup FMC_Interrupt FMC Interrupt - * @brief macros to handle FMC interrupts - * @{ - */ - -/** - * @brief Enable the NAND device interrupt. - * @param __INSTANCE__: FMC_NAND instance - * @param __INTERRUPT__: FMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) - -/** - * @brief Disable the NAND device interrupt. - * @param __INSTANCE__: FMC_NAND Instance - * @param __INTERRUPT__: FMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) - -/** - * @brief Get flag status of the NAND device. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank - * @param __FLAG__: FMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear flag status of the NAND device. - * @param __INSTANCE__: FMC_NAND Instance - * @param __FLAG__: FMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. - * @retval None - */ -#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) - -/** - * @brief Enable the SDRAM device interrupt. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __INTERRUPT__: FMC_SDRAM interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error - * @retval None - */ -#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) - -/** - * @brief Disable the SDRAM device interrupt. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __INTERRUPT__: FMC_SDRAM interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error - * @retval None - */ -#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) - -/** - * @brief Get flag status of the SDRAM device. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __FLAG__: FMC_SDRAM flag - * This parameter can be any combination of the following values: - * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. - * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. - * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear flag status of the SDRAM device. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __FLAG__: FMC_SDRAM flag - * This parameter can be any combination of the following values: - * @arg FMC_SDRAM_FLAG_REFRESH_ERROR - * @retval None - */ -#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions - * @{ - */ - -/** @defgroup FMC_LL_NORSRAM NOR SRAM - * @{ - */ -/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); -/** - * @} - */ - -/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions - * @{ - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); -/** - * @} - */ -/** - * @} - */ - -/** @defgroup FMC_LL_NAND NAND - * @{ - */ -/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); -/** - * @} - */ - -/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions - * @{ - */ -HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); -/** - * @} - */ - -/** @defgroup FMC_LL_SDRAM SDRAM - * @{ - */ -/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); - -/** - * @} - */ - -/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions - * @{ - */ -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); -HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); -uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_FMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/applications/combo/bounce.c b/demos/applications/combo/bounce.c new file mode 100644 index 00000000..72e75af8 --- /dev/null +++ b/demos/applications/combo/bounce.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org> + * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket + * Derived from the 2011 IOCCC submission by peter.eastman@gmail.com + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the <organization> nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "gfx.h" +#include <math.h> + +#include "tasks.h" + +static volatile bool_t run; +static GHandle gh; +static gfxThreadHandle thread; + +/** + * NOTE: + * + * This demo uses floating point operations. Don't expect it to work with any + * speed unless your processor has an FPU. + * + * If you see garbage inside the ball as it is running rather than the red and yellow + * checkerboard pattern then the fast invsqrt() function in GMISC does not work on + * your processor. + * + * You can modify the implementation of invsqrt() by firstly defining + * #define GMISC_INVSQRT_MIXED_ENDIAN TRUE + * in your gfxconf.h file. + * + * If it still doesn't work then instead define + * #define GMISC_INVSQRT_REAL_SLOW TRUE + * in your gfxconf.h file. This should always work although it will probably be slow. + */ +#define BALLCOLOR1 Red +#define BALLCOLOR2 Yellow +#define WALLCOLOR HTML2COLOR(0x303030) +#define BACKCOLOR HTML2COLOR(0xC0C0C0) +#define FLOORCOLOR HTML2COLOR(0x606060) +#define SHADOWALPHA (255-255*0.2) + +static DECLARE_THREAD_FUNCTION(task, param) { + coord_t width, height, x, y, radius, ballx, bally, dx, floor; + coord_t minx, miny, maxx, maxy, winx, winy; + coord_t ballcx, ballcy; + color_t colour; + float ii, spin, dy, spinspeed, h, f, g; + (void) param; + + winx = gwinGetScreenX(gh); + winy = gwinGetScreenY(gh); + width = gwinGetWidth(gh); + height = gwinGetHeight(gh); + + radius=height/5+height%2+1; // The ball radius + ii = 1.0/radius; // radius as easy math + floor=height/5-1; // floor position + spin=0.0; // current spin angle on the ball + spinspeed=0.1; // current spin speed of the ball + ballx=width/2; // ball x position (relative to the ball center) + bally=height/4; // ball y position (relative to the ball center) + dx=.01*width; // motion in the x axis + dy=0.0; // motion in the y axis + ballcx = 12*radius/5; // ball x diameter including the shadow + ballcy = 21*radius/10; // ball y diameter including the shadow + + + minx = miny = 0; maxx = width; maxy = height; // The clipping window for this frame. + + while(run) { + gfxYield(); + + // Draw one frame + gdispStreamStart(winx+minx, winy+miny, maxx-minx, maxy-miny); + for (y=miny; h = (bally-y)*ii, y<maxy; y++) { + for (x=minx; x < maxx; x++) { + g=(ballx-x)*ii; + f=-.3*g+.954*h; + if (g*g < 1-h*h) { + /* The inside of the ball */ + if ((((int)(9-spin+(.954*g+.3*h)*invsqrt(1-f*f))+(int)(2+f*2))&1)) + colour = BALLCOLOR1; + else + colour = BALLCOLOR2; + } else { + // The background (walls and floor) + if (y > height-floor) { + if (x < height-y || height-y > width-x) + colour = WALLCOLOR; + else + colour = FLOORCOLOR; + } else if (x<floor || x>width-floor) + colour = WALLCOLOR; + else + colour = BACKCOLOR; + + // The ball shadow is darker + if (g*(g+.4)+h*(h+.1) < 1) + colour = gdispBlendColor(colour, Black, SHADOWALPHA); + } + gdispStreamColor(colour); /* pixel to the LCD */ + } + } + gdispStreamStop(); + + // Force a display update if the controller supports it + gdispFlush(); + + // Calculate the new frame size (note this is a drawing optimisation only) + minx = ballx - radius; miny = bally - radius; + maxx = minx + ballcx; maxy = miny + ballcy; + if (dx > 0) maxx += dx; else minx += dx; + if (dy > 0) maxy += dy; else miny += dy; + if (minx < 0) minx = 0; + if (maxx > width) maxx = width; + if (miny < 0) miny = 0; + if (maxy > height) maxy = height; + + // Motion + spin += spinspeed; + ballx += dx; bally += dy; + dx = ballx < radius || ballx > width-radius ? spinspeed=-spinspeed,-dx : dx; + dy = bally > height-1.75*floor ? -.04*height : dy+.002*height; + } + return 0; +} + +void doBounce(GHandle parent, bool_t start) { + if (start) { + run = TRUE; + gh = parent; + thread = gfxThreadCreate(0, 0x200, LOW_PRIORITY, task, 0); + } else if (run) { + run = FALSE; + gfxThreadWait(thread); + gfxYield(); + } +} + diff --git a/demos/applications/combo/demo.mk b/demos/applications/combo/demo.mk new file mode 100644 index 00000000..bfac9743 --- /dev/null +++ b/demos/applications/combo/demo.mk @@ -0,0 +1,6 @@ +DEMODIR = $(GFXLIB)/demos/applications/combo +GFXINC += $(DEMODIR) +GFXSRC += $(DEMODIR)/main.c \ + $(DEMODIR)/mandelbrot.c \ + $(DEMODIR)/bounce.c +
\ No newline at end of file diff --git a/demos/applications/combo/gfxconf.h b/demos/applications/combo/gfxconf.h new file mode 100644 index 00000000..fcf7f96a --- /dev/null +++ b/demos/applications/combo/gfxconf.h @@ -0,0 +1,126 @@ +/** + * This file has a different license to the rest of the uGFX system. + * You can copy, modify and distribute this file as you see fit. + * You do not need to publish your source modifications to this file. + * The only thing you are not permitted to do is to relicense it + * under a different license. + */ + +/** + * Copy this file into your project directory and rename it as gfxconf.h + * Edit your copy to turn on the uGFX features you want to use. + * The values below are the defaults. You should delete anything + * you are leaving as default. + * + * Please use spaces instead of tabs in this file. + */ + +#ifndef _GFXCONF_H +#define _GFXCONF_H + +/* The operating system to use. One of these must be defined - preferably in your Makefile */ +//#define GFX_USE_OS_CHIBIOS TRUE +//#define GFX_USE_OS_WIN32 TRUE +//#define GFX_USE_OS_LINUX TRUE +//#define GFX_USE_OS_OSX TRUE + + +/////////////////////////////////////////////////////////////////////////// +// GDISP // +/////////////////////////////////////////////////////////////////////////// +#define GFX_USE_GDISP TRUE + +#define GDISP_NEED_VALIDATION TRUE +#define GDISP_NEED_CLIP TRUE +#define GDISP_NEED_CIRCLE TRUE +#define GDISP_NEED_CONVEX_POLYGON TRUE +//#define GDISP_NEED_SCROLL TRUE +#define GDISP_NEED_CONTROL TRUE +#define GDISP_NEED_TEXT TRUE + #define GDISP_INCLUDE_FONT_UI2 TRUE +#define GDISP_NEED_STREAMING TRUE + +#define GDISP_NEED_IMAGE TRUE + #define GDISP_NEED_IMAGE_GIF TRUE + +#define GDISP_DEFAULT_ORIENTATION GDISP_ROTATE_LANDSCAPE +#define GDISP_NEED_MULTITHREAD TRUE + +/////////////////////////////////////////////////////////////////////////// +// GWIN // +/////////////////////////////////////////////////////////////////////////// +#define GFX_USE_GWIN TRUE + +#define GWIN_NEED_WINDOWMANAGER TRUE + #define GWIN_NEED_FLASHING TRUE + +#define GWIN_NEED_CONSOLE TRUE + #define GWIN_CONSOLE_USE_HISTORY TRUE + #define GWIN_CONSOLE_HISTORY_AVERAGING TRUE + #define GWIN_CONSOLE_HISTORY_ATCREATE TRUE +#define GWIN_NEED_GRAPH TRUE + +#define GWIN_NEED_WIDGET TRUE + #define GWIN_NEED_LABEL TRUE + #define GWIN_LABEL_ATTRIBUTE TRUE + #define GWIN_NEED_BUTTON TRUE +// #define GWIN_BUTTON_LAZY_RELEASE TRUE + #define GWIN_NEED_SLIDER TRUE + #define GWIN_NEED_CHECKBOX TRUE + #define GWIN_NEED_IMAGE TRUE + #define GWIN_NEED_RADIO TRUE + #define GWIN_NEED_LIST TRUE + #define GWIN_NEED_LIST_IMAGES TRUE + #define GWIN_NEED_PROGRESSBAR TRUE + #define GWIN_PROGRESSBAR_AUTO TRUE + +#define GWIN_NEED_CONTAINERS TRUE + #define GWIN_NEED_CONTAINER TRUE + +#define GWIN_NEED_TABSET TRUE + +/////////////////////////////////////////////////////////////////////////// +// GEVENT // +/////////////////////////////////////////////////////////////////////////// +#define GFX_USE_GEVENT TRUE + +/////////////////////////////////////////////////////////////////////////// +// GTIMER // +/////////////////////////////////////////////////////////////////////////// +#define GFX_USE_GTIMER TRUE + +/////////////////////////////////////////////////////////////////////////// +// GQUEUE // +/////////////////////////////////////////////////////////////////////////// +#define GFX_USE_GQUEUE TRUE + +#define GQUEUE_NEED_ASYNC TRUE + +/////////////////////////////////////////////////////////////////////////// +// GINPUT // +/////////////////////////////////////////////////////////////////////////// +#define GFX_USE_GINPUT TRUE + +#define GINPUT_NEED_MOUSE TRUE +//#define GINPUT_NEED_TOGGLE TRUE +//#define GINPUT_NEED_DIAL TRUE + +/////////////////////////////////////////////////////////////////////////// +// GFILE // +/////////////////////////////////////////////////////////////////////////// +#define GFX_USE_GFILE TRUE + +#define GFILE_NEED_PRINTG TRUE +#define GFILE_NEED_STRINGS TRUE + +#define GFILE_NEED_ROMFS TRUE +//#define GFILE_NEED_NATIVEFS TRUE + +/////////////////////////////////////////////////////////////////////////// +// GMISC // +/////////////////////////////////////////////////////////////////////////// +#define GFX_USE_GMISC TRUE +#define GMISC_NEED_INVSQRT TRUE + + +#endif /* _GFXCONF_H */ diff --git a/demos/applications/combo/main.c b/demos/applications/combo/main.c new file mode 100644 index 00000000..fba3d851 --- /dev/null +++ b/demos/applications/combo/main.c @@ -0,0 +1,533 @@ +/* + * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org> + * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the <organization> nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "gfx.h" +#include "tasks.h" + +/** + * This demo demonstrates many of the ugfx features. + */ + +/** + * The image files must be stored on a GFILE file-system. + * Use either GFILE_NEED_NATIVEFS or GFILE_NEED_ROMFS (or both). + * + * The ROMFS uses the file "romfs_files.h" to describe the set of files in the ROMFS. + */ + +/* Our custom yellow style */ +static const GWidgetStyle YellowWidgetStyle = { + Yellow, // window background + HTML2COLOR(0x800000), // focus - for text edit. + + // enabled color set + { + HTML2COLOR(0x0000FF), // text + HTML2COLOR(0x404040), // edge + HTML2COLOR(0xE0E0E0), // fill + HTML2COLOR(0xE0E0E0) // progress - inactive area + }, + + // disabled color set + { + HTML2COLOR(0xC0C0C0), // text + HTML2COLOR(0x808080), // edge + HTML2COLOR(0xE0E0E0), // fill + HTML2COLOR(0xC0E0C0) // progress - active area + }, + + // pressed color set + { + HTML2COLOR(0xFF00FF), // text + HTML2COLOR(0x404040), // edge + HTML2COLOR(0x808080), // fill + HTML2COLOR(0x00E000), // progress - active area + } +}; + +/* The variables we need */ +static font_t font; +static GListener gl; +static GHandle ghConsole; +static GTimer FlashTimer; + +static GHandle ghTabset; +static GHandle ghPgControls, ghPgSliders, ghPgLabels, ghPgRadios, ghPgLists, ghPgImages, ghPgBounce, ghPgMandelbrot; +static GHandle ghButton1, ghButton2, ghButton3, ghButton4; +static GHandle ghSlider1, ghSlider2, ghSlider3, ghSlider4; +static GHandle ghCheckbox1, ghCheckbox2, ghCheckbox3, ghCheckDisableAll; +static GHandle ghLabelSlider1, ghLabelSlider2, ghLabelSlider3, ghLabelSlider4, ghLabelRadio1; +static GHandle ghRadio1, ghRadio2; +static GHandle ghRadioBlack, ghRadioWhite, ghRadioYellow; +static GHandle ghList1, ghList2, ghList3, ghList4; +static GHandle ghImage1, ghImage2; +static GHandle ghProgressbar1; +static gdispImage imgYesNo; + +/* Some useful macros */ +#define ScrWidth gdispGetWidth() +#define ScrHeight gdispGetHeight() + +#define BUTTON_PADDING 20 +#define TAB_HEIGHT 30 +#define LABEL_HEIGHT 15 +#define BUTTON_WIDTH 50 +#define BUTTON_HEIGHT 30 +#define LIST_WIDTH 75 +#define LIST_HEIGHT 80 +#define SLIDER_WIDTH 20 +#define CHECKBOX_WIDTH 80 +#define CHECKBOX_HEIGHT 20 +#define RADIO_WIDTH 50 +#define RADIO_HEIGHT 20 +#define COLOR_WIDTH 80 +#define DISABLEALL_WIDTH 100 +#define GROUP_TABS 0 +#define GROUP_YESNO 1 +#define GROUP_COLORS 2 + +static void nextline(GWidgetInit *pwi) { + pwi->g.x = 5; + pwi->g.y += pwi->g.height+1; +} + +static void setbtntext(GWidgetInit *pwi, coord_t maxwidth, char *txt) { + pwi->text = txt; + pwi->g.width = gdispGetStringWidth(pwi->text, font) + BUTTON_PADDING; + if (pwi->g.x + pwi->g.width > maxwidth) + nextline(pwi); +} + +static void nextpos(GWidgetInit *pwi, coord_t maxwidth, coord_t nextwidth) { + pwi->g.x += pwi->g.width+1; + pwi->g.width = nextwidth; + if (pwi->g.x + nextwidth > maxwidth) + nextline(pwi); +} +/** + * Create all the widgets. + * With the exception of the Pages they are all initially visible. + * + * This routine is complicated by the fact that we want a dynamic + * layout so it looks good on small and large displays. + * It is tested to work on 320x272 as a minimum LCD size. + */ +static void createWidgets(void) { + GWidgetInit wi; + coord_t border, pagewidth; + + gwinWidgetClearInit(&wi); + + // Calculate page borders based on screen size + border = ScrWidth < 450 ? 1 : 5; + + // Create the Tabs + wi.g.show = TRUE; + wi.g.x = border; wi.g.y = 0; + wi.g.width = ScrWidth - 2*border; wi.g.height = ScrHeight-wi.g.y-border; + ghTabset = gwinTabsetCreate(0, &wi, GWIN_TABSET_BORDER); + ghPgControls = gwinTabsetAddTab(ghTabset, "Controls", FALSE); + ghPgSliders = gwinTabsetAddTab(ghTabset, "Sliders", FALSE); + ghPgRadios = gwinTabsetAddTab(ghTabset, "Radios", FALSE); + ghPgLists = gwinTabsetAddTab(ghTabset, "Lists", FALSE); + ghPgLabels = gwinTabsetAddTab(ghTabset, "Labels", FALSE); + ghPgImages = gwinTabsetAddTab(ghTabset, "Images", FALSE); + ghPgBounce = gwinTabsetAddTab(ghTabset, "Bounce", FALSE); + ghPgMandelbrot = gwinTabsetAddTab(ghTabset, "Mandelbrot", FALSE); + + pagewidth = gwinGetInnerWidth(ghTabset)/2; + + // Console - we apply some special colors before making it visible + // We put the console on the tabset itself rather than a tab-page. + // This makes it appear on every page :) + wi.g.parent = ghTabset; + wi.g.x = pagewidth; + wi.g.width = pagewidth; + ghConsole = gwinConsoleCreate(0, &wi.g); + gwinSetColor(ghConsole, Black); + gwinSetBgColor(ghConsole, HTML2COLOR(0xF0F0F0)); + + // Buttons + wi.g.parent = ghPgControls; + wi.g.width = BUTTON_WIDTH; wi.g.height = BUTTON_HEIGHT; wi.g.y = 5; + wi.g.x = 5; setbtntext(&wi, pagewidth, "Button 1"); + ghButton1 = gwinButtonCreate(0, &wi); + wi.g.x += wi.g.width+3; setbtntext(&wi, pagewidth, "Button 2"); + ghButton2 = gwinButtonCreate(0, &wi); + wi.g.x += wi.g.width+3; setbtntext(&wi, pagewidth, "Button 3"); + ghButton3 = gwinButtonCreate(0, &wi); + wi.g.x += wi.g.width+3; setbtntext(&wi, pagewidth, "Button 4"); + ghButton4 = gwinButtonCreate(0, &wi); + + nextline(&wi); + wi.g.width = CHECKBOX_WIDTH; wi.g.height = CHECKBOX_HEIGHT; + wi.text = "C1"; ghCheckbox1 = gwinCheckboxCreate(0, &wi); + wi.customDraw = gwinCheckboxDraw_CheckOnRight; + nextpos(&wi, pagewidth, CHECKBOX_WIDTH); + wi.text = "C2"; ghCheckbox2 = gwinCheckboxCreate(0, &wi); + wi.customDraw = gwinCheckboxDraw_Button; + nextline(&wi); + wi.text = "C3"; wi.g.width = BUTTON_WIDTH; wi.g.height = BUTTON_HEIGHT; + ghCheckbox3 = gwinCheckboxCreate(0, &wi); + nextpos(&wi, pagewidth, DISABLEALL_WIDTH); + wi.text = "Disable All"; + wi.customDraw = 0; wi.g.height = CHECKBOX_HEIGHT; + ghCheckDisableAll = gwinCheckboxCreate(0, &wi); + + + // Horizontal Sliders + wi.g.parent = ghPgSliders; + wi.g.width = pagewidth - 10; wi.g.height = SLIDER_WIDTH; + wi.g.x = 5; wi.g.y = 5; wi.text = "S1"; + ghSlider1 = gwinSliderCreate(0, &wi); + gwinSliderSetPosition(ghSlider1, 33); + wi.g.y += wi.g.height + 1; wi.text = "S2"; + ghSlider2 = gwinSliderCreate(0, &wi); + gwinSliderSetPosition(ghSlider2, 86); + + // Progressbar + wi.g.y += wi.g.height + 1; wi.text = "Progressbar 1"; + ghProgressbar1 = gwinProgressbarCreate(0, &wi); + gwinProgressbarSetResolution(ghProgressbar1, 10); + + // Vertical Sliders + wi.g.y += wi.g.height + 5; + wi.g.width = SLIDER_WIDTH; wi.g.height = gwinGetInnerHeight(ghPgSliders) - 5 - wi.g.y; + wi.g.x = 5; wi.text = "S3"; + ghSlider3 = gwinSliderCreate(0, &wi); + gwinSliderSetPosition(ghSlider3, 13); + wi.g.x += wi.g.width+1; wi.text = "S4"; + ghSlider4 = gwinSliderCreate(0, &wi); + gwinSliderSetPosition(ghSlider4, 76); + + // Labels + wi.g.parent = ghPgLabels; + wi.g.width = pagewidth-10; wi.g.height = LABEL_HEIGHT; + wi.g.x = wi.g.y = 5; wi.text = "N/A"; + ghLabelSlider1 = gwinLabelCreate(0, &wi); + gwinLabelSetAttribute(ghLabelSlider1, 100, "Slider 1:"); + wi.g.y += LABEL_HEIGHT + 2; + ghLabelSlider2 = gwinLabelCreate(0, &wi); + gwinLabelSetAttribute(ghLabelSlider2, 100, "Slider 2:"); + wi.g.y += LABEL_HEIGHT + 2; + ghLabelSlider3 = gwinLabelCreate(0, &wi); + gwinLabelSetAttribute(ghLabelSlider3, 100, "Slider 3:"); + wi.g.y += LABEL_HEIGHT + 2; + ghLabelSlider4 = gwinLabelCreate(0, &wi); + gwinLabelSetAttribute(ghLabelSlider4, 100, "Slider 4:"); + wi.g.y += LABEL_HEIGHT + 2; + ghLabelRadio1 = gwinLabelCreate(0, &wi); + gwinLabelSetAttribute(ghLabelRadio1, 100, "RadioButton 1:"); + + + // Radio Buttons + wi.g.parent = ghPgRadios; + wi.g.width = RADIO_WIDTH; wi.g.height = RADIO_HEIGHT; wi.g.y = 5; + wi.g.x = 5; wi.text = "Yes"; + ghRadio1 = gwinRadioCreate(0, &wi, GROUP_YESNO); + wi.g.x += wi.g.width; wi.text = "No"; if (wi.g.x + wi.g.width > pagewidth) { wi.g.x = 5; wi.g.y += RADIO_HEIGHT; } + ghRadio2 = gwinRadioCreate(0, &wi, GROUP_YESNO); + gwinRadioPress(ghRadio1); + wi.g.width = COLOR_WIDTH; wi.g.y += RADIO_HEIGHT+5; + wi.g.x = 5; wi.text = "Black"; + ghRadioBlack = gwinRadioCreate(0, &wi, GROUP_COLORS); + wi.g.x += wi.g.width; wi.text = "White"; if (wi.g.x + wi.g.width > pagewidth) { wi.g.x = 5; wi.g.y += RADIO_HEIGHT; } + ghRadioWhite = gwinRadioCreate(0, &wi, GROUP_COLORS); + wi.g.x += wi.g.width; wi.text = "Yellow"; if (wi.g.x + wi.g.width > pagewidth) { wi.g.x = 5; wi.g.y += RADIO_HEIGHT; } + ghRadioYellow = gwinRadioCreate(0, &wi, GROUP_COLORS); + gwinRadioPress(ghRadioWhite); + + // Lists + border = pagewidth < 10+2*LIST_WIDTH ? 2 : 5; + wi.g.parent = ghPgLists; + wi.g.width = LIST_WIDTH; wi.g.height = LIST_HEIGHT; wi.g.y = border; + wi.g.x = border; wi.text = "L1"; + ghList1 = gwinListCreate(0, &wi, FALSE); + gwinListAddItem(ghList1, "Item 0", FALSE); + gwinListAddItem(ghList1, "Item 1", FALSE); + gwinListAddItem(ghList1, "Item 2", FALSE); + gwinListAddItem(ghList1, "Item 3", FALSE); + gwinListAddItem(ghList1, "Item 4", FALSE); + gwinListAddItem(ghList1, "Item 5", FALSE); + gwinListAddItem(ghList1, "Item 6", FALSE); + gwinListAddItem(ghList1, "Item 7", FALSE); + gwinListAddItem(ghList1, "Item 8", FALSE); + gwinListAddItem(ghList1, "Item 9", FALSE); + gwinListAddItem(ghList1, "Item 10", FALSE); + gwinListAddItem(ghList1, "Item 11", FALSE); + gwinListAddItem(ghList1, "Item 12", FALSE); + gwinListAddItem(ghList1, "Item 13", FALSE); + wi.text = "L2"; wi.g.x += LIST_WIDTH+border; if (wi.g.x + LIST_WIDTH > pagewidth) { wi.g.x = border; wi.g.y += LIST_HEIGHT+border; } + ghList2 = gwinListCreate(0, &wi, TRUE); + gwinListAddItem(ghList2, "Item 0", FALSE); + gwinListAddItem(ghList2, "Item 1", FALSE); + gwinListAddItem(ghList2, "Item 2", FALSE); + gwinListAddItem(ghList2, "Item 3", FALSE); + gwinListAddItem(ghList2, "Item 4", FALSE); + gwinListAddItem(ghList2, "Item 5", FALSE); + gwinListAddItem(ghList2, "Item 6", FALSE); + gwinListAddItem(ghList2, "Item 7", FALSE); + gwinListAddItem(ghList2, "Item 8", FALSE); + gwinListAddItem(ghList2, "Item 9", FALSE); + gwinListAddItem(ghList2, "Item 10", FALSE); + gwinListAddItem(ghList2, "Item 11", FALSE); + gwinListAddItem(ghList2, "Item 12", FALSE); + gwinListAddItem(ghList2, "Item 13", FALSE); + wi.text = "L3"; wi.g.x += LIST_WIDTH+border; if (wi.g.x + LIST_WIDTH > pagewidth) { wi.g.x = border; wi.g.y += LIST_HEIGHT+border; } + ghList3 = gwinListCreate(0, &wi, TRUE); + gwinListAddItem(ghList3, "Item 0", FALSE); + gwinListAddItem(ghList3, "Item 1", FALSE); + gwinListAddItem(ghList3, "Item 2", FALSE); + gwinListAddItem(ghList3, "Item 3", FALSE); + gdispImageOpenFile(&imgYesNo, "image_yesno.gif"); + gwinListItemSetImage(ghList3, 1, &imgYesNo); + gwinListItemSetImage(ghList3, 3, &imgYesNo); + wi.text = "L4"; wi.g.x += LIST_WIDTH+border; if (wi.g.x + LIST_WIDTH > pagewidth) { wi.g.x = border; wi.g.y += LIST_HEIGHT+border; } + ghList4 = gwinListCreate(0, &wi, TRUE); + gwinListAddItem(ghList4, "Item 0", FALSE); + gwinListAddItem(ghList4, "Item 1", FALSE); + gwinListAddItem(ghList4, "Item 2", FALSE); + gwinListAddItem(ghList4, "Item 3", FALSE); + gwinListAddItem(ghList4, "Item 4", FALSE); + gwinListAddItem(ghList4, "Item 5", FALSE); + gwinListAddItem(ghList4, "Item 6", FALSE); + gwinListAddItem(ghList4, "Item 7", FALSE); + gwinListAddItem(ghList4, "Item 8", FALSE); + gwinListAddItem(ghList4, "Item 9", FALSE); + gwinListAddItem(ghList4, "Item 10", FALSE); + gwinListAddItem(ghList4, "Item 11", FALSE); + gwinListAddItem(ghList4, "Item 12", FALSE); + gwinListAddItem(ghList4, "Item 13", FALSE); + gwinListSetScroll(ghList4, scrollSmooth); + + // Image + wi.g.parent = ghPgImages; + wi.g.x = wi.g.y = 0; wi.g.width = pagewidth; wi.g.height = gwinGetInnerHeight(ghPgImages)/2; + ghImage1 = gwinImageCreate(0, &wi.g); + gwinImageOpenFile(ghImage1, "ugfx.gif"); + wi.g.y += wi.g.height; + ghImage2 = gwinImageCreate(0, &wi.g); + gwinImageOpenFile(ghImage2, "chibios.gif"); +} + +/** + * Set the value of the labels + */ +static void setLabels(void) { + char tmp[20]; + + // The sliders + snprintg(tmp, sizeof(tmp), "%d%%", gwinSliderGetPosition(ghSlider1)); + gwinSetText(ghLabelSlider1, tmp, TRUE); + snprintg(tmp, sizeof(tmp), "%d%%", gwinSliderGetPosition(ghSlider2)); + gwinSetText(ghLabelSlider2, tmp, TRUE); + snprintg(tmp, sizeof(tmp), "%d%%", gwinSliderGetPosition(ghSlider3)); + gwinSetText(ghLabelSlider3, tmp, TRUE); + snprintg(tmp, sizeof(tmp), "%d%%", gwinSliderGetPosition(ghSlider4)); + gwinSetText(ghLabelSlider4, tmp, TRUE); + + // The radio buttons + if (gwinRadioIsPressed(ghRadio1)) + gwinSetText(ghLabelRadio1, "Yes", TRUE); + else if (gwinRadioIsPressed(ghRadio2)) + gwinSetText(ghLabelRadio1, "No", TRUE); +} + +/** + * Control the progress bar auto-increment + */ +static void setProgressbar(bool_t onoff) { + if (onoff) + gwinProgressbarStart(ghProgressbar1, 500); + else { + gwinProgressbarStop(ghProgressbar1); // Stop the progress bar + gwinProgressbarReset(ghProgressbar1); + } +} + +/** + * Set the enabled state of every widget (except the tabs etc) + */ +static void setEnabled(bool_t ena) { + //gwinSetEnabled(ghPgControls, ena); + gwinSetEnabled(ghPgSliders, ena); + gwinSetEnabled(ghPgLabels, ena); + gwinSetEnabled(ghPgRadios, ena); + gwinSetEnabled(ghPgLists, ena); + gwinSetEnabled(ghPgImages, ena); + gwinSetEnabled(ghPgBounce, ena); + gwinSetEnabled(ghPgMandelbrot, ena); + // Checkboxes and Buttons we need to do individually so we don't disable the checkbox to re-enable everything + gwinSetEnabled(ghButton1, ena); + gwinSetEnabled(ghButton2, ena); + gwinSetEnabled(ghButton3, ena); + gwinSetEnabled(ghButton4, ena); + gwinSetEnabled(ghCheckbox1, ena); + gwinSetEnabled(ghCheckbox2, ena); + gwinSetEnabled(ghCheckbox3, ena); + //gwinSetEnabled(ghCheckDisableAll, TRUE); +} + +static void FlashOffFn(void *param) { + (void) param; + + gwinNoFlash(ghCheckbox3); +} + +int main(void) { + GEvent * pe; + + // Initialize the display + gfxInit(); + + // Set the widget defaults + font = gdispOpenFont("*"); // Get the first defined font. + gwinSetDefaultFont(font); + gwinSetDefaultStyle(&WhiteWidgetStyle, FALSE); + gdispClear(White); + + // Create the gwin windows/widgets + createWidgets(); + + // Assign toggles and dials to specific buttons & sliders etc. + #if GINPUT_NEED_TOGGLE + gwinAttachToggle(ghButton1, 0, 0); + gwinAttachToggle(ghButton2, 0, 1); + #endif + #if GINPUT_NEED_DIAL + gwinAttachDial(ghSlider1, 0, 0); + gwinAttachDial(ghSlider3, 0, 1); + #endif + + // Make the console visible + gwinShow(ghConsole); + gwinClear(ghConsole); + + // We want to listen for widget events + geventListenerInit(&gl); + gwinAttachListener(&gl); + gtimerInit(&FlashTimer); + + #if !GWIN_NEED_TABSET + // Press the Tab we want visible + gwinRadioPress(ghTabButtons); + #endif + + while(1) { + // Get an Event + pe = geventEventWait(&gl, TIME_INFINITE); + + switch(pe->type) { + case GEVENT_GWIN_BUTTON: + gwinPrintf(ghConsole, "Button %s\n", gwinGetText(((GEventGWinButton *)pe)->gwin)); + break; + + case GEVENT_GWIN_SLIDER: + gwinPrintf(ghConsole, "Slider %s=%d\n", gwinGetText(((GEventGWinSlider *)pe)->gwin), ((GEventGWinSlider *)pe)->position); + break; + + case GEVENT_GWIN_CHECKBOX: + gwinPrintf(ghConsole, "Checkbox %s=%s\n", gwinGetText(((GEventGWinCheckbox *)pe)->gwin), ((GEventGWinCheckbox *)pe)->isChecked ? "Checked" : "UnChecked"); + + // If it is the Disable All checkbox then do that. + if (((GEventGWinCheckbox *)pe)->gwin == ghCheckDisableAll) { + gwinPrintf(ghConsole, "%s All\n", ((GEventGWinCheckbox *)pe)->isChecked ? "Disable" : "Enable"); + setEnabled(!((GEventGWinCheckbox *)pe)->isChecked); + + // If it is the toggle button checkbox start the flash. + } else if (((GEventGWinCheckbox *)pe)->gwin == ghCheckbox3) { + gwinFlash(ghCheckbox3); + gtimerStart(&FlashTimer, FlashOffFn, 0, FALSE, 3000); + } + break; + + case GEVENT_GWIN_LIST: + gwinPrintf(ghConsole, "List %s Item %d %s\n", gwinGetText(((GEventGWinList *)pe)->gwin), ((GEventGWinList *)pe)->item, + gwinListItemIsSelected(((GEventGWinList *)pe)->gwin, ((GEventGWinList *)pe)->item) ? "Selected" : "Unselected"); + break; + + case GEVENT_GWIN_RADIO: + gwinPrintf(ghConsole, "Radio Group %u=%s\n", ((GEventGWinRadio *)pe)->group, gwinGetText(((GEventGWinRadio *)pe)->gwin)); + + switch(((GEventGWinRadio *)pe)->group) { + #if !GWIN_NEED_TABSET + case GROUP_TABS: + + // Set control visibility depending on the tab selected + setTab(((GEventGWinRadio *)pe)->gwin); + + // We show the state of some of the GUI elements here + setProgressbar(((GEventGWinRadio *)pe)->gwin == ghTabProgressbar); + if (((GEventGWinRadio *)pe)->gwin == ghTabLabels) + setLabels(); + break; + #endif + + case GROUP_COLORS: + { + const GWidgetStyle *pstyle; + + gwinPrintf(ghConsole, "Change Color Scheme\n"); + + if (((GEventGWinRadio *)pe)->gwin == ghRadioYellow) + pstyle = &YellowWidgetStyle; + else if (((GEventGWinRadio *)pe)->gwin == ghRadioBlack) + pstyle = &BlackWidgetStyle; + else + pstyle = &WhiteWidgetStyle; + + // Clear the screen to the new color + gdispClear(pstyle->background); + + // Update the style on all controls + gwinSetDefaultStyle(pstyle, TRUE); + } + break; + } + break; + + #if GWIN_NEED_TABSET + case GEVENT_GWIN_TABSET: + gwinPrintf(ghConsole, "TabPage %u (%s)\n", ((GEventGWinTabset *)pe)->nPage, gwinTabsetGetTitle(((GEventGWinTabset *)pe)->ghPage)); + + // We show the state of some of the GUI elements here + setProgressbar(((GEventGWinTabset *)pe)->ghPage == ghPgSliders); + doMandlebrot(ghPgMandelbrot, ((GEventGWinTabset *)pe)->ghPage == ghPgMandelbrot); + doBounce(ghPgBounce, ((GEventGWinTabset *)pe)->ghPage == ghPgBounce); + if (((GEventGWinTabset *)pe)->ghPage == ghPgLabels) + setLabels(); + break; + #endif + + default: + gwinPrintf(ghConsole, "Unknown %d\n", pe->type); + break; + } + } + return 0; +} + diff --git a/demos/applications/combo/mandelbrot.c b/demos/applications/combo/mandelbrot.c new file mode 100644 index 00000000..68ee1fae --- /dev/null +++ b/demos/applications/combo/mandelbrot.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org> + * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the <organization> nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "gfx.h" +#include "tasks.h" + +static volatile bool_t run; +static GHandle gh; +static gfxThreadHandle thread; + +static void mandelbrot(float x1, float y1, float x2, float y2) { + unsigned int i,j, width, height; + uint16_t iter; + float fwidth, fheight; + + float sy = y2 - y1; + float sx = x2 - x1; + const int MAX = 512; + + width = (unsigned int)gwinGetWidth(gh); + height = (unsigned int)gwinGetHeight(gh); + fwidth = width; + fheight = height; + + for(i = 0; i < width; i++) { + for(j = 0; j < height; j++) { + float cy = j * sy / fheight + y1; + float cx = i * sx / fwidth + x1; + float x=0.0f, y=0.0f, xx=0.0f, yy=0.0f; + gfxYield(); + for(iter=0; iter <= MAX && xx+yy<4.0f; iter++) { + xx = x*x; + yy = y*y; + y = 2.0f*x*y + cy; + x = xx - yy + cx; + } + gwinSetColor(gh, RGB2COLOR(iter<<7, iter<<4, iter)); + gwinDrawPixel(gh, i, j); + } + } +} + +static DECLARE_THREAD_FUNCTION(task, param) { + float cx, cy; + float zoom = 1.0f; + (void) param; + + /* where to zoom in */ + cx = -0.086f; + cy = 0.85f; + + while(run) { + mandelbrot(-2.0f*zoom+cx, -1.5f*zoom+cy, 2.0f*zoom+cx, 1.5f*zoom+cy); + + zoom *= 0.7f; + if(zoom <= 0.00001f) + zoom = 1.0f; + } + return 0; +} + +void doMandlebrot(GHandle parent, bool_t start) { + if (start) { + run = TRUE; + gh = parent; + thread = gfxThreadCreate(0, 0x400, LOW_PRIORITY, task, 0); + } else if (run) { + run = FALSE; + gfxThreadWait(thread); + } +} + + diff --git a/demos/applications/combo/readme.txt b/demos/applications/combo/readme.txt new file mode 100644 index 00000000..b5777061 --- /dev/null +++ b/demos/applications/combo/readme.txt @@ -0,0 +1,8 @@ +This demo supports input from both a mouse/touch, toggles and/or a dial input. +If your platform does not support one or the other, turn it off in +gfxconf.h + +Note that you will need to include the drivers into your project +makefile for whichever inputs you decide to use. + +For some fun have a play with the "colors" radio group and the "Disable All" checkbox. diff --git a/demos/applications/combo/romfs_files.h b/demos/applications/combo/romfs_files.h new file mode 100644 index 00000000..5b6aecd8 --- /dev/null +++ b/demos/applications/combo/romfs_files.h @@ -0,0 +1,9 @@ +/** + * This file contains the list of files for the ROMFS. + * + * The files have been converted using... + * file2c -dbcs infile outfile + */ +#include "romfs_img_ugfx.h" +#include "romfs_img_yesno.h" +#include "romfs_img_chibios.h" diff --git a/demos/applications/combo/romfs_img_chibios.h b/demos/applications/combo/romfs_img_chibios.h new file mode 100644 index 00000000..342e3b68 --- /dev/null +++ b/demos/applications/combo/romfs_img_chibios.h @@ -0,0 +1,317 @@ +/** + * This file was generated from "chibios.gif" using... + * + * file2c -dcsn image_chibios chibios.gif + * + */ +static const char image_chibios[] = { + 0x47, 0x49, 0x46, 0x38, 0x39, 0x61, 0x5A, 0x00, 0x5A, 0x00, 0xE7, 0xFF, 0x00, 0x09, 0x0E, 0x06, + 0x06, 0x0E, 0x3D, 0x0F, 0x0F, 0x1A, 0x06, 0x12, 0x2B, 0x0A, 0x1A, 0x00, 0x14, 0x2A, 0x04, 0x48, + 0x1D, 0x0E, 0x1D, 0x34, 0x00, 0x33, 0x31, 0x35, 0x19, 0x3E, 0x03, 0x11, 0x36, 0x70, 0x13, 0x33, + 0x95, 0x1C, 0x3E, 0x3A, 0x52, 0x2F, 0x30, 0x00, 0x49, 0x22, 0x00, 0x41, 0x72, 0x26, 0x47, 0x01, + 0x20, 0x4A, 0x01, 0x00, 0x49, 0x6A, 0x3C, 0x3D, 0x50, 0x00, 0x53, 0x2E, 0x74, 0x31, 0x2F, 0x03, + 0x50, 0x4C, 0x03, 0x56, 0x19, 0x2E, 0x46, 0x3C, 0x0E, 0x4A, 0x75, 0x23, 0x44, 0x86, 0x00, 0x55, + 0x48, 0x01, 0x56, 0x3C, 0x03, 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0x00, 0x0D, 0x94, 0x81, 0x46, 0xCD, 0x30, + 0x0A, 0x41, 0x0B, 0x17, 0xB2, 0x90, 0x08, 0xF3, 0x2B, 0x71, 0xBC, 0x10, 0x12, 0x88, 0x0A, 0x0C, + 0xBE, 0xA0, 0x09, 0x8E, 0x70, 0xBE, 0xAB, 0xE0, 0xBD, 0x0A, 0xD1, 0x0A, 0xFB, 0xF1, 0xB5, 0xFA, + 0xA3, 0x08, 0xCB, 0x20, 0x37, 0xD4, 0x1B, 0x11, 0x29, 0x2B, 0x0D, 0xC8, 0x9B, 0x0E, 0x4D, 0xCB, + 0xB7, 0x12, 0xF1, 0x0A, 0x45, 0x91, 0xC1, 0x11, 0x71, 0x08, 0x99, 0x70, 0xAF, 0x69, 0x62, 0x5F, + 0xB7, 0x00, 0xBB, 0x17, 0x41, 0xBD, 0x18, 0x22, 0xBF, 0x4A, 0x11, 0x54, 0xB9, 0x81, 0xB7, 0x55, + 0x3A, 0x12, 0xC9, 0xD0, 0x0B, 0x27, 0x3C, 0x10, 0xC3, 0x30, 0x27, 0xB2, 0x51, 0xBB, 0x2F, 0x5C, + 0xC3, 0xFF, 0x90, 0x0E, 0x5D, 0xCB, 0xB1, 0x03, 0x71, 0x8F, 0x2E, 0x6C, 0xC3, 0x39, 0x81, 0x21, + 0xAD, 0xB5, 0xBF, 0xFF, 0xA0, 0x9D, 0xBB, 0x20, 0xC4, 0x3E, 0x4C, 0x12, 0xA8, 0xD6, 0x0D, 0x06, + 0xFC, 0x0D, 0xCD, 0x20, 0x0B, 0x37, 0x71, 0xC4, 0x3E, 0x9C, 0x46, 0xE0, 0xF0, 0xC0, 0x50, 0xAC, + 0x14, 0xAA, 0x52, 0xC5, 0x58, 0x9C, 0xC5, 0x5A, 0xBC, 0xC5, 0x5C, 0xDC, 0xC5, 0x5E, 0xFC, 0xC5, + 0x60, 0x1C, 0xC6, 0x02, 0x11, 0x10, 0x00, 0x3B, +}; + +#ifdef ROMFS_DIRENTRY_HEAD + static const ROMFS_DIRENTRY image_chibios_dir = { 0, 0, ROMFS_DIRENTRY_HEAD, "chibios.gif", 4840, image_chibios }; + #undef ROMFS_DIRENTRY_HEAD + #define ROMFS_DIRENTRY_HEAD &image_chibios_dir +#endif diff --git a/demos/applications/combo/romfs_img_ugfx.h b/demos/applications/combo/romfs_img_ugfx.h new file mode 100644 index 00000000..cfbd1026 --- /dev/null +++ b/demos/applications/combo/romfs_img_ugfx.h @@ -0,0 +1,304 @@ +/** + * This file was generated from "romfs_img_ugfx.gif" using... + * + * file2c -dcs romfs_img_ugfx.gif romfs_img_ugfx.h + * + */ +static const char romfs_img_ugfx[] = { + 0x47, 0x49, 0x46, 0x38, 0x39, 0x61, 0xAE, 0x00, 0x32, 0x00, 0xE7, 0xFF, 0x00, 0x16, 0x00, 0xFF, + 0x0E, 0x30, 0x52, 0x03, 0x34, 0x55, 0x08, 0x37, 0x59, 0x16, 0x35, 0x58, 0x0E, 0x3A, 0x5C, 0x02, + 0x3E, 0x64, 0x13, 0x3B, 0x63, 0x07, 0x3D, 0x76, 0x1C, 0x3A, 0x5D, 0x18, 0x3C, 0x70, 0x21, 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0x82, 0xD0, 0x0D, 0x2F, 0xD6, 0x0E, + 0xFE, 0xD0, 0x0F, 0x7D, 0xB6, 0x95, 0x3C, 0x7A, 0x0A, 0x60, 0x54, 0x44, 0xB5, 0xF0, 0x25, 0x96, + 0x7A, 0xA9, 0x44, 0xFA, 0x63, 0x43, 0x16, 0x26, 0x13, 0xA6, 0x00, 0x12, 0xA0, 0x05, 0xA7, 0x80, + 0x9F, 0x4A, 0x06, 0x29, 0xCF, 0x60, 0x09, 0x52, 0xE0, 0x08, 0x93, 0x42, 0x0D, 0x6B, 0x89, 0x04, + 0xBC, 0x90, 0x29, 0xB5, 0x39, 0x96, 0xE4, 0x00, 0x0E, 0xD4, 0xE0, 0x8D, 0x10, 0x81, 0x05, 0x07, + 0xA2, 0x20, 0x0F, 0x04, 0x92, 0x18, 0xF2, 0x05, 0xD4, 0x90, 0x0E, 0x6C, 0x4A, 0x92, 0x19, 0xB4, + 0x5B, 0xF8, 0x68, 0x7C, 0xE3, 0x79, 0x0C, 0xA0, 0x80, 0x5D, 0x2A, 0xA6, 0x03, 0x75, 0x26, 0x03, + 0xE9, 0xC9, 0x04, 0x9F, 0xC0, 0x0F, 0x8E, 0x5A, 0x0F, 0xEC, 0xE0, 0x0D, 0x4E, 0x42, 0x91, 0x99, + 0x40, 0x0B, 0xAE, 0x42, 0x3E, 0x70, 0xD2, 0x0A, 0x8A, 0x26, 0x06, 0x1B, 0x20, 0x05, 0x73, 0xD0, + 0x07, 0xD4, 0x27, 0x06, 0x2F, 0xF0, 0x00, 0x0A, 0xA0, 0x01, 0x46, 0x20, 0x05, 0xEA, 0x6A, 0x04, + 0x71, 0xB8, 0x87, 0x05, 0xD1, 0x14, 0x13, 0xA0, 0x01, 0x33, 0x60, 0x04, 0x62, 0x10, 0x2C, 0x52, + 0x60, 0x04, 0x33, 0x20, 0x01, 0x66, 0xB8, 0x01, 0x33, 0xD0, 0xAF, 0x33, 0x40, 0x2C, 0x2F, 0xE0, + 0xAF, 0x02, 0x3B, 0xB0, 0xFE, 0xCA, 0x86, 0x06, 0x21, 0xB0, 0x41, 0x90, 0xB0, 0x0A, 0xAB, 0xB0, + 0x08, 0x15, 0xB0, 0x33, 0xA0, 0xB0, 0x35, 0x10, 0xB1, 0x12, 0x3B, 0xB1, 0x29, 0x40, 0x8E, 0x0A, + 0xF1, 0x03, 0x68, 0x50, 0x0C, 0xAF, 0x10, 0x67, 0x76, 0xE0, 0x04, 0x37, 0x10, 0x24, 0x32, 0xC4, + 0x05, 0x78, 0x56, 0x84, 0x7B, 0x56, 0x0F, 0xE9, 0xA0, 0x0D, 0x5D, 0xB9, 0x08, 0x96, 0xA0, 0x68, + 0xA1, 0xE0, 0xFE, 0xA3, 0x0A, 0x51, 0x06, 0x84, 0x80, 0x44, 0x99, 0x00, 0x04, 0x9C, 0xA6, 0x60, + 0x99, 0x26, 0x1B, 0x9B, 0x06, 0x21, 0x94, 0x16, 0x6A, 0xB4, 0xF1, 0x50, 0x3C, 0x6B, 0xB3, 0x3C, + 0xAB, 0x93, 0x3F, 0x10, 0x09, 0xA0, 0x70, 0x5D, 0x6D, 0x00, 0x48, 0x41, 0x42, 0x01, 0x14, 0x70, + 0x01, 0x44, 0x02, 0x03, 0x68, 0x20, 0x5E, 0xEC, 0x00, 0x1F, 0xB5, 0x32, 0x7D, 0x99, 0x90, 0x6B, + 0x44, 0x94, 0x5E, 0x62, 0xE0, 0x6B, 0x84, 0x70, 0x08, 0xB8, 0x29, 0x70, 0x5E, 0x7B, 0x11, 0x28, + 0xB0, 0x04, 0xA9, 0xC0, 0x08, 0xC7, 0x36, 0x05, 0x44, 0xD0, 0x02, 0x8B, 0x17, 0x45, 0x7E, 0x70, + 0x68, 0x32, 0xA0, 0x0A, 0xF0, 0x60, 0x63, 0xCC, 0xB0, 0x09, 0x8D, 0xC0, 0x07, 0xBD, 0xA6, 0x6B, + 0x14, 0x11, 0x03, 0xBD, 0x36, 0x4F, 0x7D, 0x20, 0x02, 0xB6, 0xF8, 0xB5, 0x7E, 0x3B, 0x94, 0x68, + 0xC0, 0x09, 0x84, 0x10, 0x85, 0xB4, 0x04, 0x02, 0xD0, 0x45, 0x10, 0x21, 0xF0, 0x03, 0xD2, 0x00, + 0xB7, 0xB5, 0xC2, 0x07, 0x7D, 0x20, 0x0A, 0x57, 0x5B, 0x11, 0x13, 0xF0, 0x02, 0x2F, 0x30, 0x01, + 0x7D, 0xFB, 0xB7, 0x98, 0x0B, 0x11, 0x2C, 0x20, 0x09, 0x84, 0xC0, 0x06, 0x55, 0xD0, 0x03, 0x38, + 0xB0, 0x05, 0x90, 0x40, 0x6F, 0xC7, 0x85, 0x06, 0xE1, 0x00, 0x1F, 0x72, 0xDB, 0x9A, 0x0E, 0xA9, + 0x11, 0x3D, 0x9B, 0xB9, 0xAE, 0x6B, 0x10, 0x2C, 0xB0, 0x04, 0xE7, 0x52, 0x45, 0x90, 0x40, 0x0B, + 0xA2, 0xF2, 0x09, 0x4D, 0x12, 0x59, 0xAE, 0xF9, 0xBA, 0xBC, 0x7B, 0x2D, 0x2C, 0xF0, 0x06, 0x60, + 0x90, 0x07, 0xA5, 0x20, 0x6E, 0x0A, 0x11, 0x3C, 0xBB, 0xE0, 0x0B, 0xBA, 0x20, 0x9A, 0xBD, 0xBB, + 0xBC, 0xD6, 0xA2, 0x02, 0x6F, 0x40, 0xBC, 0x12, 0xA1, 0x02, 0x7D, 0xCA, 0xBC, 0xD4, 0x9B, 0x11, + 0x01, 0x01, 0x01, 0x00, 0x3B, +}; + +#ifdef ROMFS_DIRENTRY_HEAD + static const ROMFS_DIRENTRY romfs_img_ugfx_dir = { 0, 0, ROMFS_DIRENTRY_HEAD, "ugfx.gif", 4629, romfs_img_ugfx }; + #undef ROMFS_DIRENTRY_HEAD + #define ROMFS_DIRENTRY_HEAD &romfs_img_ugfx_dir +#endif diff --git a/demos/applications/combo/romfs_img_yesno.h b/demos/applications/combo/romfs_img_yesno.h new file mode 100644 index 00000000..6b2c1290 --- /dev/null +++ b/demos/applications/combo/romfs_img_yesno.h @@ -0,0 +1,27 @@ +/** + * This file was generated from "image_yesno.gif" using... + * + * file2c -dcs image_yesno.gif romfs_img_yesno.h + * + */ +static const char image_yesno[] = { + 0x47, 0x49, 0x46, 0x38, 0x39, 0x61, 0x0B, 0x00, 0x2C, 0x00, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xC6, 0x00, 0xC6, 0xFF, 0xC6, 0xCE, 0xFF, 0xCE, 0xFF, 0x08, 0x18, 0xFF, 0xCE, 0xDE, 0xFF, + 0xDE, 0xDE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x21, 0xF9, 0x04, + 0x03, 0x00, 0x00, 0x0F, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x2C, 0x00, 0x00, 0x04, + 0x77, 0xF0, 0xC9, 0x49, 0x03, 0xBD, 0xC1, 0xDE, 0x97, 0x83, 0xD8, 0xD9, 0xB7, 0x71, 0x22, 0xA8, + 0x8D, 0x59, 0x55, 0x7A, 0x55, 0x2A, 0x9C, 0x6D, 0x8A, 0xC2, 0x23, 0x45, 0xDC, 0x84, 0x61, 0xE7, + 0x12, 0xDE, 0x13, 0x1B, 0x1C, 0x70, 0xE4, 0x0B, 0x02, 0x6F, 0x17, 0xE4, 0xC3, 0x30, 0xFC, 0xED, + 0x24, 0xCC, 0x0B, 0x53, 0xA7, 0x7C, 0x36, 0x93, 0xD7, 0xCD, 0xA0, 0xF6, 0x18, 0x6C, 0xB5, 0xDE, + 0x03, 0x58, 0x3C, 0x1A, 0x90, 0xC1, 0x5C, 0x2F, 0xC5, 0x3C, 0x61, 0xB7, 0xD5, 0x87, 0xEF, 0xC5, + 0xAB, 0x2E, 0xCB, 0xB9, 0x93, 0x82, 0xBE, 0x70, 0x7E, 0xE8, 0xC9, 0x7B, 0x12, 0x7A, 0x1B, 0x7B, + 0x05, 0x35, 0x81, 0x84, 0x86, 0x83, 0x14, 0x8B, 0x07, 0x86, 0x79, 0x8F, 0x82, 0x8F, 0x8E, 0x17, + 0x8E, 0x62, 0x8B, 0x8C, 0x8A, 0x87, 0x05, 0x11, 0x00, 0x3B, +}; + +#ifdef ROMFS_DIRENTRY_HEAD + static const ROMFS_DIRENTRY image_yesno_dir = { 0, 0, ROMFS_DIRENTRY_HEAD, "image_yesno.gif", 202, image_yesno }; + #undef ROMFS_DIRENTRY_HEAD + #define ROMFS_DIRENTRY_HEAD &image_yesno_dir +#endif diff --git a/demos/applications/combo/rsc/chibios.gif b/demos/applications/combo/rsc/chibios.gif Binary files differnew file mode 100644 index 00000000..96d55ba4 --- /dev/null +++ b/demos/applications/combo/rsc/chibios.gif diff --git a/demos/applications/combo/rsc/image_yesno.gif b/demos/applications/combo/rsc/image_yesno.gif Binary files differnew file mode 100644 index 00000000..5a3d3998 --- /dev/null +++ b/demos/applications/combo/rsc/image_yesno.gif diff --git a/demos/applications/combo/rsc/romfs_img_ugfx.gif b/demos/applications/combo/rsc/romfs_img_ugfx.gif Binary files differnew file mode 100644 index 00000000..89aa28fa --- /dev/null +++ b/demos/applications/combo/rsc/romfs_img_ugfx.gif diff --git a/demos/applications/combo/tasks.h b/demos/applications/combo/tasks.h new file mode 100644 index 00000000..68a32e09 --- /dev/null +++ b/demos/applications/combo/tasks.h @@ -0,0 +1,7 @@ +#ifndef _TASKS_INCLUDED +#define _TASKS_INCLUDED + +void doMandlebrot(GHandle parent, bool_t start); +void doBounce(GHandle parent, bool_t start); + +#endif diff --git a/docs/releases.txt b/docs/releases.txt index 7c49f185..c4e1073e 100644 --- a/docs/releases.txt +++ b/docs/releases.txt @@ -10,14 +10,14 @@ FEATURE: New board STM32F746G-Discovery FEATURE: New gdisp driver STM32LTDC FEATURE: Better support for Raw32 platforms FEATURE: Renaming GFX_NO_OS_INIT to GFX_OS_NO_INIT -FEATURE: Implementing widget focusing. See gwinSetFocus() and gwinGetFocus() +FEATURE: New demo applications/combo FEATURE: Adding more font metrics (BaselineX and BaselineY) FEATURE: Adding gdispGetStringWidthCount() +FEATURE: Implementing widget focusing. See gwinSetFocus() and gwinGetFocus() FEATURE: Adding TextEdit widget FEATURE: Added color to widget style for focused widgets FEATURE: Added GWIN_FOCUS_HIGHLIGHT_WIDTH as an option in the configuration file - *** Release 2.3 *** FEATURE: Added more events to the slider widget FIX: Clean up visibility issues diff --git a/drivers/gdisp/STM32LTDC/gdisp_lld_config.h b/drivers/gdisp/STM32LTDC/gdisp_lld_config.h index c661f67c..846fc1f0 100644 --- a/drivers/gdisp/STM32LTDC/gdisp_lld_config.h +++ b/drivers/gdisp/STM32LTDC/gdisp_lld_config.h @@ -14,7 +14,7 @@ /* Driver hardware support. */ /*===========================================================================*/ -#define LTDC_USE_DMA2D TRUE +#define LTDC_USE_DMA2D FALSE // Currently has display artifacts #define GDISP_HARDWARE_DRAWPIXEL TRUE #define GDISP_HARDWARE_PIXELREAD TRUE #define GDISP_HARDWARE_CONTROL TRUE diff --git a/src/gdisp/gdisp_image_gif.c b/src/gdisp/gdisp_image_gif.c index d5c6b3ca..88dac4c8 100644 --- a/src/gdisp/gdisp_image_gif.c +++ b/src/gdisp/gdisp_image_gif.c @@ -687,6 +687,7 @@ gdispImageError gdispImageCache_GIF(gdispImage *img) { // Check for interlacing cnt = 0; + q = 0; if (cache->frame.flags & GIFL_INTERLACE) { // Every 8th row starting at row 0 for(p=cache->imagebits, my=0; my < cache->frame.height; my+=8, p += cache->frame.width*7) { diff --git a/src/gos/gos_chibios.c b/src/gos/gos_chibios.c index eb839dc6..d650caa0 100644 --- a/src/gos/gos_chibios.c +++ b/src/gos/gos_chibios.c @@ -158,13 +158,13 @@ gfxThreadHandle gfxThreadCreate(void *stackarea, size_t stacksz, threadpriority_ { if (!stackarea) { if (!stacksz) stacksz = 256; - return chThdCreateFromHeap(0, stacksz, prio, fn, param); + return chThdCreateFromHeap(0, stacksz, prio, (tfunc_t)fn, param); } if (!stacksz) return 0; - return chThdCreateStatic(stackarea, stacksz, prio, fn, param); + return chThdCreateStatic(stackarea, stacksz, prio, (tfunc_t)fn, param); } #endif /* GFX_USE_OS_CHIBIOS */ diff --git a/src/gos/gos_raw32.h b/src/gos/gos_raw32.h index 0fca9223..2937e52b 100644 --- a/src/gos/gos_raw32.h +++ b/src/gos/gos_raw32.h @@ -33,6 +33,13 @@ typedef unsigned char bool_t; #if __STDC_VERSION__ >= 199901L #include <stdint.h> +#elif defined(__GNUC__) || defined(__GNUG__) + typedef __INT8_TYPE__ int8_t; + typedef __UINT8_TYPE__ uint8_t; + typedef __INT16_TYPE__ int16_t; + typedef __UINT16_TYPE__ uint16_t; + typedef __INT32_TYPE__ int32_t; + typedef __UINT32_TYPE__ uint32_t; #else typedef signed char int8_t; typedef unsigned char uint8_t; diff --git a/tools/gmake_scripts/cpu_stm32m4.mk b/tools/gmake_scripts/cpu_stm32m4.mk index 5acfe8ad..1e205eb6 100644 --- a/tools/gmake_scripts/cpu_stm32m4.mk +++ b/tools/gmake_scripts/cpu_stm32m4.mk @@ -14,11 +14,11 @@ # NONE # -#SRCFLAGS += -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -falign-functions=16 -#LDFLAGS += -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -falign-functions=16 -#DEFS += CORTEX_USE_FPU=TRUE -#LIBS += m -SRCFLAGS += -mcpu=cortex-m4 -falign-functions=16 -LDFLAGS += -mcpu=cortex-m4 -DEFS += CORTEX_USE_FPU=FALSE +SRCFLAGS += -mcpu=cortex-m4 -falign-functions=16 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant +LDFLAGS += -mcpu=cortex-m4 -falign-functions=16 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant +DEFS += CORTEX_USE_FPU=TRUE USE_FPU=hard +LIBS += m +#SRCFLAGS += -mcpu=cortex-m4 -falign-functions=16 +#LDFLAGS += -mcpu=cortex-m4 +#DEFS += CORTEX_USE_FPU=FALSE diff --git a/tools/gmake_scripts/cpu_stm32m7.mk b/tools/gmake_scripts/cpu_stm32m7.mk index 0a59e24f..78e1cc4e 100644 --- a/tools/gmake_scripts/cpu_stm32m7.mk +++ b/tools/gmake_scripts/cpu_stm32m7.mk @@ -13,12 +13,7 @@ # # NONE # - -#SRCFLAGS += -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -falign-functions=16 -#LDFLAGS += -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -falign-functions=16 -#DEFS += CORTEX_USE_FPU=TRUE -#LIBS += m -SRCFLAGS += -mcpu=cortex-m7 -falign-functions=16 -LDFLAGS += -mcpu=cortex-m7 -DEFS += CORTEX_USE_FPU=FALSE - +SRCFLAGS += -mcpu=cortex-m7 -falign-functions=16 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant +LDFLAGS += -mcpu=cortex-m7 -falign-functions=16 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant +DEFS += CORTEX_USE_FPU=TRUE USE_FPU=hard +LIBS += m
\ No newline at end of file |
