More STM32F746-Discovery changes.

12 files changed, 238 insertions, 3411 deletions

diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk
index d12b4016..71d820ca 100644
--- a/boards/base/STM32F746-Discovery/board.mk
+++ b/boards/base/STM32F746-Discovery/board.mk
@@ -1,29 +1,22 @@
 GFXINC  +=	$(GFXLIB)/boards/base/STM32F746-Discovery \
 			$(STMHAL)/Inc
 GFXSRC  +=	$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \
-			$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c \
 			$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7_i2c.c
-
+				
 ifeq ($(OPT_OS),raw32)
-	HAL      =  $(STMHAL)
 	GFXDEFS +=	STM32F746xx
-	GFXSRC	+=	$(HAL)/Src/stm32f7xx_hal.c \
-				$(HAL)/Src/stm32f7xx_hal_cortex.c \
-				$(HAL)/Src/stm32f7xx_hal_flash.c \
-				$(HAL)/Src/stm32f7xx_hal_flash_ex.c \
-				$(HAL)/Src/stm32f7xx_hal_rcc.c \
-				$(HAL)/Src/stm32f7xx_hal_rcc_ex.h \
-				$(HAL)/Src/stm32f7xx_hal_gpio.c \
-				$(HAL)/Src/stm32f7xx_hal_pwr.c \
-				$(HAL)/Src/stm32f7xx_hal_pwr_ex.c \
-				$(HAL)/Src/stm32f7xx_hal_sdram.c \
-				$(HAL)/Src/stm32f7xx_hal_dma.c
+	GFXSRC	+=	$(STMHAL)/Src/stm32f7xx_hal.c \
+				$(STMHAL)/Src/stm32f7xx_hal_cortex.c \
+				$(STMHAL)/Src/stm32f7xx_hal_rcc.c \
+				$(STMHAL)/Src/stm32f7xx_hal_rcc_ex.h \
+				$(STMHAL)/Src/stm32f7xx_hal_gpio.c \
+				$(STMHAL)/Src/stm32f7xx_hal_pwr.c \
+				$(STMHAL)/Src/stm32f7xx_hal_pwr_ex.c
 	GFXSRC	+=	$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s \
 				$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c \
 				$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c \
 				$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c
 	GFXDEFS	+=	GFX_OS_EXTRA_INIT_FUNCTION=Raw32OSInit GFX_OS_INIT_NO_WARNING=TRUE
-	SRCFLAGS+=	-std=c99
 	GFXINC	+=	$(CMSIS)/Device/ST/STM32F7xx/Include \
 				$(CMSIS)/Include \
 				$(STMHAL)/Inc
diff --git a/boards/base/STM32F746-Discovery/board_STM32LTDC.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h
index 1bf3dec8..f5011d4c 100644
--- a/boards/base/STM32F746-Discovery/board_STM32LTDC.h
+++ b/boards/base/STM32F746-Discovery/board_STM32LTDC.h
@@ -8,8 +8,9 @@
 #ifndef _GDISP_LLD_BOARD_H
 #define _GDISP_LLD_BOARD_H
 
-#include "stm32f7xx_ll_fmc.h"
 #include "stm32f746g_discovery_sdram.h"
+#include "stm32f7xx_hal_rcc.h"
+#include "stm32f7xx_hal_gpio.h"
 #include <string.h>
 
 #if !GFX_USE_OS_CHIBIOS
diff --git a/boards/base/STM32F746-Discovery/example_chibios3/Makefile b/boards/base/STM32F746-Discovery/example_chibios3/Makefile
index d7414ef2..c265cada 100644
--- a/boards/base/STM32F746-Discovery/example_chibios3/Makefile
+++ b/boards/base/STM32F746-Discovery/example_chibios3/Makefile
@@ -55,7 +55,8 @@ LDFLAGS  =
 SRC      = 
 
 OBJS     =
-DEFS     = GFX_OS_HEAP_SIZE=40960
+#DEFS     = GFX_OS_HEAP_SIZE=40960
+DEFS     = 
 LIBS     =
 INCPATH  = 
 
diff --git a/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h b/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h
index 765e1377..40ebe103 100644
--- a/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h
+++ b/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h
@@ -65,7 +65,7 @@
 /* #define HAL_NAND_MODULE_ENABLED */
 /* #define HAL_NOR_MODULE_ENABLED */
 /* #define HAL_SRAM_MODULE_ENABLED */
-#define HAL_SDRAM_MODULE_ENABLED
+//#define HAL_SDRAM_MODULE_ENABLED
 /* #define HAL_HASH_MODULE_ENABLED   */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_I2C_MODULE_ENABLED */
diff --git a/boards/base/STM32F746-Discovery/example_raw32/Makefile b/boards/base/STM32F746-Discovery/example_raw32/Makefile
index b0f8344a..c6540bba 100644
--- a/boards/base/STM32F746-Discovery/example_raw32/Makefile
+++ b/boards/base/STM32F746-Discovery/example_raw32/Makefile
@@ -56,6 +56,7 @@ SRC      =
 
 OBJS     =
 DEFS     = GFX_OS_HEAP_SIZE=40960
+#DEFS     = 
 LIBS     =
 INCPATH  = 
 
diff --git a/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h
index 765e1377..40ebe103 100644
--- a/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h
+++ b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h
@@ -65,7 +65,7 @@
 /* #define HAL_NAND_MODULE_ENABLED */
 /* #define HAL_NOR_MODULE_ENABLED */
 /* #define HAL_SRAM_MODULE_ENABLED */
-#define HAL_SDRAM_MODULE_ENABLED
+//#define HAL_SDRAM_MODULE_ENABLED
 /* #define HAL_HASH_MODULE_ENABLED   */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_I2C_MODULE_ENABLED */
diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c
index 6f921492..66475b8f 100644
--- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c
+++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c
@@ -1,152 +1,47 @@
-/**
-  ******************************************************************************
-  * @file    stm32746g_discovery_sdram.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    25-June-2015
-  * @brief   This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory 
-  *          device mounted on STM32746G-Discovery board.
-  @verbatim
-   1. How To use this driver:
-   --------------------------
-      - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
-        on STM32746G-Discovery board.
-      - This driver does not need a specific component driver for the SDRAM device
-        to be included with.
-   
-   2. Driver description:
-   ---------------------
-     + Initialization steps:
-        o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This 
-          function includes the MSP layer hardware resources initialization and the
-          FMC controller configuration to interface with the external SDRAM memory.
-        o It contains the SDRAM initialization sequence to program the SDRAM external 
-          device using the function BSP_SDRAM_Initialization_sequence(). Note that this 
-          sequence is standard for all SDRAM devices, but can include some differences
-          from a device to another. If it is the case, the right sequence should be 
-          implemented separately.
-     
-     + SDRAM read/write operations
-        o SDRAM external memory can be accessed with read/write operations once it is
-          initialized.
-          Read/write operation can be performed with AHB access using the functions
-          BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
-          BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
-        o The AHB access is performed with 32-bit width transaction, the DMA transfer
-          configuration is fixed at single (no burst) word transfer (see the 
-          SDRAM_MspInit() static function).
-        o User can implement his own functions for read/write access with his desired 
-          configurations.
-        o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
-          is called in IRQ handler file, to serve the generated interrupt once the DMA 
-          transfer is complete.
-        o You can send a command to the SDRAM device in runtime using the function 
-          BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between 
-          the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. 
- 
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
 #include "gfx.h"
 #include "stm32f746g_discovery_sdram.h"
 #include "stm32f7xx_hal_rcc.h"
-#include "stm32f7xx_hal_rcc_ex.h"
-#include "stm32f7xx_hal_cortex.h"
-
-#if GFX_USE_OS_CHIBIOS
-	#define HAL_GPIO_Init(port, ptr)	palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
-#endif
-
-/** @addtogroup BSP
-  * @{
-  */
-
-/** @addtogroup STM32746G_DISCOVERY
-  * @{
-  */ 
-  
-/** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM
-  * @{
-  */ 
-
-/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions
-  * @{
-  */ 
-/**
-  * @}
-  */
-
-/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines
-  * @{
-  */
-/**
-  * @}
-  */
-
-/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros
-  * @{
-  */  
-/**
-  * @}
-  */
-
-/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables
-  * @{
-  */       
-static SDRAM_HandleTypeDef sdramHandle;
-static FMC_SDRAM_TimingTypeDef Timing;
-static FMC_SDRAM_CommandTypeDef Command;
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes
-  * @{
-  */ 
-/**
-  * @}
-  */
-    
-/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions
-  * @{
-  */ 
-
-static HAL_StatusTypeDef _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
+#include "stm32f7xx_hal_dma.h"
+#include "stm32f7xx_hal_gpio.h"
+#include "stm32f7xx_hal_sdram.h"
+
+#define SDRAM_MEMORY_WIDTH               FMC_SDRAM_MEM_BUS_WIDTH_16
+#define SDCLOCK_PERIOD                   FMC_SDRAM_CLOCK_PERIOD_2
+#define REFRESH_COUNT                    ((uint32_t)0x0603)   /* SDRAM refresh counter (100Mhz SD clock) */
+#define SDRAM_TIMEOUT                    ((uint32_t)0xFFFF)
+
+/* DMA definitions for SDRAM DMA transfer */
+#define __DMAx_CLK_ENABLE                 __HAL_RCC_DMA2_CLK_ENABLE
+#define SDRAM_DMAx_CHANNEL                DMA_CHANNEL_0
+#define SDRAM_DMAx_STREAM                 DMA2_Stream0
+#define SDRAM_DMAx_IRQn                   DMA2_Stream0_IRQn
+
+/* FMC SDRAM Mode definition register defines */
+#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
+
+static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshCount);
+static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram);
+static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
+static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
+static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
+static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
+
+static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
 {
   /* Check the SDRAM handle parameter */
   if(hsdram == NULL)
-  {
-    return HAL_ERROR;
-  }
+    return;
 
   if(hsdram->State == HAL_SDRAM_STATE_RESET)
   {
@@ -158,27 +53,127 @@ static HAL_StatusTypeDef _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_
   hsdram->State = HAL_SDRAM_STATE_BUSY;
 
   /* Initialize SDRAM control Interface */
-  FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
+  _FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
 
   /* Initialize SDRAM timing Interface */
-  FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
+  _FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
 
   /* Update the SDRAM controller state */
   hsdram->State = HAL_SDRAM_STATE_READY;
+}
+
+static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
+{
+  uint32_t tmpr1 = 0;
+  uint32_t tmpr2 = 0;
+
+  /* Set SDRAM bank configuration parameters */
+  if (Init->SDBank != FMC_SDRAM_BANK2)
+  {
+    tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
+
+    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+    tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+                         FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+                         FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+    tmpr1 |= (uint32_t)(Init->ColumnBitsNumber   |\
+                        Init->RowBitsNumber      |\
+                        Init->MemoryDataWidth    |\
+                        Init->InternalBankNumber |\
+                        Init->CASLatency         |\
+                        Init->WriteProtection    |\
+                        Init->SDClockPeriod      |\
+                        Init->ReadBurst          |\
+                        Init->ReadPipeDelay
+                        );
+    Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
+  }
+  else /* FMC_Bank2_SDRAM */
+  {
+    tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
+
+    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+    tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+    tmpr1 |= (uint32_t)(Init->SDClockPeriod      |\
+                        Init->ReadBurst          |\
+                        Init->ReadPipeDelay);
+
+    tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
+
+    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+    tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+    tmpr2 |= (uint32_t)(Init->ColumnBitsNumber   |\
+                       Init->RowBitsNumber      |\
+                       Init->MemoryDataWidth    |\
+                       Init->InternalBankNumber |\
+                       Init->CASLatency         |\
+                       Init->WriteProtection);
+
+    Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
+    Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
+  }
 
   return HAL_OK;
 }
 
-static HAL_StatusTypeDef _HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
+static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
 {
-  /* Configure the SDRAM registers with their reset values */
-  FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
+  uint32_t tmpr1 = 0;
+  uint32_t tmpr2 = 0;
 
-  /* Reset the SDRAM controller state */
-  hsdram->State = HAL_SDRAM_STATE_RESET;
+  /* Set SDRAM device timing parameters */
+  if (Bank != FMC_SDRAM_BANK2)
+  {
+    tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsdram);
+    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+                          FMC_SDTR1_TRCD));
+
+    tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
+                       (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
+                       (((Timing->SelfRefreshTime)-1) << 8)      |\
+                       (((Timing->RowCycleDelay)-1) << 12)       |\
+                       (((Timing->WriteRecoveryTime)-1) <<16)    |\
+                       (((Timing->RPDelay)-1) << 20)             |\
+                       (((Timing->RCDDelay)-1) << 24));
+    Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
+  }
+  else /* FMC_Bank2_SDRAM */
+  {
+    tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
+
+    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+                          FMC_SDTR1_TRCD));
+
+    tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
+                       (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
+                       (((Timing->SelfRefreshTime)-1) << 8)      |\
+                       (((Timing->WriteRecoveryTime)-1) <<16)    |\
+                       (((Timing->RCDDelay)-1) << 24));
+
+    tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
+
+    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+    tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+                          FMC_SDTR1_TRCD));
+    tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12)       |\
+                        (((Timing->RPDelay)-1) << 20));
+
+    Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
+    Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
+  }
 
   return HAL_OK;
 }
@@ -187,9 +182,11 @@ static HAL_StatusTypeDef _HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
   * @brief  Initializes the SDRAM device.
   * @retval SDRAM status
   */
-uint8_t BSP_SDRAM_Init(void)
+void BSP_SDRAM_Init(void)
 { 
-  static uint8_t sdramstatus = SDRAM_ERROR;
+  SDRAM_HandleTypeDef sdramHandle;
+  FMC_SDRAM_TimingTypeDef Timing;
+
   /* SDRAM device configuration */
   sdramHandle.Instance = FMC_SDRAM_DEVICE;
     
@@ -215,46 +212,12 @@ uint8_t BSP_SDRAM_Init(void)
   
   /* SDRAM controller initialization */
 
-  BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
+  BSP_SDRAM_MspInit(&sdramHandle);
 
-  if(_HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
-  {
-    sdramstatus = SDRAM_ERROR;
-  }
-  else
-  {
-    sdramstatus = SDRAM_OK;
-  }
+  _HAL_SDRAM_Init(&sdramHandle, &Timing);
   
   /* SDRAM initialization sequence */
-  BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
-  
-  return sdramstatus;
-}
-
-/**
-  * @brief  DeInitializes the SDRAM device.
-  * @retval SDRAM status
-  */
-uint8_t BSP_SDRAM_DeInit(void)
-{ 
-  static uint8_t sdramstatus = SDRAM_ERROR;
-  /* SDRAM device de-initialization */
-  sdramHandle.Instance = FMC_SDRAM_DEVICE;
-
-  if(_HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
-  {
-    sdramstatus = SDRAM_ERROR;
-  }
-  else
-  {
-    sdramstatus = SDRAM_OK;
-  }
-  
-  /* SDRAM controller de-initialization */
-  BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
-  
-  return sdramstatus;
+  BSP_SDRAM_Initialization_sequence(&sdramHandle, REFRESH_COUNT);
 }
 
 static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
@@ -269,7 +232,7 @@ static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC
   hsdram->State = HAL_SDRAM_STATE_BUSY;
 
   /* Send SDRAM command */
-  FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
+  _FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
 
   /* Update the SDRAM controller state state */
   if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
@@ -284,6 +247,41 @@ static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC
   return HAL_OK;
 }
 
+static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
+{
+  __IO uint32_t tmpr = 0;
+  systemticks_t tickstart = 0;
+
+  /* Set command register */
+  tmpr = (uint32_t)((Command->CommandMode)                  |\
+                    (Command->CommandTarget)                |\
+                    (((Command->AutoRefreshNumber)-1) << 5) |\
+                    ((Command->ModeRegisterDefinition) << 9)
+                    );
+
+  Device->SDCMR = tmpr;
+
+  /* Get tick */
+  tickstart = gfxSystemTicks();
+
+  /* wait until command is send */
+  while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((gfxSystemTicks() - tickstart ) > Timeout))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
 static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
 {
   /* Check the SDRAM controller state */
@@ -296,7 +294,7 @@ static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdr
   hsdram->State = HAL_SDRAM_STATE_BUSY;
 
   /* Program the refresh rate */
-  FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
+  _FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
 
   /* Update the SDRAM state */
   hsdram->State = HAL_SDRAM_STATE_READY;
@@ -304,33 +302,10 @@ static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdr
   return HAL_OK;
 }
 
-static HAL_StatusTypeDef _HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
 {
-  __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
-
-  /* Process Locked */
-  __HAL_LOCK(hsdram);
-
-  /* Check the SDRAM controller state */
-  if(hsdram->State == HAL_SDRAM_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Read data from source */
-  for(; BufferSize != 0; BufferSize--)
-  {
-    *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
-    pDstBuffer++;
-    pSdramAddress++;
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hsdram);
+  /* Set the refresh rate in command register */
+  Device->SDRTR |= (RefreshRate<<1);
 
   return HAL_OK;
 }
@@ -461,363 +436,14 @@ static HAL_StatusTypeDef _HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
   return HAL_OK;
 }
 
-static void _HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
-  /* Transfer Error Interrupt management ***************************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
-    {
-      /* Disable the transfer error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
-
-      /* Clear the transfer error flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
-    }
-  }
-  /* FIFO Error Interrupt management ******************************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
-    {
-      /* Disable the FIFO Error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
-
-      /* Clear the FIFO error flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
-    }
-  }
-  /* Direct Mode Error Interrupt management ***********************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
-    {
-      /* Disable the direct mode Error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
-
-      /* Clear the direct mode error flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
-    }
-  }
-  /* Half Transfer Complete Interrupt management ******************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
-    {
-      /* Multi_Buffering mode enabled */
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
-      {
-        /* Clear the half transfer complete flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
-        /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
-        {
-          /* Change DMA peripheral state */
-          hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
-        }
-        /* Current memory buffer used is Memory 1 */
-        else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
-        {
-          /* Change DMA peripheral state */
-          hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
-        }
-      }
-      else
-      {
-        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
-        {
-          /* Disable the half transfer interrupt */
-          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
-        }
-        /* Clear the half transfer complete flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
-      }
-
-      if(hdma->XferHalfCpltCallback != NULL)
-      {
-        /* Half transfer callback */
-        hdma->XferHalfCpltCallback(hdma);
-      }
-    }
-  }
-  /* Transfer Complete Interrupt management ***********************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
-    {
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
-      {
-        /* Clear the transfer complete flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
-        /* Current memory buffer used is Memory 1 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
-        {
-          if(hdma->XferM1CpltCallback != NULL)
-          {
-            /* Transfer complete Callback for memory1 */
-            hdma->XferM1CpltCallback(hdma);
-          }
-        }
-        /* Current memory buffer used is Memory 0 */
-        else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
-        {
-          if(hdma->XferCpltCallback != NULL)
-          {
-            /* Transfer complete Callback for memory0 */
-            hdma->XferCpltCallback(hdma);
-          }
-        }
-      }
-      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
-      else
-      {
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
-        {
-          /* Disable the transfer complete interrupt */
-          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
-        }
-        /* Clear the transfer complete flag */
-        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY_MEM0;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
-        if(hdma->XferCpltCallback != NULL)
-        {
-          /* Transfer complete callback */
-          hdma->XferCpltCallback(hdma);
-        }
-      }
-    }
-  }
-}
-
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Clear DBM bit */
-  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
-
-  /* Configure DMA Stream data length */
-  hdma->Instance->NDTR = DataLength;
-
-  /* Peripheral to Memory */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {
-    /* Configure DMA Stream destination address */
-    hdma->Instance->PAR = DstAddress;
-
-    /* Configure DMA Stream source address */
-    hdma->Instance->M0AR = SrcAddress;
-  }
-  /* Memory to Peripheral */
-  else
-  {
-    /* Configure DMA Stream source address */
-    hdma->Instance->PAR = SrcAddress;
-
-    /* Configure DMA Stream destination address */
-    hdma->Instance->M0AR = DstAddress;
-  }
-}
-
-static HAL_StatusTypeDef _HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Configure the source, destination address and the data length */
-  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-  /* Enable the transfer complete interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
-
-  /* Enable the Half transfer complete interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
-
-  /* Enable the transfer Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
-
-  /* Enable the FIFO Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
-
-  /* Enable the direct mode Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
-
-   /* Enable the Peripheral */
-  __HAL_DMA_ENABLE(hdma);
-
-  return HAL_OK;
-}
-
-static HAL_StatusTypeDef _HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
-  uint32_t tmp = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hsdram);
-
-  /* Check the SDRAM controller state */
-  tmp = hsdram->State;
-
-  if(tmp == HAL_SDRAM_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Configure DMA user callbacks */
-  hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
-  hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
-
-  /* Enable the DMA Stream */
-  _HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hsdram);
-
-  return HAL_OK;
-}
-
-static HAL_StatusTypeDef _HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
-  __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
-  uint32_t tmp = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hsdram);
-
-  /* Check the SDRAM controller state */
-  tmp = hsdram->State;
-
-  if(tmp == HAL_SDRAM_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Write data to memory */
-  for(; BufferSize != 0; BufferSize--)
-  {
-    *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
-    pSrcBuffer++;
-    pSdramAddress++;
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hsdram);
-
-  return HAL_OK;
-}
-
-static HAL_StatusTypeDef _HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
-  uint32_t tmp = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hsdram);
-
-  /* Check the SDRAM controller state */
-  tmp = hsdram->State;
-
-  if(tmp == HAL_SDRAM_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Configure DMA user callbacks */
-  hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
-  hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
-
-  /* Enable the DMA Stream */
-  _HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hsdram);
-
-  return HAL_OK;
-}
-
 /**
   * @brief  Programs the SDRAM device.
   * @param  RefreshCount: SDRAM refresh counter value 
   * @retval None
   */
-void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
+static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshCount)
 {
-  __IO uint32_t tmpmrd = 0;
+  FMC_SDRAM_CommandTypeDef Command;
   
   /* Step 1: Configure a clock configuration enable command */
   Command.CommandMode            = FMC_SDRAM_CMD_CLK_ENABLE;
@@ -826,7 +452,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
   Command.ModeRegisterDefinition = 0;
 
   /* Send the command */
-  _HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+  _HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT);
 
   /* Step 2: Insert 100 us minimum delay */ 
   /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
@@ -839,7 +465,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
   Command.ModeRegisterDefinition = 0;
 
   /* Send the command */
-  _HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+  _HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT);
   
   /* Step 4: Configure an Auto Refresh command */ 
   Command.CommandMode            = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
@@ -848,168 +474,24 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
   Command.ModeRegisterDefinition = 0;
 
   /* Send the command */
-  _HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+  _HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT);
   
   /* Step 5: Program the external memory mode register */
-  tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1          |\
-                     SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |\
-                     SDRAM_MODEREG_CAS_LATENCY_2           |\
-                     SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
-                     SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
-  
   Command.CommandMode            = FMC_SDRAM_CMD_LOAD_MODE;
   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
   Command.AutoRefreshNumber      = 1;
-  Command.ModeRegisterDefinition = tmpmrd;
+  Command.ModeRegisterDefinition = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1          |\
+          	  	  	  	  	  	  	  	  	  SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |\
+          	  	  	  	  	  	  	  	  	  SDRAM_MODEREG_CAS_LATENCY_2           |\
+          	  	  	  	  	  	  	  	  	  SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
+          	  	  	  	  	  	  	  	  	  SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;;
 
   /* Send the command */
-  _HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+  _HAL_SDRAM_SendCommand(hsdram, &Command, SDRAM_TIMEOUT);
   
   /* Step 6: Set the refresh rate counter */
   /* Set the device refresh rate */
-  _HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
-}
-
-/**
-  * @brief  Reads an amount of data from the SDRAM memory in polling mode.
-  * @param  uwStartAddress: Read start address
-  * @param  pData: Pointer to data to be read  
-  * @param  uwDataSize: Size of read data from the memory
-  * @retval SDRAM status
-  */
-uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
-{
-  if(_HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
-  {
-    return SDRAM_ERROR;
-  }
-  else
-  {
-    return SDRAM_OK;
-  } 
-}
-
-/**
-  * @brief  Reads an amount of data from the SDRAM memory in DMA mode.
-  * @param  uwStartAddress: Read start address
-  * @param  pData: Pointer to data to be read  
-  * @param  uwDataSize: Size of read data from the memory
-  * @retval SDRAM status
-  */
-uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
-{
-  if(_HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
-  {
-    return SDRAM_ERROR;
-  }
-  else
-  {
-    return SDRAM_OK;
-  }     
-}
-
-/**
-  * @brief  Writes an amount of data to the SDRAM memory in polling mode.
-  * @param  uwStartAddress: Write start address
-  * @param  pData: Pointer to data to be written  
-  * @param  uwDataSize: Size of written data from the memory
-  * @retval SDRAM status
-  */
-uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 
-{
-  if(_HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
-  {
-    return SDRAM_ERROR;
-  }
-  else
-  {
-    return SDRAM_OK;
-  }
-}
-
-__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-            the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA transfer complete error callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-            the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
-   */
-}
-
-static void _HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
-}
-
-static void _HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  /* Disable interrupt */
-  NVIC_DisableIRQ(IRQn);
-}
-
-/**
-  * @brief  Writes an amount of data to the SDRAM memory in DMA mode.
-  * @param  uwStartAddress: Write start address
-  * @param  pData: Pointer to data to be written  
-  * @param  uwDataSize: Size of written data from the memory
-  * @retval SDRAM status
-  */
-uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 
-{
-  if(_HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
-  {
-    return SDRAM_ERROR;
-  }
-  else
-  {
-    return SDRAM_OK;
-  } 
-}
-
-/**
-  * @brief  Sends command to the SDRAM bank.
-  * @param  SdramCmd: Pointer to SDRAM command structure 
-  * @retval SDRAM status
-  */  
-uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
-{
-  if(_HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
-  {
-    return SDRAM_ERROR;
-  }
-  else
-  {
-    return SDRAM_OK;
-  }
-}
-
-static void _HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t prioritygroup = 0x00;
-
-  prioritygroup = NVIC_GetPriorityGrouping();
-
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
-  * @brief  Handles SDRAM DMA transfer interrupt request.
-  * @retval None
-  */
-void BSP_SDRAM_DMA_IRQHandler(void)
-{
-  _HAL_DMA_IRQHandler(sdramHandle.hdma);
+  _HAL_SDRAM_ProgramRefreshRate(hsdram, RefreshCount);
 }
 
 /**
@@ -1018,10 +500,12 @@ void BSP_SDRAM_DMA_IRQHandler(void)
   * @param  Params
   * @retval None
   */
-__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
+static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram)
 {  
   static DMA_HandleTypeDef dma_handle;
+#if !GFX_USE_OS_CHIBIOS
   GPIO_InitTypeDef gpio_init_structure;
+#endif
   
   /* Enable FMC clock */
   __HAL_RCC_FMC_CLK_ENABLE();
@@ -1037,7 +521,8 @@ __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
   __HAL_RCC_GPIOG_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE();
   
-  /* Common GPIO configuration */
+  /* Common GPIO configuration - some are already setup by ChibiOS Init */
+#if !GFX_USE_OS_CHIBIOS
   gpio_init_structure.Mode      = GPIO_MODE_AF_PP;
   gpio_init_structure.Pull      = GPIO_PULLUP;
   gpio_init_structure.Speed     = GPIO_SPEED_FAST;
@@ -1072,6 +557,7 @@ __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
   /* GPIOH configuration */  
   gpio_init_structure.Pin   = GPIO_PIN_3 | GPIO_PIN_5;
   HAL_GPIO_Init(GPIOH, &gpio_init_structure); 
+#endif
   
   /* Configure common DMA parameters */
   dma_handle.Init.Channel             = SDRAM_DMAx_CHANNEL;
@@ -1099,45 +585,7 @@ __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
   _HAL_DMA_Init(&dma_handle);
   
   /* NVIC configuration for DMA transfer complete interrupt */
-  _HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
-  _HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
-}
-
-/**
-  * @brief  DeInitializes SDRAM MSP.
-  * @param  hsdram: SDRAM handle
-  * @param  Params
-  * @retval None
-  */
-__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
-{  
-    static DMA_HandleTypeDef dma_handle;
-  
-    /* Disable NVIC configuration for DMA interrupt */
-    _HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
-
-    /* Deinitialize the stream for new transfer */
-    dma_handle.Instance = SDRAM_DMAx_STREAM;
-    _HAL_DMA_DeInit(&dma_handle);
-
-    /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
-       by surcharging this __weak function */ 
+  NVIC_SetPriority(SDRAM_DMAx_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
+  /* Enable interrupt */
+  NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
 }
-
-/**
-  * @}
-  */  
-  
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h
index 5512f9d8..abf88291 100644
--- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h
+++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h
@@ -44,127 +44,13 @@
  extern "C" {
 #endif
 
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_rcc.h"
-#include "stm32f7xx_hal_rcc_ex.h"
-#include "stm32f7xx_hal_dma.h"
-#include "stm32f7xx_hal_gpio.h"
-#include "stm32f7xx_hal_sdram.h"
-#include "stm32f7xx_ll_fmc.h"
-
-/** @addtogroup BSP
-  * @{
-  */
-
-/** @addtogroup STM32746G_DISCOVERY
-  * @{
-  */
-
-/** @addtogroup STM32746G_DISCOVERY_SDRAM
-  * @{
-  */
-
-/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types
-  * @{
-  */
-
-/**
-  * @brief  SDRAM status structure definition
-  */
-#define   SDRAM_OK         ((uint8_t)0x00)
-#define   SDRAM_ERROR      ((uint8_t)0x01)
-
-/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
-  * @{
-  */
 #define SDRAM_DEVICE_ADDR  ((uint32_t)0xC0000000)
 #define SDRAM_DEVICE_SIZE  ((uint32_t)0x800000)  /* SDRAM device size in MBytes */
 
-/* #define SDRAM_MEMORY_WIDTH            FMC_SDRAM_MEM_BUS_WIDTH_8  */
-#define SDRAM_MEMORY_WIDTH               FMC_SDRAM_MEM_BUS_WIDTH_16
-
-#define SDCLOCK_PERIOD                   FMC_SDRAM_CLOCK_PERIOD_2
-/* #define SDCLOCK_PERIOD                FMC_SDRAM_CLOCK_PERIOD_3 */
-
-#define REFRESH_COUNT                    ((uint32_t)0x0603)   /* SDRAM refresh counter (100Mhz SD clock) */
-
-#define SDRAM_TIMEOUT                    ((uint32_t)0xFFFF)
-
-/* DMA definitions for SDRAM DMA transfer */
-#define __DMAx_CLK_ENABLE                 __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMAx_CLK_DISABLE                __HAL_RCC_DMA2_CLK_DISABLE
-#define SDRAM_DMAx_CHANNEL                DMA_CHANNEL_0
-#define SDRAM_DMAx_STREAM                 DMA2_Stream0
-#define SDRAM_DMAx_IRQn                   DMA2_Stream0_IRQn
-#define SDRAM_DMAx_IRQHandler             DMA2_Stream0_IRQHandler
-/**
-  * @}
-  */
-
-/**
-  * @brief  FMC SDRAM Mode definition register defines
-  */
-#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
-#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
-#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
-#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
-#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
-#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
-#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
-/**
-  * @}
-  */
-
-/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro
-  * @{
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions
-  * @{
-  */
-uint8_t BSP_SDRAM_Init(void);
-uint8_t BSP_SDRAM_DeInit(void);
-void    BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
-uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
-uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
-uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
-uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
-uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
-void    BSP_SDRAM_DMA_IRQHandler(void);
-
-/* These functions can be modified in case the current settings (e.g. DMA stream)
-   need to be changed for specific application needs */
-void    BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
-void    BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
+void BSP_SDRAM_Init(void);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32746G_DISCOVERY_SDRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif
diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
index 794d3c66..73df79e8 100644
--- a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
+++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
@@ -1,6 +1,7 @@
 #include "gfx.h"
 #include "stm32f7xx_hal.h"
 
+#if !GFX_USE_OS_CHIBIOS
 systemticks_t gfxSystemTicks(void)
 {
 	return HAL_GetTick();
@@ -10,13 +11,12 @@ systemticks_t gfxMillisecondsToTicks(delaytime_t ms)
 {
 	return ms;
 }
+#endif
 
 static void SystemClock_Config(void);
 static void CPU_CACHE_Enable(void);
 
 void Raw32OSInit(void) {
-    RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
-
     /* Enable the CPU Cache */
     CPU_CACHE_Enable();
 
@@ -31,6 +31,7 @@ void Raw32OSInit(void) {
     /* Configure the system clock to 216 MHz */
     SystemClock_Config();
 
+#if !GFX_USE_OS_CHIBIOS
     // LED - for testing
 	GPIO_InitTypeDef  GPIO_InitStruct;
 	GPIO_InitStruct.Pin = GPIO_PIN_1;
@@ -39,6 +40,7 @@ void Raw32OSInit(void) {
 	GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
     __GPIOI_CLK_ENABLE();
 	HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+#endif
 
 }
 
@@ -64,48 +66,6 @@ void Raw32OSInit(void) {
   */
 void SystemClock_Config(void)
 {
-#if 0
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  HAL_StatusTypeDef ret = HAL_OK;
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = 12;
-  RCC_OscInitStruct.PLL.PLLN = 192;		// 432
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 2;		// 9
-
-  ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  if(ret != HAL_OK)
-  {
-    while(1) { ; }
-  }
-
-  /* Activate the OverDrive to reach the 200/216 MHz Frequency */
-  ret = HAL_PWREx_EnableOverDrive();
-  if(ret != HAL_OK)
-  {
-    while(1) { ; }
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-
-  ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6);	// FLASH_LATENCY_7
-  if(ret != HAL_OK)
-  {
-    while(1) { ; }
-  }
-#else
-
   RCC_OscInitTypeDef RCC_OscInitStruct;
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
@@ -143,7 +103,6 @@ void SystemClock_Config(void)
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
-#endif
 }
 
 /**
diff --git a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c
deleted file mode 100644
index b7995014..00000000
--- a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c
+++ /dev/null
@@ -1,1124 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_ll_fmc.c
-  * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
-  * @brief   FMC Low Layer HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                        ##### FMC peripheral features #####
-  ==============================================================================
-  [..] The Flexible memory controller (FMC) includes three memory controllers:
-       (+) The NOR/PSRAM memory controller
-       (+) The NAND memory controller
-       (+) The Synchronous DRAM (SDRAM) controller 
-       
-  [..] The FMC functional block makes the interface with synchronous and asynchronous static
-       memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
-       (+) to translate AHB transactions into the appropriate external device protocol
-       (+) to meet the access time requirements of the external memory devices
-   
-  [..] All external memories share the addresses, data and control signals with the controller.
-       Each external device is accessed by means of a unique Chip Select. The FMC performs
-       only one access at a time to an external device.
-       The main features of the FMC controller are the following:
-        (+) Interface with static-memory mapped devices including:
-           (++) Static random access memory (SRAM)
-           (++) Read-only memory (ROM)
-           (++) NOR Flash memory/OneNAND Flash memory
-           (++) PSRAM (4 memory banks)
-           (++) 16-bit PC Card compatible devices
-           (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
-                data
-        (+) Interface with synchronous DRAM (SDRAM) memories
-        (+) Independent Chip Select control for each memory bank
-        (+) Independent configuration for each memory bank
-                    
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "gfx.h"
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FMC_LL  FMC Low Layer
-  * @brief FMC driver modules
-  * @{
-  */
-
-#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
-  * @{
-  */
-
-/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
-  * @brief  NORSRAM Controller functions 
-  *
-  @verbatim 
-  ==============================================================================   
-                   ##### How to use NORSRAM device driver #####
-  ==============================================================================
- 
-  [..] 
-    This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
-    to run the NORSRAM external devices.
-      
-    (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() 
-    (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
-    (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
-    (+) FMC NORSRAM bank extended timing configuration using the function 
-        FMC_NORSRAM_Extended_Timing_Init()
-    (+) FMC NORSRAM bank enable/disable write operation using the functions
-        FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
-        
-
-@endverbatim
-  * @{
-  */
-       
-/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    Initialization and Configuration functions 
-  *
-  @verbatim    
-  ==============================================================================
-              ##### Initialization and de_initialization functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to:
-    (+) Initialize and configure the FMC NORSRAM interface
-    (+) De-initialize the FMC NORSRAM interface 
-    (+) Configure the FMC clock and associated GPIOs    
- 
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Initialize the FMC_NORSRAM device according to the specified
-  *         control parameters in the FMC_NORSRAM_InitTypeDef
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Init: Pointer to NORSRAM Initialization structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
-{ 
-  uint32_t tmpr = 0;
-    
-  /* Check the parameters */
-  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
-  assert_param(IS_FMC_MUX(Init->DataAddressMux));
-  assert_param(IS_FMC_MEMORY(Init->MemoryType));
-  assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
-  assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
-  assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
-  assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
-  assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
-  assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
-  assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
-  assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
-  assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
-  assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); 
-  assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
-  assert_param(IS_FMC_PAGESIZE(Init->PageSize));
-
-  /* Get the BTCR register value */
-  tmpr = Device->BTCR[Init->NSBank];
-  
-  /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
-           WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
-  tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN     | FMC_BCR1_MUXEN    | FMC_BCR1_MTYP     | \
-                       FMC_BCR1_MWID      | FMC_BCR1_FACCEN   | FMC_BCR1_BURSTEN  | \
-                       FMC_BCR1_WAITPOL   | FMC_BCR1_CPSIZE    | FMC_BCR1_WAITCFG  | \
-                       FMC_BCR1_WREN      | FMC_BCR1_WAITEN   | FMC_BCR1_EXTMOD   | \
-                       FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));
-  
-  /* Set NORSRAM device control parameters */
-  tmpr |= (uint32_t)(Init->DataAddressMux       |\
-                    Init->MemoryType           |\
-                    Init->MemoryDataWidth      |\
-                    Init->BurstAccessMode      |\
-                    Init->WaitSignalPolarity   |\
-                    Init->WaitSignalActive     |\
-                    Init->WriteOperation       |\
-                    Init->WaitSignal           |\
-                    Init->ExtendedMode         |\
-                    Init->AsynchronousWait     |\
-                    Init->WriteBurst           |\
-                    Init->ContinuousClock      |\
-                    Init->PageSize             |\
-                    Init->WriteFifo);
-                    
-  if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
-  {
-    tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
-  }
-  
-  Device->BTCR[Init->NSBank] = tmpr;
-
-  /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
-  if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
-  { 
-    Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; 
-    Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode  |\
-                                                  Init->ContinuousClock);
-  }
-  if(Init->NSBank != FMC_NORSRAM_BANK1)
-  {
-    Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);              
-  }
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  DeInitialize the FMC_NORSRAM peripheral 
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  ExDevice: Pointer to NORSRAM extended mode device instance  
-  * @param  Bank: NORSRAM bank number  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
-{
-  /* Check the parameters */
-  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
-  assert_param(IS_FMC_NORSRAM_BANK(Bank));
-  
-  /* Disable the FMC_NORSRAM device */
-  __FMC_NORSRAM_DISABLE(Device, Bank);
-  
-  /* De-initialize the FMC_NORSRAM device */
-  /* FMC_NORSRAM_BANK1 */
-  if(Bank == FMC_NORSRAM_BANK1)
-  {
-    Device->BTCR[Bank] = 0x000030DB;    
-  }
-  /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
-  else
-  {   
-    Device->BTCR[Bank] = 0x000030D2; 
-  }
-  
-  Device->BTCR[Bank + 1] = 0x0FFFFFFF;
-  ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
-   
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initialize the FMC_NORSRAM Timing according to the specified
-  *         parameters in the FMC_NORSRAM_TimingTypeDef
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Timing: Pointer to NORSRAM Timing structure
-  * @param  Bank: NORSRAM bank number  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
-{
-  uint32_t tmpr = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
-  assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
-  assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
-  assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-  assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
-  assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
-  assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
-  assert_param(IS_FMC_NORSRAM_BANK(Bank));
-  
-  /* Get the BTCR register value */
-  tmpr = Device->BTCR[Bank + 1];
-
-  /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
-  tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET  | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
-                       FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
-                       FMC_BTR1_ACCMOD));
-  
-  /* Set FMC_NORSRAM device timing parameters */  
-  tmpr |= (uint32_t)(Timing->AddressSetupTime                  |\
-                   ((Timing->AddressHoldTime) << 4)          |\
-                   ((Timing->DataSetupTime) << 8)            |\
-                   ((Timing->BusTurnAroundDuration) << 16)   |\
-                   (((Timing->CLKDivision)-1) << 20)         |\
-                   (((Timing->DataLatency)-2) << 24)         |\
-                    (Timing->AccessMode)
-                    );
-  
-  Device->BTCR[Bank + 1] = tmpr;
-  
-  /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
-  if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
-  {
-    tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); 
-    tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
-    Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
-  }  
-  
-  return HAL_OK;   
-}
-
-/**
-  * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
-  *         parameters in the FMC_NORSRAM_TimingTypeDef
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Timing: Pointer to NORSRAM Timing structure
-  * @param  Bank: NORSRAM bank number  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
-{  
-  uint32_t tmpr = 0;
- 
-  /* Check the parameters */
-  assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
-  
-  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
-  if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
-  {
-    /* Check the parameters */
-    assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  
-    assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
-    assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
-    assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
-    assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-    assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
-    assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
-    assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
-    assert_param(IS_FMC_NORSRAM_BANK(Bank));  
-    
-    /* Get the BWTR register value */
-    tmpr = Device->BWTR[Bank];
-
-    /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
-    tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET  | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
-                         FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
-    
-    tmpr |= (uint32_t)(Timing->AddressSetupTime                 |\
-                      ((Timing->AddressHoldTime) << 4)          |\
-                      ((Timing->DataSetupTime) << 8)            |\
-                      ((Timing->BusTurnAroundDuration) << 16)   |\
-                      (Timing->AccessMode));
-
-    Device->BWTR[Bank] = tmpr;
-  }
-  else
-  {
-    Device->BWTR[Bank] = 0x0FFFFFFF;
-  }   
-  
-  return HAL_OK;  
-}
-/**
-  * @}
-  */
-
-/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
- *  @brief   management functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### FMC_NORSRAM Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control dynamically
-    the FMC NORSRAM interface.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables dynamically FMC_NORSRAM write operation.
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Bank: NORSRAM bank number   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
-  /* Check the parameters */
-  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FMC_NORSRAM_BANK(Bank));
-  
-  /* Enable write operation */
-  Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; 
-
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Disables dynamically FMC_NORSRAM write operation.
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Bank: NORSRAM bank number   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{ 
-  /* Check the parameters */
-  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FMC_NORSRAM_BANK(Bank));
-    
-  /* Disable write operation */
-  Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; 
-
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
-  * @brief    NAND Controller functions 
-  *
-  @verbatim 
-  ==============================================================================
-                    ##### How to use NAND device driver #####
-  ==============================================================================
-  [..]
-    This driver contains a set of APIs to interface with the FMC NAND banks in order
-    to run the NAND external devices.
-  
-    (+) FMC NAND bank reset using the function FMC_NAND_DeInit() 
-    (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
-    (+) FMC NAND bank common space timing configuration using the function 
-        FMC_NAND_CommonSpace_Timing_Init()
-    (+) FMC NAND bank attribute space timing configuration using the function 
-        FMC_NAND_AttributeSpace_Timing_Init()
-    (+) FMC NAND bank enable/disable ECC correction feature using the functions
-        FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
-    (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()    
-
-@endverbatim
-  * @{
-  */
-
-/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de_initialization functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to:
-    (+) Initialize and configure the FMC NAND interface
-    (+) De-initialize the FMC NAND interface 
-    (+) Configure the FMC clock and associated GPIOs
-        
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the FMC_NAND device according to the specified
-  *         control parameters in the FMC_NAND_HandleTypeDef
-  * @param  Device: Pointer to NAND device instance
-  * @param  Init: Pointer to NAND Initialization structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
-{
-  uint32_t tmpr  = 0; 
-    
-  /* Check the parameters */
-  assert_param(IS_FMC_NAND_DEVICE(Device));
-  assert_param(IS_FMC_NAND_BANK(Init->NandBank));
-  assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
-  assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
-  assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
-  assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
-  assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
-  assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));   
-
-  /* Get the NAND bank 3 register value */
-  tmpr = Device->PCR;
-
-  /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
-  tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN  | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
-                       FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
-                       FMC_PCR_TAR | FMC_PCR_ECCPS));  
-  /* Set NAND device control parameters */
-  tmpr |= (uint32_t)(Init->Waitfeature                |\
-                      FMC_PCR_MEMORY_TYPE_NAND         |\
-                      Init->MemoryDataWidth            |\
-                      Init->EccComputation             |\
-                      Init->ECCPageSize                |\
-                      ((Init->TCLRSetupTime) << 9)     |\
-                      ((Init->TARSetupTime) << 13));   
-  
-    /* NAND bank 3 registers configuration */
-    Device->PCR  = tmpr;
-  
-  return HAL_OK;
-
-}
-
-/**
-  * @brief  Initializes the FMC_NAND Common space Timing according to the specified
-  *         parameters in the FMC_NAND_PCC_TimingTypeDef
-  * @param  Device: Pointer to NAND device instance
-  * @param  Timing: Pointer to NAND timing structure
-  * @param  Bank: NAND bank number   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
-{
-  uint32_t tmpr = 0;  
-  
-  /* Check the parameters */
-  assert_param(IS_FMC_NAND_DEVICE(Device));
-  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
-  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
-  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
-  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
-  assert_param(IS_FMC_NAND_BANK(Bank));
-  
-  /* Get the NAND bank 3 register value */
-  tmpr = Device->PMEM;
-
-  /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
-  tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3  | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \
-                       FMC_PMEM_MEMHIZ3)); 
-  /* Set FMC_NAND device timing parameters */
-  tmpr |= (uint32_t)(Timing->SetupTime                  |\
-                       ((Timing->WaitSetupTime) << 8)     |\
-                       ((Timing->HoldSetupTime) << 16)    |\
-                       ((Timing->HiZSetupTime) << 24)
-                       );
-                            
-    /* NAND bank 3 registers configuration */
-    Device->PMEM = tmpr;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
-  *         parameters in the FMC_NAND_PCC_TimingTypeDef
-  * @param  Device: Pointer to NAND device instance
-  * @param  Timing: Pointer to NAND timing structure
-  * @param  Bank: NAND bank number 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
-{
-  uint32_t tmpr = 0;  
-  
-  /* Check the parameters */ 
-  assert_param(IS_FMC_NAND_DEVICE(Device)); 
-  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
-  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
-  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
-  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
-  assert_param(IS_FMC_NAND_BANK(Bank));
-  
-  /* Get the NAND bank 3 register value */
-  tmpr = Device->PATT;
-
-  /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
-  tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3  | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \
-                       FMC_PATT_ATTHIZ3));
-  /* Set FMC_NAND device timing parameters */
-  tmpr |= (uint32_t)(Timing->SetupTime                  |\
-                   ((Timing->WaitSetupTime) << 8)     |\
-                   ((Timing->HoldSetupTime) << 16)    |\
-                   ((Timing->HiZSetupTime) << 24));
-                       
-    /* NAND bank 3 registers configuration */
-    Device->PATT = tmpr;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the FMC_NAND device 
-  * @param  Device: Pointer to NAND device instance
-  * @param  Bank: NAND bank number
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
-{
-  /* Check the parameters */ 
-  assert_param(IS_FMC_NAND_DEVICE(Device)); 
-  assert_param(IS_FMC_NAND_BANK(Bank));
-      
-  /* Disable the NAND Bank */
-  __FMC_NAND_DISABLE(Device);
- 
-    /* Set the FMC_NAND_BANK3 registers to their reset values */
-    Device->PCR  = 0x00000018;
-    Device->SR   = 0x00000040;
-    Device->PMEM = 0xFCFCFCFC;
-    Device->PATT = 0xFCFCFCFC; 
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FMC_NAND_Group3 Control functions 
-  *  @brief   management functions 
-  *
-@verbatim   
-  ==============================================================================
-                       ##### FMC_NAND Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control dynamically
-    the FMC NAND interface.
-
-@endverbatim
-  * @{
-  */ 
-
-    
-/**
-  * @brief  Enables dynamically FMC_NAND ECC feature.
-  * @param  Device: Pointer to NAND device instance
-  * @param  Bank: NAND bank number
-  * @retval HAL status
-  */    
-HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
-{
-  /* Check the parameters */ 
-  assert_param(IS_FMC_NAND_DEVICE(Device)); 
-  assert_param(IS_FMC_NAND_BANK(Bank));
-    
-  /* Enable ECC feature */
-    Device->PCR |= FMC_PCR_ECCEN;
-  
-  return HAL_OK;  
-}
-
-
-/**
-  * @brief  Disables dynamically FMC_NAND ECC feature.
-  * @param  Device: Pointer to NAND device instance
-  * @param  Bank: NAND bank number
-  * @retval HAL status
-  */  
-HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  
-{  
-  /* Check the parameters */ 
-  assert_param(IS_FMC_NAND_DEVICE(Device)); 
-  assert_param(IS_FMC_NAND_BANK(Bank));
-    
-  /* Disable ECC feature */
-    Device->PCR &= ~FMC_PCR_ECCEN;
-
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Disables dynamically FMC_NAND ECC feature.
-  * @param  Device: Pointer to NAND device instance
-  * @param  ECCval: Pointer to ECC value
-  * @param  Bank: NAND bank number
-  * @param  Timeout: Timeout wait value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
-{
-  systemticks_t tickstart = 0;
-
-  /* Check the parameters */ 
-  assert_param(IS_FMC_NAND_DEVICE(Device)); 
-  assert_param(IS_FMC_NAND_BANK(Bank));
-
-  /* Get tick */ 
-  tickstart = gfxSystemTicks();
-
-  /* Wait until FIFO is empty */
-  while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((gfxSystemTicks() - tickstart ) > Timeout))
-      {
-        return HAL_TIMEOUT;
-      }
-    }  
-  }
- 
-  /* Get the ECCR register value */
-  *ECCval = (uint32_t)Device->ECCR;
-
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/** @defgroup FMC_LL_SDRAM
-  * @brief    SDRAM Controller functions 
-  *
-  @verbatim 
-  ==============================================================================
-                     ##### How to use SDRAM device driver #####
-  ==============================================================================
-  [..] 
-    This driver contains a set of APIs to interface with the FMC SDRAM banks in order
-    to run the SDRAM external devices.
-    
-    (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() 
-    (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
-    (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
-    (+) FMC SDRAM bank enable/disable write operation using the functions
-        FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()   
-    (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()      
-       
-@endverbatim
-  * @{
-  */
-         
-/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de_initialization functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to:
-    (+) Initialize and configure the FMC SDRAM interface
-    (+) De-initialize the FMC SDRAM interface 
-    (+) Configure the FMC clock and associated GPIOs
-        
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the FMC_SDRAM device according to the specified
-  *         control parameters in the FMC_SDRAM_InitTypeDef
-  * @param  Device: Pointer to SDRAM device instance
-  * @param  Init: Pointer to SDRAM Initialization structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
-{
-  uint32_t tmpr1 = 0;
-  uint32_t tmpr2 = 0;
-    
-  /* Check the parameters */
-  assert_param(IS_FMC_SDRAM_DEVICE(Device));
-  assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
-  assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
-  assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
-  assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
-  assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
-  assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
-  assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
-  assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
-  assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
-  assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));   
-
-  /* Set SDRAM bank configuration parameters */
-  if (Init->SDBank != FMC_SDRAM_BANK2) 
-  { 
-    tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
-    
-    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
-    tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
-                         FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
-                         FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
-
-    tmpr1 |= (uint32_t)(Init->ColumnBitsNumber   |\
-                        Init->RowBitsNumber      |\
-                        Init->MemoryDataWidth    |\
-                        Init->InternalBankNumber |\
-                        Init->CASLatency         |\
-                        Init->WriteProtection    |\
-                        Init->SDClockPeriod      |\
-                        Init->ReadBurst          |\
-                        Init->ReadPipeDelay
-                        );                                      
-    Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
-  }
-  else /* FMC_Bank2_SDRAM */                      
-  {
-    tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
-    
-    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
-    tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
-                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
-                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
-    
-    tmpr1 |= (uint32_t)(Init->SDClockPeriod      |\
-                        Init->ReadBurst          |\
-                        Init->ReadPipeDelay);  
-    
-    tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
-    
-    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
-    tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
-                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
-                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
-
-    tmpr2 |= (uint32_t)(Init->ColumnBitsNumber   |\
-                       Init->RowBitsNumber      |\
-                       Init->MemoryDataWidth    |\
-                       Init->InternalBankNumber |\
-                       Init->CASLatency         |\
-                       Init->WriteProtection);
-
-    Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
-    Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
-  }  
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the FMC_SDRAM device timing according to the specified
-  *         parameters in the FMC_SDRAM_TimingTypeDef
-  * @param  Device: Pointer to SDRAM device instance
-  * @param  Timing: Pointer to SDRAM Timing structure
-  * @param  Bank: SDRAM bank number   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
-{
-  uint32_t tmpr1 = 0;
-  uint32_t tmpr2 = 0;
-    
-  /* Check the parameters */
-  assert_param(IS_FMC_SDRAM_DEVICE(Device));
-  assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
-  assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
-  assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
-  assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
-  assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
-  assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
-  assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
-  assert_param(IS_FMC_SDRAM_BANK(Bank));
-  
-  /* Set SDRAM device timing parameters */ 
-  if (Bank != FMC_SDRAM_BANK2) 
-  { 
-    tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
-    
-    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
-    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
-                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
-                          FMC_SDTR1_TRCD));
-    
-    tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
-                       (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
-                       (((Timing->SelfRefreshTime)-1) << 8)      |\
-                       (((Timing->RowCycleDelay)-1) << 12)       |\
-                       (((Timing->WriteRecoveryTime)-1) <<16)    |\
-                       (((Timing->RPDelay)-1) << 20)             |\
-                       (((Timing->RCDDelay)-1) << 24));
-    Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
-  }
-  else /* FMC_Bank2_SDRAM */
-  {  
-    tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
-    
-    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
-    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
-                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
-                          FMC_SDTR1_TRCD));
-    
-    tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
-                       (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
-                       (((Timing->SelfRefreshTime)-1) << 8)      |\
-                       (((Timing->WriteRecoveryTime)-1) <<16)    |\
-                       (((Timing->RCDDelay)-1) << 24));   
-    
-    tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
-    
-    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
-    tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
-                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
-                          FMC_SDTR1_TRCD));
-    tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12)       |\
-                        (((Timing->RPDelay)-1) << 20)); 
-
-    Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
-    Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
-  }   
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the FMC_SDRAM peripheral 
-  * @param  Device: Pointer to SDRAM device instance
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
-{
-  /* Check the parameters */
-  assert_param(IS_FMC_SDRAM_DEVICE(Device));
-  assert_param(IS_FMC_SDRAM_BANK(Bank));
-  
-  /* De-initialize the SDRAM device */
-  Device->SDCR[Bank] = 0x000002D0;
-  Device->SDTR[Bank] = 0x0FFFFFFF;    
-  Device->SDCMR      = 0x00000000;
-  Device->SDRTR      = 0x00000000;
-  Device->SDSR       = 0x00000000;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
-  *  @brief   management functions 
-  *
-@verbatim   
-  ==============================================================================
-                      ##### FMC_SDRAM Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control dynamically
-    the FMC SDRAM interface.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables dynamically FMC_SDRAM write protection.
-  * @param  Device: Pointer to SDRAM device instance
-  * @param  Bank: SDRAM bank number 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
-{ 
-  /* Check the parameters */
-  assert_param(IS_FMC_SDRAM_DEVICE(Device));
-  assert_param(IS_FMC_SDRAM_BANK(Bank));
-  
-  /* Enable write protection */
-  Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Disables dynamically FMC_SDRAM write protection.
-  * @param  hsdram: FMC_SDRAM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
-{
-  /* Check the parameters */
-  assert_param(IS_FMC_SDRAM_DEVICE(Device));
-  assert_param(IS_FMC_SDRAM_BANK(Bank));
-  
-  /* Disable write protection */
-  Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
-  
-  return HAL_OK;
-}
-  
-/**
-  * @brief  Send Command to the FMC SDRAM bank
-  * @param  Device: Pointer to SDRAM device instance
-  * @param  Command: Pointer to SDRAM command structure   
-  * @param  Timing: Pointer to SDRAM Timing structure
-  * @param  Timeout: Timeout wait value
-  * @retval HAL state
-  */  
-HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
-{
-  __IO uint32_t tmpr = 0;
-  systemticks_t tickstart = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_FMC_SDRAM_DEVICE(Device));
-  assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
-  assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
-  assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
-  assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));  
-
-  /* Set command register */
-  tmpr = (uint32_t)((Command->CommandMode)                  |\
-                    (Command->CommandTarget)                |\
-                    (((Command->AutoRefreshNumber)-1) << 5) |\
-                    ((Command->ModeRegisterDefinition) << 9)
-                    );
-    
-  Device->SDCMR = tmpr;
-
-  /* Get tick */ 
-  tickstart = gfxSystemTicks();
-
-  /* wait until command is send */
-  while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((gfxSystemTicks() - tickstart ) > Timeout))
-      {
-        return HAL_TIMEOUT;
-      }
-    }     
-    
-    return HAL_ERROR;
-  }
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Program the SDRAM Memory Refresh rate.
-  * @param  Device: Pointer to SDRAM device instance  
-  * @param  RefreshRate: The SDRAM refresh rate value.       
-  * @retval HAL state
-  */
-HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
-{
-  /* Check the parameters */
-  assert_param(IS_FMC_SDRAM_DEVICE(Device));
-  assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
-  
-  /* Set the refresh rate in command register */
-  Device->SDRTR |= (RefreshRate<<1);
-  
-  return HAL_OK;   
-}
-
-/**
-  * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.
-  * @param  Device: Pointer to SDRAM device instance  
-  * @param  AutoRefreshNumber: Specifies the auto Refresh number.       
-  * @retval None
-  */
-HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
-{
-  /* Check the parameters */
-  assert_param(IS_FMC_SDRAM_DEVICE(Device));
-  assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
-  
-  /* Set the Auto-refresh number in command register */
-  Device->SDCMR |= (AutoRefreshNumber << 5); 
-
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Returns the indicated FMC SDRAM bank mode status.
-  * @param  Device: Pointer to SDRAM device instance  
-  * @param  Bank: Defines the FMC SDRAM bank. This parameter can be 
-  *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. 
-  * @retval The FMC SDRAM bank mode status, could be on of the following values:
-  *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or 
-  *         FMC_SDRAM_POWER_DOWN_MODE.           
-  */
-uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_FMC_SDRAM_DEVICE(Device));
-  assert_param(IS_FMC_SDRAM_BANK(Bank));
-
-  /* Get the corresponding bank mode */
-  if(Bank == FMC_SDRAM_BANK1)
-  {
-    tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); 
-  }
-  else
-  {
-    tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
-  }
-  
-  /* Return the mode status */
-  return tmpreg;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h
deleted file mode 100644
index 85e8bedf..00000000
--- a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h
+++ /dev/null
@@ -1,1338 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_ll_fmc.h
-  * @author  MCD Application Team
-  * @version V1.0.1
-  * @date    25-June-2015
-  * @brief   Header file of FMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_FMC_H
-#define __STM32F7xx_LL_FMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gfx.h"
-#include "stm32f7xx_hal_def.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FMC_LL
-  * @{
-  */
-
-/** @addtogroup FMC_LL_Private_Macros
-  * @{
-  */
-#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
-                                   ((BANK) == FMC_NORSRAM_BANK2) || \
-                                   ((BANK) == FMC_NORSRAM_BANK3) || \
-                                   ((BANK) == FMC_NORSRAM_BANK4))
-
-#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
-                              ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
-
-#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
-                                    ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
-                                    ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
-
-#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
-                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
-                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
-
-#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
-                                       ((__MODE__) == FMC_ACCESS_MODE_B) || \
-                                       ((__MODE__) == FMC_ACCESS_MODE_C) || \
-                                       ((__MODE__) == FMC_ACCESS_MODE_D))
-
-#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
-
-#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
-                                      ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
-
-#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \
-                                         ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
-
-#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
-                                 ((STATE) == FMC_NAND_ECC_ENABLE))
-
-#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
-                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
-                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
-                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
-                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
-                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-								   
-#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8)  || \
-                                      ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
-                                      ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
-
-#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
-                                            ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))									  
-
-#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE)  || \
-                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
-                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
-										   
-#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
-                                       ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
-									   
-#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
-                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
-                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
-
-#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE)      || \
-                                          ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE)       || \
-                                          ((__COMMAND__) == FMC_SDRAM_CMD_PALL)             || \
-                                          ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
-                                          ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE)        || \
-                                          ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
-                                          ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
-
-#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
-                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
-                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) 										  
-						   
-/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
-  * @{
-  */
-#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time 
-  * @{
-  */
-#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Setup_Time FMC Setup Time 
-  * @{
-  */
-#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time 
-  * @{
-  */
-#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time 
-  * @{
-  */
-#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time 
-  * @{
-  */
-#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
-/**
-  * @}
-  */
-
-#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
-                                      ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
-
-#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
-                                             ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
-
-#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
-                                                ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 
-
-#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
-                                                ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
-
-#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
-                                          ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
-
-#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
-                                         ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
-
-#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
-                                     ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
-
-/** @defgroup FMC_Data_Latency FMC Data Latency 
-  * @{
-  */
-#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
-/**
-  * @}
-  */
-
-#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
-                                        ((__BURST__) == FMC_WRITE_BURST_ENABLE))
-
-#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
-                                        ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-
-
-/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
-  * @{
-  */
-#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
-  * @{
-  */
-#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
-  * @{
-  */
-#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
-  * @{
-  */
-#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_CLK_Division FMC CLK Division 
-  * @{
-  */
-#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
-  * @{
-  */
-#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
-  * @}
-  */
-  
-/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
-  * @{
-  */
-#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
-  * @}
-  */ 
-     
-/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
-  * @{
-  */  
-#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
-/**
-  * @}
-  */
-  
-/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
-  * @{
-  */  
-#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
-  * @}
-  */  
-  
-/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
-  * @{
-  */  
-#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
-/**
-  * @}
-  */         
-  
-/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
-  * @{
-  */  
-#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
-  * @}
-  */ 
-  
-/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
-  * @{
-  */  
-#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
-  * @}
-  */
-  
-/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
-  * @{
-  */  
-#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
-  * @{
-  */
-#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
-  * @{
-  */
-#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
-/**
-  * @}
-  */
-  
-/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
-  * @{
-  */
-#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
-  * @{
-  */
-#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
-/**
-  * @}
-  */
-  
-/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
-  * @{
-  */
-#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
-  * @{
-  */
-#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
-/**
-  * @}
-  */
-
-#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
-                                 ((BANK) == FMC_SDRAM_BANK2))
-
-#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8)  || \
-                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9)  || \
-                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
-                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
-
-#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
-                                    ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
-                                    ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
-
-#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
-                                            ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
-
-
-#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
-                                     ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
-                                     ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
-
-#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
-                                   ((__SIZE__) == FMC_PAGE_SIZE_128) || \
-                                   ((__SIZE__) == FMC_PAGE_SIZE_256) || \
-                                   ((__SIZE__) == FMC_PAGE_SIZE_1024))
-
-#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
-                                     ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
-/**
-  * @}
-  */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
-  * @{
-  */
-#define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef
-#define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef
-#define FMC_NAND_TypeDef               FMC_Bank3_TypeDef
-#define FMC_SDRAM_TypeDef              FMC_Bank5_6_TypeDef
-
-#define FMC_NORSRAM_DEVICE             FMC_Bank1
-#define FMC_NORSRAM_EXTENDED_DEVICE    FMC_Bank1E
-#define FMC_NAND_DEVICE                FMC_Bank3
-#define FMC_SDRAM_DEVICE               FMC_Bank5_6
-
-/** 
-  * @brief  FMC NORSRAM Configuration Structure definition
-  */ 
-typedef struct
-{
-  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
-                                              This parameter can be a value of @ref FMC_NORSRAM_Bank                     */
-
-  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
-                                              multiplexed on the data bus or not. 
-                                              This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing    */
-
-  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
-                                              the corresponding memory device.
-                                              This parameter can be a value of @ref FMC_Memory_Type                      */
-
-  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
-                                              This parameter can be a value of @ref FMC_NORSRAM_Data_Width               */
-
-  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
-                                              valid only with synchronous burst Flash memories.
-                                              This parameter can be a value of @ref FMC_Burst_Access_Mode                */
-
-  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
-                                              the Flash memory in burst mode.
-                                              This parameter can be a value of @ref FMC_Wait_Signal_Polarity             */
-
-  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
-                                              clock cycle before the wait state or during the wait state,
-                                              valid only when accessing memories in burst mode. 
-                                              This parameter can be a value of @ref FMC_Wait_Timing                      */
-
-  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC. 
-                                              This parameter can be a value of @ref FMC_Write_Operation                  */
-
-  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
-                                              signal, valid for Flash memory access in burst mode. 
-                                              This parameter can be a value of @ref FMC_Wait_Signal                      */
-
-  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
-                                              This parameter can be a value of @ref FMC_Extended_Mode                    */
-
-  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
-                                              valid only with asynchronous Flash memories.
-                                              This parameter can be a value of @ref FMC_AsynchronousWait                 */
-
-  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
-                                              This parameter can be a value of @ref FMC_Write_Burst                      */
-
-  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
-                                              This parameter is only enabled through the FMC_BCR1 register, and don't care 
-                                              through FMC_BCR2..4 registers.
-                                              This parameter can be a value of @ref FMC_Continous_Clock                  */
-
-  uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FMC controller.
-                                              This parameter is only enabled through the FMC_BCR1 register, and don't care 
-                                              through FMC_BCR2..4 registers.
-                                              This parameter can be a value of @ref FMC_Write_FIFO                      */
-
-  uint32_t PageSize;                     /*!< Specifies the memory page size.
-                                              This parameter can be a value of @ref FMC_Page_Size                        */
-
-}FMC_NORSRAM_InitTypeDef;
-
-/** 
-  * @brief  FMC NORSRAM Timing parameters structure definition  
-  */
-typedef struct
-{
-  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the address setup time. 
-                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
-                                              @note This parameter is not used with synchronous NOR Flash memories.      */
-
-  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the address hold time.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15. 
-                                              @note This parameter is not used with synchronous NOR Flash memories.      */
-
-  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the data setup time.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
-                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 
-                                              NOR Flash memories.                                                        */
-
-  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the bus turnaround.
-                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
-                                              @note This parameter is only used for multiplexed NOR Flash memories.      */
-
-  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of 
-                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
-                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 
-                                              accesses.                                                                  */
-
-  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
-                                              to the memory before getting the first data.
-                                              The parameter value depends on the memory type as shown below:
-                                              - It must be set to 0 in case of a CRAM
-                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
-                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
-                                                with synchronous burst mode enable                                       */
-
-  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode. 
-                                              This parameter can be a value of @ref FMC_Access_Mode                      */
-}FMC_NORSRAM_TimingTypeDef;
-
-/** 
-  * @brief  FMC NAND Configuration Structure definition  
-  */ 
-typedef struct
-{
-  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
-                                        This parameter can be a value of @ref FMC_NAND_Bank                    */
-
-  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
-                                        This parameter can be any value of @ref FMC_Wait_feature               */
-
-  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
-                                        This parameter can be any value of @ref FMC_NAND_Data_Width            */
-
-  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
-                                        This parameter can be any value of @ref FMC_ECC                        */
-
-  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
-                                        This parameter can be any value of @ref FMC_ECC_Page_Size              */
-
-  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
-                                        delay between CLE low and RE low.
-                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
-
-  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
-                                        delay between ALE low and RE low.
-                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-}FMC_NAND_InitTypeDef;
-
-/** 
-  * @brief  FMC NAND Timing parameters structure definition
-  */
-typedef struct
-{
-  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
-                                      the command assertion for NAND-Flash read or write access
-                                      to common/Attribute or I/O memory space (depending on
-                                      the memory space timing to be configured).
-                                      This parameter can be a value between Min_Data = 0 and Max_Data = 254    */
-
-  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
-                                      command for NAND-Flash read or write access to
-                                      common/Attribute or I/O memory space (depending on the
-                                      memory space timing to be configured). 
-                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
-
-  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
-                                      (and data for write access) after the command de-assertion
-                                      for NAND-Flash read or write access to common/Attribute
-                                      or I/O memory space (depending on the memory space timing
-                                      to be configured).
-                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
-
-  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
-                                      data bus is kept in HiZ after the start of a NAND-Flash
-                                      write access to common/Attribute or I/O memory space (depending
-                                      on the memory space timing to be configured).
-                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
-}FMC_NAND_PCC_TimingTypeDef;
-
-/** 
-  * @brief  FMC SDRAM Configuration Structure definition  
-  */  
-typedef struct
-{
-  uint32_t SDBank;                      /*!< Specifies the SDRAM memory device that will be used.
-                                             This parameter can be a value of @ref FMC_SDRAM_Bank                */
-
-  uint32_t ColumnBitsNumber;            /*!< Defines the number of bits of column address.
-                                             This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
-
-  uint32_t RowBitsNumber;               /*!< Defines the number of bits of column address.
-                                             This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number.    */
-
-  uint32_t MemoryDataWidth;             /*!< Defines the memory device width.
-                                             This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width.   */
-
-  uint32_t InternalBankNumber;          /*!< Defines the number of the device's internal banks.
-                                             This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number.      */
-
-  uint32_t CASLatency;                  /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
-                                             This parameter can be a value of @ref FMC_SDRAM_CAS_Latency.        */
-
-  uint32_t WriteProtection;             /*!< Enables the SDRAM device to be accessed in write mode.
-                                             This parameter can be a value of @ref FMC_SDRAM_Write_Protection.   */
-
-  uint32_t SDClockPeriod;               /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow 
-                                             to disable the clock before changing frequency.
-                                             This parameter can be a value of @ref FMC_SDRAM_Clock_Period.       */
-
-  uint32_t ReadBurst;                   /*!< This bit enable the SDRAM controller to anticipate the next read 
-                                             commands during the CAS latency and stores data in the Read FIFO.
-                                             This parameter can be a value of @ref FMC_SDRAM_Read_Burst.         */
-
-  uint32_t ReadPipeDelay;               /*!< Define the delay in system clock cycles on read data path.
-                                             This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay.    */
-}FMC_SDRAM_InitTypeDef;
-
-/** 
-  * @brief FMC SDRAM Timing parameters structure definition
-  */
-typedef struct
-{
-  uint32_t LoadToActiveDelay;            /*!< Defines the delay between a Load Mode Register command and 
-                                              an active or Refresh command in number of memory clock cycles.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
-
-  uint32_t ExitSelfRefreshDelay;         /*!< Defines the delay from releasing the self refresh command to 
-                                              issuing the Activate command in number of memory clock cycles.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
-
-  uint32_t SelfRefreshTime;              /*!< Defines the minimum Self Refresh period in number of memory clock 
-                                              cycles.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
-
-  uint32_t RowCycleDelay;                /*!< Defines the delay between the Refresh command and the Activate command
-                                              and the delay between two consecutive Refresh commands in number of 
-                                              memory clock cycles.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
-
-  uint32_t WriteRecoveryTime;            /*!< Defines the Write recovery Time in number of memory clock cycles.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
-
-  uint32_t RPDelay;                      /*!< Defines the delay between a Precharge Command and an other command 
-                                              in number of memory clock cycles.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
-
-  uint32_t RCDDelay;                     /*!< Defines the delay between the Activate Command and a Read/Write 
-                                              command in number of memory clock cycles.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */ 
-}FMC_SDRAM_TimingTypeDef;
-
-/** 
-  * @brief SDRAM command parameters structure definition
-  */
-typedef struct
-{
-  uint32_t CommandMode;                  /*!< Defines the command issued to the SDRAM device.
-                                              This parameter can be a value of @ref FMC_SDRAM_Command_Mode.          */
-
-  uint32_t CommandTarget;                /*!< Defines which device (1 or 2) the command will be issued to.
-                                              This parameter can be a value of @ref FMC_SDRAM_Command_Target.        */
-
-  uint32_t AutoRefreshNumber;            /*!< Defines the number of consecutive auto refresh command issued
-                                              in auto refresh mode.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16   */
-  uint32_t ModeRegisterDefinition;       /*!< Defines the SDRAM Mode register content                                */
-}FMC_SDRAM_CommandTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
-  * @{
-  */
-
-/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 
-  * @{
-  */
-
-/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
-  * @{
-  */
-#define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
-#define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
-#define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
-#define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
-  * @{
-  */
-#define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
-#define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Memory_Type FMC Memory Type
-  * @{
-  */
-#define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
-#define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)0x00000004)
-#define FMC_MEMORY_TYPE_NOR                     ((uint32_t)0x00000008)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
-  * @{
-  */
-#define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
-  * @{
-  */
-#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)0x00000040)
-#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
-  * @{
-  */
-#define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000) 
-#define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)0x00000100)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
-  * @{
-  */
-#define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)0x00000200)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Wait_Timing FMC Wait Timing
-  * @{
-  */
-#define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
-#define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)0x00000800) 
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Write_Operation FMC Write Operation
-  * @{
-  */
-#define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
-#define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)0x00001000)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Wait_Signal FMC Wait Signal
-  * @{
-  */
-#define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)0x00002000)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Extended_Mode FMC Extended Mode
-  * @{
-  */
-#define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
-#define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)0x00004000)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
-  * @{
-  */
-#define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
-#define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)0x00008000)
-/**
-  * @}
-  */  
-
-/** @defgroup FMC_Page_Size FMC Page Size
-  * @{
-  */
-#define FMC_PAGE_SIZE_NONE           ((uint32_t)0x00000000)
-#define FMC_PAGE_SIZE_128            ((uint32_t)FMC_BCR1_CPSIZE_0)
-#define FMC_PAGE_SIZE_256            ((uint32_t)FMC_BCR1_CPSIZE_1)
-#define FMC_PAGE_SIZE_1024           ((uint32_t)FMC_BCR1_CPSIZE_2)
-/**
-  * @}
-  */  
-
-/** @defgroup FMC_Write_Burst FMC Write Burst
-  * @{
-  */
-#define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
-#define FMC_WRITE_BURST_ENABLE                  ((uint32_t)0x00080000) 
-/**
-  * @}
-  */
-  
-/** @defgroup FMC_Continous_Clock FMC Continuous Clock
-  * @{
-  */
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000)
-/**
-  * @}
-  */ 
-
-/** @defgroup FMC_Write_FIFO FMC Write FIFO 
-  * @{
-  */
-#define FMC_WRITE_FIFO_DISABLE           ((uint32_t)0x00000000)
-#define FMC_WRITE_FIFO_ENABLE            ((uint32_t)FMC_BCR1_WFDIS)
-/**
-  * @}
-  */
-	
-/** @defgroup FMC_Access_Mode FMC Access Mode 
-  * @{
-  */
-#define FMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
-#define FMC_ACCESS_MODE_B                        ((uint32_t)0x10000000) 
-#define FMC_ACCESS_MODE_C                        ((uint32_t)0x20000000)
-#define FMC_ACCESS_MODE_D                        ((uint32_t)0x30000000)
-/**
-  * @}
-  */
-    
-/**
-  * @}
-  */ 
-
-/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 
-  * @{
-  */
-/** @defgroup FMC_NAND_Bank FMC NAND Bank 
-  * @{
-  */
-#define FMC_NAND_BANK3                          ((uint32_t)0x00000100) 
-/**
-  * @}
-  */
-
-/** @defgroup FMC_Wait_feature FMC Wait feature
-  * @{
-  */
-#define FMC_NAND_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
-#define FMC_NAND_WAIT_FEATURE_ENABLE            ((uint32_t)0x00000002)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 
-  * @{
-  */
-#define FMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)0x00000008)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 
-  * @{
-  */
-#define FMC_NAND_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
-#define FMC_NAND_MEM_BUS_WIDTH_16               ((uint32_t)0x00000010)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_ECC FMC ECC 
-  * @{
-  */
-#define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_ENABLE                     ((uint32_t)0x00000040)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 
-  * @{
-  */
-#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)0x00020000)
-#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)0x00040000)
-#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)0x00060000)
-#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)0x00080000)
-#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)0x000A0000)
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller 
-  * @{
-  */
-/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
-  * @{
-  */
-#define FMC_SDRAM_BANK1                       ((uint32_t)0x00000000)
-#define FMC_SDRAM_BANK2                       ((uint32_t)0x00000001)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number 
-  * @{
-  */
-#define FMC_SDRAM_COLUMN_BITS_NUM_8           ((uint32_t)0x00000000)
-#define FMC_SDRAM_COLUMN_BITS_NUM_9           ((uint32_t)0x00000001)
-#define FMC_SDRAM_COLUMN_BITS_NUM_10          ((uint32_t)0x00000002)
-#define FMC_SDRAM_COLUMN_BITS_NUM_11          ((uint32_t)0x00000003)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
-  * @{
-  */
-#define FMC_SDRAM_ROW_BITS_NUM_11             ((uint32_t)0x00000000)
-#define FMC_SDRAM_ROW_BITS_NUM_12             ((uint32_t)0x00000004)
-#define FMC_SDRAM_ROW_BITS_NUM_13             ((uint32_t)0x00000008)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
-  * @{
-  */
-#define FMC_SDRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
-#define FMC_SDRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010)
-#define FMC_SDRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
-  * @{
-  */
-#define FMC_SDRAM_INTERN_BANKS_NUM_2          ((uint32_t)0x00000000)
-#define FMC_SDRAM_INTERN_BANKS_NUM_4          ((uint32_t)0x00000040)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
-  * @{
-  */
-#define FMC_SDRAM_CAS_LATENCY_1               ((uint32_t)0x00000080)
-#define FMC_SDRAM_CAS_LATENCY_2               ((uint32_t)0x00000100)
-#define FMC_SDRAM_CAS_LATENCY_3               ((uint32_t)0x00000180)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
-  * @{
-  */
-#define FMC_SDRAM_WRITE_PROTECTION_DISABLE    ((uint32_t)0x00000000)
-#define FMC_SDRAM_WRITE_PROTECTION_ENABLE     ((uint32_t)0x00000200)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
-  * @{
-  */
-#define FMC_SDRAM_CLOCK_DISABLE               ((uint32_t)0x00000000)
-#define FMC_SDRAM_CLOCK_PERIOD_2              ((uint32_t)0x00000800)
-#define FMC_SDRAM_CLOCK_PERIOD_3              ((uint32_t)0x00000C00)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
-  * @{
-  */
-#define FMC_SDRAM_RBURST_DISABLE              ((uint32_t)0x00000000)
-#define FMC_SDRAM_RBURST_ENABLE               ((uint32_t)0x00001000)
-/**
-  * @}
-  */
-  
-/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
-  * @{
-  */
-#define FMC_SDRAM_RPIPE_DELAY_0               ((uint32_t)0x00000000)
-#define FMC_SDRAM_RPIPE_DELAY_1               ((uint32_t)0x00002000)
-#define FMC_SDRAM_RPIPE_DELAY_2               ((uint32_t)0x00004000)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
-  * @{
-  */
-#define FMC_SDRAM_CMD_NORMAL_MODE             ((uint32_t)0x00000000)
-#define FMC_SDRAM_CMD_CLK_ENABLE              ((uint32_t)0x00000001)
-#define FMC_SDRAM_CMD_PALL                    ((uint32_t)0x00000002)
-#define FMC_SDRAM_CMD_AUTOREFRESH_MODE        ((uint32_t)0x00000003)
-#define FMC_SDRAM_CMD_LOAD_MODE               ((uint32_t)0x00000004)
-#define FMC_SDRAM_CMD_SELFREFRESH_MODE        ((uint32_t)0x00000005)
-#define FMC_SDRAM_CMD_POWERDOWN_MODE          ((uint32_t)0x00000006)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
-  * @{
-  */
-#define FMC_SDRAM_CMD_TARGET_BANK2            FMC_SDCMR_CTB2
-#define FMC_SDRAM_CMD_TARGET_BANK1            FMC_SDCMR_CTB1
-#define FMC_SDRAM_CMD_TARGET_BANK1_2          ((uint32_t)0x00000018)
-/**
-  * @}
-  */
-
-/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status 
-  * @{
-  */
-#define FMC_SDRAM_NORMAL_MODE                     ((uint32_t)0x00000000)
-#define FMC_SDRAM_SELF_REFRESH_MODE               FMC_SDSR_MODES1_0
-#define FMC_SDRAM_POWER_DOWN_MODE                 FMC_SDSR_MODES1_1
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition  
-  * @{
-  */  
-#define FMC_IT_RISING_EDGE                ((uint32_t)0x00000008)
-#define FMC_IT_LEVEL                      ((uint32_t)0x00000010)
-#define FMC_IT_FALLING_EDGE               ((uint32_t)0x00000020)
-#define FMC_IT_REFRESH_ERROR              ((uint32_t)0x00004000)
-/**
-  * @}
-  */
-    
-/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 
-  * @{
-  */ 
-#define FMC_FLAG_RISING_EDGE                    ((uint32_t)0x00000001)
-#define FMC_FLAG_LEVEL                          ((uint32_t)0x00000002)
-#define FMC_FLAG_FALLING_EDGE                   ((uint32_t)0x00000004)
-#define FMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
-#define FMC_SDRAM_FLAG_REFRESH_IT               FMC_SDSR_RE
-#define FMC_SDRAM_FLAG_BUSY                     FMC_SDSR_BUSY
-#define FMC_SDRAM_FLAG_REFRESH_ERROR            FMC_SDRTR_CRE
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FMC_LL_Private_Macros FMC_LL  Private Macros
-  * @{
-  */
-
-/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
- *  @brief macros to handle NOR device enable/disable and read/write operations
- *  @{
- */
- 
-/**
-  * @brief  Enable the NORSRAM device access.
-  * @param  __INSTANCE__: FMC_NORSRAM Instance
-  * @param  __BANK__: FMC_NORSRAM Bank     
-  * @retval None
-  */ 
-#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
-
-/**
-  * @brief  Disable the NORSRAM device access.
-  * @param  __INSTANCE__: FMC_NORSRAM Instance
-  * @param  __BANK__: FMC_NORSRAM Bank   
-  * @retval None
-  */ 
-#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)  
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
- *  @brief macros to handle NAND device enable/disable
- *  @{
- */
- 
-/**
-  * @brief  Enable the NAND device access.
-  * @param  __INSTANCE__: FMC_NAND Instance    
-  * @retval None
-  */  
-#define __FMC_NAND_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
-
-/**
-  * @brief  Disable the NAND device access.
-  * @param  __INSTANCE__: FMC_NAND Instance  
-  * @retval None
-  */
-#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
-
-/**
-  * @}
-  */ 
-    
-/** @defgroup FMC_Interrupt FMC Interrupt
- *  @brief macros to handle FMC interrupts
- * @{
- */ 
-
-/**
-  * @brief  Enable the NAND device interrupt.
-  * @param  __INSTANCE__:  FMC_NAND instance     
-  * @param  __INTERRUPT__: FMC_NAND interrupt 
-  *         This parameter can be any combination of the following values:
-  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
-  *            @arg FMC_IT_LEVEL: Interrupt level.
-  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.       
-  * @retval None
-  */  
-#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the NAND device interrupt.
-  * @param  __INSTANCE__:  FMC_NAND Instance
-  * @param  __INTERRUPT__: FMC_NAND interrupt
-  *         This parameter can be any combination of the following values:
-  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
-  *            @arg FMC_IT_LEVEL: Interrupt level.
-  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.   
-  * @retval None
-  */
-#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
-                                                                                                                           
-/**
-  * @brief  Get flag status of the NAND device.
-  * @param  __INSTANCE__: FMC_NAND Instance
-  * @param  __BANK__:     FMC_NAND Bank     
-  * @param  __FLAG__: FMC_NAND flag
-  *         This parameter can be any combination of the following values:
-  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
-  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
-  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
-  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.   
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear flag status of the NAND device.
-  * @param  __INSTANCE__: FMC_NAND Instance   
-  * @param  __FLAG__: FMC_NAND flag
-  *         This parameter can be any combination of the following values:
-  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
-  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
-  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
-  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.   
-  * @retval None
-  */
-#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR &= ~(__FLAG__))  
-
-/**
-  * @brief  Enable the SDRAM device interrupt.
-  * @param  __INSTANCE__: FMC_SDRAM instance  
-  * @param  __INTERRUPT__: FMC_SDRAM interrupt 
-  *         This parameter can be any combination of the following values:
-  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error      
-  * @retval None
-  */
-#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SDRAM device interrupt.
-  * @param  __INSTANCE__: FMC_SDRAM instance  
-  * @param  __INTERRUPT__: FMC_SDRAM interrupt 
-  *         This parameter can be any combination of the following values:
-  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error      
-  * @retval None
-  */
-#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Get flag status of the SDRAM device.
-  * @param  __INSTANCE__: FMC_SDRAM instance  
-  * @param  __FLAG__: FMC_SDRAM flag
-  *         This parameter can be any combination of the following values:
-  *            @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
-  *            @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
-  *            @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear flag status of the SDRAM device.
-  * @param  __INSTANCE__: FMC_SDRAM instance  
-  * @param  __FLAG__: FMC_SDRAM flag
-  *         This parameter can be any combination of the following values:
-  *           @arg FMC_SDRAM_FLAG_REFRESH_ERROR
-  * @retval None
-  */
-#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SDRTR |= (__FLAG__))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
-  *  @{
-  */
-
-/** @defgroup FMC_LL_NORSRAM  NOR SRAM
-  *  @{
-  */
-/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 
-  *  @{
-  */
-HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
-/**
-  * @}
-  */ 
-
-/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 
-  *  @{
-  */
-HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/** @defgroup FMC_LL_NAND NAND
-  *  @{
-  */
-/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 
-  *  @{
-  */
-HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
-/**
-  * @}
-  */
-
-/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 
-  *  @{
-  */
-HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @defgroup FMC_LL_SDRAM SDRAM
-  *  @{
-  */
-/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions 
-  *  @{
-  */
-HAL_StatusTypeDef  FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
-HAL_StatusTypeDef  FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-
-/**
-  * @}
-  */
-
-/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions 
-  *  @{
-  */
-HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef  FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
-HAL_StatusTypeDef  FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
-HAL_StatusTypeDef  FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
-uint32_t           FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_LL_FMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/gos/gos_chibios.c b/src/gos/gos_chibios.c
index eb839dc6..d650caa0 100644
--- a/src/gos/gos_chibios.c
+++ b/src/gos/gos_chibios.c
@@ -158,13 +158,13 @@ gfxThreadHandle gfxThreadCreate(void *stackarea, size_t stacksz, threadpriority_
 {
 	if (!stackarea) {
 		if (!stacksz) stacksz = 256;
-		return chThdCreateFromHeap(0, stacksz, prio, fn, param);
+		return chThdCreateFromHeap(0, stacksz, prio, (tfunc_t)fn, param);
 	}
 
 	if (!stacksz)
 		return 0;
 
-	return chThdCreateStatic(stackarea, stacksz, prio, fn, param);
+	return chThdCreateStatic(stackarea, stacksz, prio, (tfunc_t)fn, param);
 }
 
 #endif /* GFX_USE_OS_CHIBIOS */