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path: root/protocol/ps2_io_mbed.c
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#include <stdbool.h>
#include "ps2_io.h"
#include "gpio_api.h"


static gpio_t clock;
static gpio_t data;

/*
 * Clock
 */
void clock_init(void)
{
    gpio_init(&clock, P0_9);
    gpio_mode(&clock, OpenDrain|PullNone);
}

void clock_lo(void)
{
    gpio_dir(&clock, PIN_OUTPUT);
    gpio_write(&clock, 0);
}
void clock_hi(void)
{
    gpio_dir(&clock, PIN_OUTPUT);
    gpio_write(&clock, 1);
}

bool clock_in(void)
{
    gpio_dir(&clock, PIN_INPUT);
    return gpio_read(&clock);
}

/*
 * Data
 */
void data_init(void)
{
    gpio_init(&data, P0_8);
    gpio_mode(&data, OpenDrain|PullNone);
}

void data_lo(void)
{
    gpio_dir(&data, PIN_OUTPUT);
    gpio_write(&data, 0);
}

void data_hi(void)
{
    gpio_dir(&data, PIN_OUTPUT);
    gpio_write(&data, 1);
}

bool data_in(void)
{
    gpio_dir(&data, PIN_INPUT);
    return gpio_read(&data);
}
class="o">@0 { status = "okay"; label = "eth0"; }; port@1 { status = "okay"; label = "eth1"; mtd-mac-address = <&factory 0x22>; mtd-mac-address-increment = <1>; }; port@2 { status = "okay"; label = "eth2"; mtd-mac-address = <&factory 0x22>; mtd-mac-address-increment = <2>; }; port@3 { status = "okay"; label = "eth3"; mtd-mac-address = <&factory 0x22>; mtd-mac-address-increment = <3>; }; port@4 { status = "okay"; label = "eth4"; mtd-mac-address = <&factory 0x22>; mtd-mac-address-increment = <4>; }; }; }; &nand { status = "okay"; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "u-boot"; reg = <0x0 0x80000>; read-only; }; partition@80000 { label = "u-boot-env"; reg = <0x80000 0x60000>; read-only; }; factory: partition@e0000 { label = "factory"; reg = <0xe0000 0x60000>; }; partition@140000 { label = "kernel1"; reg = <0x140000 0x300000>; }; partition@440000 { label = "kernel2"; reg = <0x440000 0x300000>; }; partition@740000 { label = "ubi"; reg = <0x740000 0xf7c0000>; }; }; }; &state_default { gpio { groups = "uart2", "uart3", "pcie", "rgmii2", "jtag"; function = "gpio"; }; }; &spi0 { /* * This board has 2Mb spi flash soldered in and visible * from manufacturer's firmware. * But this SoC shares spi and nand pins, * and current driver doesn't handle this sharing well */ status = "disabled"; flash@1 { compatible = "jedec,spi-nor"; reg = <1>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi"; reg = <0x0 0x200000>; read-only; }; }; }; }; &xhci { status = "disabled"; };