library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity p_jinfo_ac_dhuff_tbl_ml is port ( wa0_data : in std_logic_vector(31 downto 0); wa0_addr : in std_logic; clk : in std_logic; ra0_addr : in std_logic; ra0_data : out std_logic_vector(31 downto 0); wa0_en : in std_logic ); end p_jinfo_ac_dhuff_tbl_ml; architecture augh of p_jinfo_ac_dhuff_tbl_ml is -- Embedded RAM type ram_type is array (0 to 1) of std_logic_vector(31 downto 0); signal ram : ram_type := (others => (others => '0')); -- Little utility functions to make VHDL syntactically correct -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. -- This happens when accessing arrays with <= 2 cells, for example. function to_integer(B: std_logic) return integer is variable V: std_logic_vector(0 to 0); begin V(0) := B; return to_integer(unsigned(V)); end; function to_integer(V: std_logic_vector) return integer is begin return to_integer(unsigned(V)); end; begin -- Sequential process -- It handles the Writes process (clk) begin if rising_edge(clk) then -- Write to the RAM -- Note: there should be only one port. if wa0_en = '1' then ram( to_integer(wa0_addr) ) <= wa0_data; end if; end if; end process; -- The Read side (the outputs) ra0_data <= ram( to_integer(ra0_addr) ); end architecture; >refslogtreecommitdiffstats
path: root/lib/lufa/Projects/Webserver/Lib/uip/clock.c
blob: e71f7209d2c45fd1c2abf19a4c6498d88c3611ee (plain) 
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#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>

#include <LUFA/Common/Common.h>

#include "clock.h"

//Counted time
volatile clock_time_t clock_datetime = 0;

//Overflow interrupt
ISR(TIMER1_COMPA_vect, ISR_BLOCK)
{
	clock_datetime += 1;
}

//Initialise the clock
void clock_init()
{
	OCR1A  = (((F_CPU / 1024) / 100) - 1);
	TCCR1B = ((1 << WGM12) | (1 << CS12) | (1 << CS10));
	TIMSK1 = (1 << OCIE1A);
}

//Return time
clock_time_t clock_time()
{
	clock_time_t time;

	GlobalInterruptDisable();
	time = clock_datetime;
	GlobalInterruptEnable();

	return time;
}
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