aboutsummaryrefslogtreecommitdiffstats
path: root/lib/lufa/Demos/Device/LowLevel/DualVirtualSerial/makefile
blob: c91ec4f880120f5dc8dc3edf072d76073b166214 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
#
#             LUFA Library
#     Copyright (C) Dean Camera, 2017.
#
#  dean [at] fourwalledcubicle [dot] com
#           www.lufa-lib.org
#
# --------------------------------------
#         LUFA Project Makefile.
# --------------------------------------

# Run "make help" for target help.

MCU          = at90usb1287
ARCH         = AVR8
BOARD        = USBKEY
F_CPU        = 8000000
F_USB        = $(F_CPU)
OPTIMIZATION = s
TARGET       = DualVirtualSerial
SRC          = $(TARGET).c Descriptors.c $(LUFA_SRC_USB)
LUFA_PATH    = ../../../../LUFA
CC_FLAGS     = -DUSE_LUFA_CONFIG_HEADER -IConfig/
LD_FLAGS     =

# Default target
all:

# Include LUFA-specific DMBS extension modules
DMBS_LUFA_PATH ?= $(LUFA_PATH)/Build/LUFA
include $(DMBS_LUFA_PATH)/lufa-sources.mk
include $(DMBS_LUFA_PATH)/lufa-gcc.mk

# Include common DMBS build system modules
DMBS_PATH      ?= $(LUFA_PATH)/Build/DMBS/DMBS
include $(DMBS_PATH)/core.mk
include $(DMBS_PATH)/cppcheck.mk
include $(DMBS_PATH)/doxygen.mk
include $(DMBS_PATH)/dfu.mk
include $(DMBS_PATH)/gcc.mk
include $(DMBS_PATH)/hid.mk
include $(DMBS_PATH)/avrdude.mk
include $(DMBS_PATH)/atprogram.mk
pan class="o">= "ALTERNATE"; parameter clock_enable_input_a = "ALTERNATE"; parameter clock_enable_output_b = "NORMAL"; parameter clock_enable_output_a = "NORMAL"; parameter wrcontrol_aclr_a = "NONE"; parameter indata_aclr_a = "NONE"; parameter address_aclr_a = "NONE"; parameter outdata_aclr_a = "NONE"; parameter outdata_reg_a = "UNREGISTERED"; parameter operation_mode = "SINGLE_PORT"; parameter intended_device_family = "MAX 10 FPGA"; parameter outdata_reg_a = "UNREGISTERED"; parameter lpm_type = "altsyncram"; parameter init_type = "unused"; parameter ram_block_type = "AUTO"; parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO"; parameter power_up_uninitialized = "FALSE"; parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ"; parameter width_byteena_a = 1; parameter numwords_b = 0; parameter numwords_a = 0; parameter widthad_b = 1; parameter width_b = 1; parameter widthad_a = 1; parameter width_a = 1; // Port A declarations output [35:0] q_a; input [35:0] data_a; input [7:0] address_a; input wren_a; input rden_a; // Port B declarations output [35:0] q_b; input [35:0] data_b; input [7:0] address_b; input wren_b; input rden_b; // Control signals input clock0, clock1; input clocken0, clocken1, clocken2, clocken3; input aclr0, aclr1; input addressstall_a; input addressstall_b; // TODO: Implement the correct simulation model endmodule // altsyncram