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author	Andrew Kannan <andrew.kannan@klaviyo.com>	2020-04-12 06:36:03 -0400
committer	GitHub <noreply@github.com>	2020-04-12 03:36:03 -0700
commit	799b21f8cd6546811652deae23424a3fa603e9b5 (patch)
tree	f3ee7b34bf7078e7c5b48c0901b430164c15025f /shell.nix
parent	750179e111dfa35d8023fe9ef785dcbef24f1e55 (diff)
download	firmware-799b21f8cd6546811652deae23424a3fa603e9b5.tar.gz firmware-799b21f8cd6546811652deae23424a3fa603e9b5.tar.bz2 firmware-799b21f8cd6546811652deae23424a3fa603e9b5.zip

[Keyboard] Add CannonKeys Rekt1800 keyboard (#7760)

* Add Rekt1800 keyboards * Update keyboards/cannonkeys/rekt1800/config.h * Update keyboards/cannonkeys/rekt1800/info.json * Apply suggestions from code review * Apply suggestions from code review * Remove line * Apply suggestions from code review

Diffstat (limited to 'shell.nix')

0 files changed, 0 insertions, 0 deletions

eral.Number.Bin */ .highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */ .highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */ .highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */ .highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */ .highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */ .highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */ .highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */ .highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */ .highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */ .highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */ .highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */ .highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */ .highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */ .highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */ .highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */ .highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */ .highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */ .highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */ .highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */ .highlight .vc { color: #336699 } /* Name.Variable.Class */ .highlight .vg { color: #dd7700 } /* Name.Variable.Global */ .highlight .vi { color: #3333bb } /* Name.Variable.Instance */ .highlight .vm { color: #336699 } /* Name.Variable.Magic */ .highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */

// http://www.reddit.com/r/yosys/comments/1vljks/new_support_for_systemveriloglike_asserts/
module test(input clk, input rst, output y);
reg [2:0] state;
always @(posedge clk) begin
    if (rst || state == 3) begin
        state <= 0;
    end else begin
        assert(state < 3);
        state <= state + 1;
    end
end
assign y = state[2];
assert property (y !== 1'b1);
endmodule


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