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path: root/testhal/STM32/STM32F0xx/SPI/main.c
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/*
    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

#include "ch.h"
#include "hal.h"

/*
 * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).
 */
static const SPIConfig hs_spicfg = {
  NULL,
  GPIOB,
  12,
  0,
  SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
};

/*
 * Low speed SPI configuration (140.625kHz, CPHA=0, CPOL=0, MSb first).
 */
static const SPIConfig ls_spicfg = {
  NULL,
  GPIOB,
  12,
  SPI_CR1_BR_2 | SPI_CR1_BR_1,
  SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
};

/*
 * SPI TX and RX buffers.
 */
static uint8_t txbuf[512];
static uint8_t rxbuf[512];

/*
 * SPI bus contender 1.
 */
static THD_WORKING_AREA(spi_thread_1_wa, 256);
static msg_t spi_thread_1(void *p) {

  (void)p;
  chRegSetThreadName("SPI thread 1");
  while (TRUE) {
    spiAcquireBus(&SPID2);              /* Acquire ownership of the bus.    */
    palSetPad(GPIOC, GPIOC_LED4);       /* LED ON.                          */
    spiStart(&SPID2, &hs_spicfg);       /* Setup transfer parameters.       */
    spiSelect(&SPID2);                  /* Slave Select assertion.          */
    spiExchange(&SPID2, 512,
                txbuf, rxbuf);          /* Atomic transfer operations.      */
    spiUnselect(&SPID2);                /* Slave Select de-assertion.       */
    spiReleaseBus(&SPID2);              /* Ownership release.               */
  }
  return 0;
}

/*
 * SPI bus contender 2.
 */
static THD_WORKING_AREA(spi_thread_2_wa, 256);
static msg_t spi_thread_2(void *p) {

  (void)p;
  chRegSetThreadName("SPI thread 2");
  while (TRUE) {
    spiAcquireBus(&SPID2);              /* Acquire ownership of the bus.    */
    palClearPad(GPIOC, GPIOC_LED4);     /* LED OFF.                         */
    spiStart(&SPID2, &ls_spicfg);       /* Setup transfer parameters.       */
    spiSelect(&SPID2);                  /* Slave Select assertion.          */
    spiExchange(&SPID2, 512,
                txbuf, rxbuf);          /* Atomic transfer operations.      */
    spiUnselect(&SPID2);                /* Slave Select de-assertion.       */
    spiReleaseBus(&SPID2);              /* Ownership release.               */
  }
  return 0;
}
/*
 * This is a periodic thread that does absolutely nothing except flashing
 * a LED.
 */
static THD_WORKING_AREA(blinker_wa, 128);
static msg_t blinker(void *arg) {

  (void)arg;
  chRegSetThreadName("blinker");
  while (TRUE) {
    palSetPad(GPIOC, GPIOC_LED3);
    chThdSleepMilliseconds(500);
    palClearPad(GPIOC, GPIOC_LED3);
    chThdSleepMilliseconds(500);
  }
}

/*
 * Application entry point.
 */
int main(void) {
  unsigned i;

  /*
   * System initializations.
   * - HAL initialization, this also initializes the configured device drivers
   *   and performs the board-specific initializations.
   * - Kernel initialization, the main() function becomes a thread and the
   *   RTOS is active.
   */
  halInit();
  chSysInit();

  /*
   * SPI2 I/O pins setup.
   */
  palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(0) |
                           PAL_STM32_OSPEED_HIGHEST);       /* New SCK.     */
  palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(0) |
                           PAL_STM32_OSPEED_HIGHEST);       /* New MISO.    */
  palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(0) |
                           PAL_STM32_OSPEED_HIGHEST);       /* New MOSI.    */
  palSetPad(GPIOB, 12);
  palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL |
                           PAL_STM32_OSPEED_HIGHEST);       /* New CS.      */

  /*
   * Prepare transmit pattern.
   */
  for (i = 0; i < sizeof(txbuf); i++)
    txbuf[i] = (uint8_t)i;

  /*
   * Starting the transmitter and receiver threads.
   */
  chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa),
                    NORMALPRIO + 1, spi_thread_1, NULL);
  chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa),
                    NORMALPRIO + 1, spi_thread_2, NULL);

  /*
   * Starting the blinker thread.
   */
  chThdCreateStatic(blinker_wa, sizeof(blinker_wa),
                    NORMALPRIO-1, blinker, NULL);

  /*
   * Normal main() thread activity, in this demo it does nothing.
   */
  while (TRUE) {
    chThdSleepMilliseconds(500);
  }
  return 0;
}
amp;& (s->cmos_data[RTC_REG_B] & REG_B_PIE)) { if (period_code <= 2) period_code += 7; /* period in 32 Khz cycles */ period = 1 << (period_code - 1); /* compute 32 khz clock */ cur_clock = muldiv64(current_time, 32768, ticks_per_sec); next_irq_clock = (cur_clock & ~(period - 1)) + period; s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1; qemu_mod_timer(s->periodic_timer, s->next_periodic_time); } else { qemu_del_timer(s->periodic_timer); } } static void rtc_periodic_timer(void *opaque) { RTCState *s = opaque; rtc_timer_update(s, s->next_periodic_time); s->cmos_data[RTC_REG_C] |= 0xc0; pic_set_irq(s->irq, 1); } static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) { RTCState *s = opaque; if ((addr & 1) == 0) { s->cmos_index = data & 0x7f; } else { #ifdef DEBUG_CMOS printf("cmos: write index=0x%02x val=0x%02x\n", s->cmos_index, data); #endif switch(s->cmos_index) { case RTC_SECONDS_ALARM: case RTC_MINUTES_ALARM: case RTC_HOURS_ALARM: /* XXX: not supported */ s->cmos_data[s->cmos_index] = data; break; case RTC_SECONDS: case RTC_MINUTES: case RTC_HOURS: case RTC_DAY_OF_WEEK: case RTC_DAY_OF_MONTH: case RTC_MONTH: case RTC_YEAR: s->cmos_data[s->cmos_index] = data; /* if in set mode, do not update the time */ if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { rtc_set_time(s); } break; case RTC_REG_A: /* UIP bit is read only */ s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); rtc_timer_update(s, qemu_get_clock(vm_clock)); break; case RTC_REG_B: if (data & REG_B_SET) { /* set mode: reset UIP mode */ s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; data &= ~REG_B_UIE; } else { /* if disabling set mode, update the time */ if (s->cmos_data[RTC_REG_B] & REG_B_SET) { rtc_set_time(s); } } s->cmos_data[RTC_REG_B] = data; rtc_timer_update(s, qemu_get_clock(vm_clock)); break; case RTC_REG_C: case RTC_REG_D: /* cannot write to them */ break; default: s->cmos_data[s->cmos_index] = data; break; } } } static inline int to_bcd(RTCState *s, int a) { if (s->cmos_data[RTC_REG_B] & 0x04) { return a; } else { return ((a / 10) << 4) | (a % 10); } } static inline int from_bcd(RTCState *s, int a) { if (s->cmos_data[RTC_REG_B] & 0x04) { return a; } else { return ((a >> 4) * 10) + (a & 0x0f); } } static void send_timeoffset_msg(time_t delta) { /* This routine is used to inform another entity that the base time offset has changed. For instance, if you were using xenstore, you might want to write to the store at this point. Or, you might use some other method. Whatever you might choose, here's a hook point to implement it. One item of note is that this delta is in addition to any existing offset you might be already using. */ return; } static void rtc_set_time(RTCState *s) { struct tm *tm = &s->current_tm; time_t before, after; before = mktime(tm); tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]); tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]); tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); if (!(s->cmos_data[RTC_REG_B] & 0x02) && (s->cmos_data[RTC_HOURS] & 0x80)) { tm->tm_hour += 12; } tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]); tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100; /* Compute, and send, the additional time delta We could compute the total time delta, but this is sufficient, and simple. */ after = mktime(tm); send_timeoffset_msg(after-before); } static void rtc_copy_date(RTCState *s) { const struct tm *tm = &s->current_tm; s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); if (s->cmos_data[RTC_REG_B] & 0x02) { /* 24 hour format */ s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour); } else { /* 12 hour format */ s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12); if (tm->tm_hour >= 12) s->cmos_data[RTC_HOURS] |= 0x80; } s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday); s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1); s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100); } /* month is between 0 and 11. */ static int get_days_in_month(int month, int year) { static const int days_tab[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; int d; if ((unsigned )month >= 12) return 31; d = days_tab[month]; if (month == 1) { if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) d++; } return d; } /* update 'tm' to the next second */ static void rtc_next_second(struct tm *tm) { int days_in_month; tm->tm_sec++; if ((unsigned)tm->tm_sec >= 60) { tm->tm_sec = 0; tm->tm_min++; if ((unsigned)tm->tm_min >= 60) { tm->tm_min = 0; tm->tm_hour++; if ((unsigned)tm->tm_hour >= 24) { tm->tm_hour = 0; /* next day */ tm->tm_wday++; if ((unsigned)tm->tm_wday >= 7) tm->tm_wday = 0; days_in_month = get_days_in_month(tm->tm_mon, tm->tm_year + 1900); tm->tm_mday++; if (tm->tm_mday < 1) { tm->tm_mday = 1; } else if (tm->tm_mday > days_in_month) { tm->tm_mday = 1; tm->tm_mon++; if (tm->tm_mon >= 12) { tm->tm_mon = 0; tm->tm_year++; } } } } } } static void rtc_update_second(void *opaque) { RTCState *s = opaque; int64_t delay; /* if the oscillator is not in normal operation, we do not update */ if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { s->next_second_time += ticks_per_sec; qemu_mod_timer(s->second_timer, s->next_second_time); } else { rtc_next_second(&s->current_tm); if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { /* update in progress bit */ s->cmos_data[RTC_REG_A] |= REG_A_UIP; } /* should be 244 us = 8 / 32768 seconds, but currently the timers do not have the necessary resolution. */ delay = (ticks_per_sec * 1) / 100; if (delay < 1) delay = 1; qemu_mod_timer(s->second_timer2, s->next_second_time + delay); } } static void rtc_update_second2(void *opaque) { RTCState *s = opaque; if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { rtc_copy_date(s);