aboutsummaryrefslogtreecommitdiffstats
path: root/test/testpools.c
blob: ce67164441c63522634054579434c5d8b5be9e62 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
/*
    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

#include <ch.h>

#include "test.h"

/**
 * @page test_pools Memory Pools test
 *
 * <h2>Description</h2>
 * This module implements the test sequence for the @ref MemoryPools subsystem.
 *
 * <h2>Objective</h2>
 * Objective of the test module is to cover 100% of the @ref MemoryPools
 * code as a necessary step in order to assess its maturity level.<br>
 *
 * <h2>Preconditions</h2>
 * The module requires the following kernel options:
 * - @p CH_USE_MEMPOOLS
 * .
 * In case some of the required options are not enabled then some or all tests
 * may be skipped.
 *
 * <h2>Test Cases</h2>
 * - @subpage test_pools_001
 * .
 * @file testpools.c
 * @brief Memory Pools test source file
 * @file testpools.h
 * @brief Memory Pools test header file
 */

#if CH_USE_MEMPOOLS

static MEMORYPOOL_DECL(mp1, THD_WA_SIZE(THREADS_STACK_SIZE));

/**
 * @page test_pools_001 Allocation and enqueuing test
 *
 * <h2>Description</h2>
 * Five memory blocks are added to a memory pool then removed.<br>
 * The test expects to find the pool queue in the proper status after each
 * operation.
 */

static char *pools1_gettest(void) {

  return "Memory Pools, queue/dequeue";
}

static void pools1_setup(void) {

  chPoolInit(&mp1, THD_WA_SIZE(THREADS_STACK_SIZE));
}

static void pools1_execute(void) {
  int i;

  /* Adding the WAs to the pool. */
  for (i = 0; i < MAX_THREADS; i++)
    chPoolFree(&mp1, wa[i]);

  /* Empting the pool again. */
  for (i = 0; i < MAX_THREADS; i++)
    test_assert(1, chPoolAlloc(&mp1) != NULL, "list empty");

  /* Now must be empty. */
  test_assert(2, chPoolAlloc(&mp1) == NULL, "list not empty");
}

const struct testcase testpools1 = {
  pools1_gettest,
  pools1_setup,
  NULL,
  pools1_execute
};

#endif /* CH_USE_MEMPOOLS */

/*
 * Test sequence for pools pattern.
 */
const struct testcase * const patternpools[] = {
#if CH_USE_MEMPOOLS
  &testpools1,
#endif
  NULL
};
} .highlight { background: #ffffff; } .highlight .c { color: #888888 } /* Comment */ .highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */ .highlight .k { color: #008800; font-weight: bold } /* Keyword */ .highlight .ch { color: #888888 } /* Comment.Hashbang */ .highlight .cm { color: #888888 } /* Comment.Multiline */ .highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */ .highlight .cpf { color: #888888 } /* Comment.PreprocFile */ .highlight .c1 { color: #888888 } /* Comment.Single */ .highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */ .highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */ .highlight .ge { font-style: italic } /* Generic.Emph */ .highlight .gr { color: #aa0000 } /* Generic.Error */ .highlight .gh { color: #333333 } /* Generic.Heading */ .highlight .gi { color: #000000; background-color: #ddffdd } /* Generic.Inserted */ .highlight .go { color: #888888 } /* Generic.Output */ .highlight .gp { color: #555555 } /* Generic.Prompt */ .highlight .gs { font-weight: bold } /* Generic.Strong */ .highlight .gu { color: #666666 } /* Generic.Subheading */ .highlight .gt { color: #aa0000 } /* Generic.Traceback */ .highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */ .highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */ .highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */ .highlight .kp { color: #008800 } /* Keyword.Pseudo */ .highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */ .highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */ .highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */ .highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */ .highlight .na { color: #336699 } /* Name.Attribute */ .highlight .nb { color: #003388 } /* Name.Builtin */ .highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */ .highlight .no { color: #003366; font-weight: bold } /* Name.Constant */ .highlight .nd { color: #555555 } /* Name.Decorator */ .highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */ .highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */ .highlight .nl { color: #336699; font-style: italic } /* Name.Label */ .highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */ .highlight .py { color: #336699; font-weight: bold } /* Name.Property */ .highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */ .highlight .nv { color: #336699 } /* Name.Variable */ .highlight .ow { color: #008800 } /* Operator.Word */ .highlight .w { color: #bbbbbb } /* Text.Whitespace */ .highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */ .highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */ .highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */ .highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */ .highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */ .highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */ .highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */ .highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */ .highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */ .highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */ .highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */ .highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */ .highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */ .highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */ .highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */ .highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */ .highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */ .highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */ .highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */ .highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */ .highlight .vc { color: #336699 } /* Name.Variable.Class */ .highlight .vg { color: #dd7700 } /* Name.Variable.Global */ .highlight .vi { color: #3333bb } /* Name.Variable.Instance */ .highlight .vm { color: #336699 } /* Name.Variable.Magic */ .highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */
module $__ANLOGIC_BRAM_TDP_ (...);

parameter INIT = 0;
parameter OPTION_RESETMODE = "SYNC";

parameter PORT_A_WIDTH = 9;
parameter PORT_A_CLK_POL = 1;
parameter PORT_A_OPTION_WRITEMODE = "NORMAL";

input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input PORT_A_RD_SRST;
input PORT_A_RD_ARST;
input [12:0] PORT_A_ADDR;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;

parameter PORT_B_WIDTH = 9;
parameter PORT_B_CLK_POL = 1;
parameter PORT_B_OPTION_WRITEMODE = "NORMAL";

input PORT_B_CLK;
input PORT_B_CLK_EN;
input PORT_B_WR_EN;
input PORT_B_RD_SRST;
input PORT_B_RD_ARST;
input [12:0] PORT_B_ADDR;
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;

function [255:0] init_slice;
	input integer idx;
	integer i;
	for (i = 0; i < 32; i = i + 1) begin
		init_slice[i*8+:8] = INIT[(idx * 32 + i) * 9 +: 8];
	end
endfunction

function [255:0] initp_slice;
	input integer idx;
	integer i;
	for (i = 0; i < 256; i = i + 1) begin
		initp_slice[i] = INIT[(idx * 256 + i) * 9 + 8];
	end
endfunction

wire [8:0] DOA;
wire [8:0] DOB;
// the replication is important — the BRAM behaves in... unexpected ways for
// width 1 and 2
wire [8:0] DIA = {9{PORT_A_WR_DATA}};
wire [8:0] DIB = {9{PORT_B_WR_DATA}};

assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;

EG_PHY_BRAM #(
	.INIT_00(init_slice('h00)),
	.INIT_01(init_slice('h01)),
	.INIT_02(init_slice('h02)),
	.INIT_03(init_slice('h03)),
	.INIT_04(init_slice('h04)),
	.INIT_05(init_slice('h05)),
	.INIT_06(init_slice('h06)),
	.INIT_07(init_slice('h07)),
	.INIT_08(init_slice('h08)),
	.INIT_09(init_slice('h09)),
	.INIT_0A(init_slice('h0a)),
	.INIT_0B(init_slice('h0b)),
	.INIT_0C(init_slice('h0c)),
	.INIT_0D(init_slice('h0d)),
	.INIT_0E(init_slice('h0e)),
	.INIT_0F(init_slice('h0f)),
	.INIT_10(init_slice('h10)),
	.INIT_11(init_slice('h11)),
	.INIT_12(init_slice('h12)),
	.INIT_13(init_slice('h13)),
	.INIT_14(init_slice('h14)),
	.INIT_15(init_slice('h15)),
	.INIT_16(init_slice('h16)),
	.INIT_17(init_slice('h17)),
	.INIT_18(init_slice('h18)),
	.INIT_19(init_slice('h19)),
	.INIT_1A(init_slice('h1a)),
	.INIT_1B(init_slice('h1b)),
	.INIT_1C(init_slice('h1c)),
	.INIT_1D(init_slice('h1d)),
	.INIT_1E(init_slice('h1e)),
	.INIT_1F(init_slice('h1f)),
	.INITP_00(initp_slice('h00)),
	.INITP_01(initp_slice('h01)),
	.INITP_02(initp_slice('h02)),
	.INITP_03(initp_slice('h03)),
	.MODE("DP8K"),
	.DATA_WIDTH_A($sformatf("%d", PORT_A_WIDTH)),
	.DATA_WIDTH_B($sformatf("%d", PORT_B_WIDTH)),
	.REGMODE_A("NOREG"),
	.REGMODE_B("NOREG"),
	.RESETMODE(OPTION_RESETMODE),
	.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
	.CLKAMUX(PORT_A_CLK_POL ? "SIG" : "INV"),
	.CLKBMUX(PORT_B_CLK_POL ? "SIG" : "INV"),
	.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
	.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
) _TECHMAP_REPLACE_ (
	.clka(PORT_A_CLK),
	.wea(PORT_A_WR_EN),
	.cea(PORT_A_CLK_EN),
	.ocea(1'b1),
	.rsta(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
	.csa(3'b111),
	.addra(PORT_A_WIDTH == 9 ? {PORT_A_ADDR[12:1], 1'b1} : PORT_A_ADDR),
	.dia(DIA),
	.doa(DOA),

	.clkb(PORT_B_CLK),
	.web(PORT_B_WR_EN),
	.ceb(PORT_B_CLK_EN),
	.oceb(1'b1),
	.rstb(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
	.csb(3'b111),
	.addrb(PORT_B_WIDTH == 9 ? {PORT_B_ADDR[12:1], 1'b1} : PORT_B_ADDR),
	.dib(DIB),
	.dob(DOB),
);

endmodule


module $__ANLOGIC_BRAM_SDP_ (...);

parameter INIT = 0;
parameter OPTION_RESETMODE = "SYNC";

parameter PORT_R_WIDTH = 18;
parameter PORT_R_CLK_POL = 1;

input PORT_R_CLK;
input PORT_R_CLK_EN;
input PORT_R_RD_SRST;
input PORT_R_RD_ARST;
input [12:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;

parameter PORT_W_WIDTH = 18;
parameter PORT_W_WR_EN_WIDTH = 2;
parameter PORT_W_CLK_POL = 1;

input PORT_W_CLK;
input PORT_W_CLK_EN;
input [12:0] PORT_W_ADDR;
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;

function [255:0] init_slice;
	input integer idx;
	integer i;
	for (i = 0; i < 32; i = i + 1) begin
		init_slice[i*8+:8] = INIT[(idx * 32 + i) * 9 +: 8];
	end
endfunction

function [255:0] initp_slice;
	input integer idx;
	integer i;
	for (i = 0; i < 256; i = i + 1) begin
		initp_slice[i] = INIT[(idx * 256 + i) * 9 + 8];
	end
endfunction

wire [17:0] DI = {18{PORT_W_WR_DATA}};
wire [17:0] DO;

assign PORT_R_RD_DATA = PORT_R_WIDTH == 18 ? DO : DO[17:9];

EG_PHY_BRAM #(
	.INIT_00(init_slice('h00)),
	.INIT_01(init_slice('h01)),
	.INIT_02(init_slice('h02)),
	.INIT_03(init_slice('h03)),
	.INIT_04(init_slice('h04)),
	.INIT_05(init_slice('h05)),
	.INIT_06(init_slice('h06)),
	.INIT_07(init_slice('h07)),
	.INIT_08(init_slice('h08)),
	.INIT_09(init_slice('h09)),
	.INIT_0A(init_slice('h0a)),
	.INIT_0B(init_slice('h0b)),
	.INIT_0C(init_slice('h0c)),
	.INIT_0D(init_slice('h0d)),
	.INIT_0E(init_slice('h0e)),
	.INIT_0F(init_slice('h0f)),
	.INIT_10(init_slice('h10)),
	.INIT_11(init_slice('h11)),
	.INIT_12(init_slice('h12)),
	.INIT_13(init_slice('h13)),
	.INIT_14(init_slice('h14)),
	.INIT_15(init_slice('h15)),
	.INIT_16(init_slice('h16)),
	.INIT_17(init_slice('h17)),
	.INIT_18(init_slice('h18)),
	.INIT_19(init_slice('h19)),
	.INIT_1A(init_slice('h1a)),
	.INIT_1B(init_slice('h1b)),
	.INIT_1C(init_slice('h1c)),
	.INIT_1D(init_slice('h1d)),
	.INIT_1E(init_slice('h1e)),
	.INIT_1F(init_slice('h1f)),
	.INITP_00(initp_slice('h00)),
	.INITP_01(initp_slice('h01)),
	.INITP_02(initp_slice('h02)),
	.INITP_03(initp_slice('h03)),
	.MODE("PDPW8K"),
	.DATA_WIDTH_A($sformatf("%d", PORT_W_WIDTH)),
	.DATA_WIDTH_B($sformatf("%d", PORT_R_WIDTH)),
	.REGMODE_A("NOREG"),
	.REGMODE_B("NOREG"),
	.RESETMODE(OPTION_RESETMODE),
	.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
	.CLKAMUX(PORT_W_CLK_POL ? "SIG" : "INV"),
	.CLKBMUX(PORT_R_CLK_POL ? "SIG" : "INV"),
) _TECHMAP_REPLACE_ (
	.clka(PORT_W_CLK),
	.wea(PORT_W_WIDTH >= 9 ? 1'b1 : PORT_W_WR_EN[0]),
	.cea(PORT_W_CLK_EN),
	.ocea(1'b1),
	.rsta(1'b0),
	.csa(3'b111),
	.addra(PORT_W_WIDTH == 18 ? {PORT_W_ADDR[12:2], PORT_W_WR_EN[1:0]} : (PORT_W_WIDTH == 9 ? {PORT_W_ADDR[12:1], PORT_W_WR_EN[0]} : PORT_W_ADDR)),
	.dia(DI[8:0]),
	.doa(DO[8:0]),

	.clkb(PORT_R_CLK),
	.web(1'b0),
	.ceb(PORT_R_CLK_EN),
	.oceb(1'b1),
	.rstb(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST),
	.csb(3'b111),
	.addrb(PORT_R_ADDR),
	.dib(DI[17:9]),
	.dob(DO[17:9]),
);

endmodule


module $__ANLOGIC_BRAM32K_ (...);

parameter INIT = 0;

parameter PORT_A_WIDTH = 16;
parameter PORT_A_WR_EN_WIDTH = 2;
parameter PORT_A_CLK_POL = 1;
parameter PORT_A_OPTION_WRITEMODE = "NORMAL";

input PORT_A_CLK;
input PORT_A_CLK_EN;
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
input [11:0] PORT_A_ADDR;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;

parameter PORT_B_WIDTH = 16;
parameter PORT_B_WR_EN_WIDTH = 2;
parameter PORT_B_CLK_POL = 1;
parameter PORT_B_OPTION_WRITEMODE = "NORMAL";

input PORT_B_CLK;
input PORT_B_CLK_EN;
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
input [11:0] PORT_B_ADDR;
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;

function [255:0] init_slice;
	input integer idx;
	init_slice = INIT[256 * idx +: 256];
endfunction

wire [15:0] DOA;
wire [15:0] DOB;
wire [15:0] DIA = PORT_A_WR_DATA;
wire [15:0] DIB = PORT_B_WR_DATA;

assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;

wire BYTE_A, BYTEWE_A;
wire BYTE_B, BYTEWE_B;

generate

if (PORT_A_WIDTH == 8) begin
	assign BYTE_A = PORT_A_ADDR[0];
	assign BYTEWE_A = 1;
end else begin
	assign BYTE_A = PORT_A_WR_EN == 2;
	assign BYTEWE_A = ^PORT_A_WR_EN;
end

if (PORT_B_WIDTH == 8) begin
	assign BYTE_B = PORT_B_ADDR[0];
	assign BYTEWE_B = 1;
end else begin
	assign BYTE_B = PORT_B_WR_EN == 2;
	assign BYTEWE_B = ^PORT_B_WR_EN;
end

endgenerate

EG_PHY_BRAM32K #(
	.INIT_00(init_slice('h00)),
	.INIT_01(init_slice('h01)),
	.INIT_02(init_slice('h02)),
	.INIT_03(init_slice('h03)),
	.INIT_04(init_slice('h04)),
	.INIT_05(init_slice('h05)),
	.INIT_06(init_slice('h06)),
	.INIT_07(init_slice('h07)),
	.INIT_08(init_slice('h08)),
	.INIT_09(init_slice('h09)),
	.INIT_0A(init_slice('h0a)),
	.INIT_0B(init_slice('h0b)),
	.INIT_0C(init_slice('h0c)),
	.INIT_0D(init_slice('h0d)),
	.INIT_0E(init_slice('h0e)),
	.INIT_0F(init_slice('h0f)),
	.INIT_10(init_slice('h10)),
	.INIT_11(init_slice('h11)),
	.INIT_12(init_slice('h12)),
	.INIT_13(init_slice('h13)),
	.INIT_14(init_slice('h14)),
	.INIT_15(init_slice('h15)),
	.INIT_16(init_slice('h16)),
	.INIT_17(init_slice('h17)),
	.INIT_18(init_slice('h18)),
	.INIT_19(init_slice('h19)),
	.INIT_1A(init_slice('h1a)),
	.INIT_1B(init_slice('h1b)),
	.INIT_1C(init_slice('h1c)),
	.INIT_1D(init_slice('h1d)),
	.INIT_1E(init_slice('h1e)),
	.INIT_1F(init_slice('h1f)),
	.INIT_20(init_slice('h20)),
	.INIT_21(init_slice('h21)),
	.INIT_22(init_slice('h22)),
	.INIT_23(init_slice('h23)),
	.INIT_24(init_slice('h24)),
	.INIT_25(init_slice('h25)),
	.INIT_26(init_slice('h26)),
	.INIT_27(init_slice('h27)),
	.INIT_28(init_slice('h28)),
	.INIT_29(init_slice('h29)),
	.INIT_2A(init_slice('h2a)),
	.INIT_2B(init_slice('h2b)),
	.INIT_2C(init_slice('h2c)),
	.INIT_2D(init_slice('h2d)),
	.INIT_2E(init_slice('h2e)),
	.INIT_2F(init_slice('h2f)),
	.INIT_30(init_slice('h30)),
	.INIT_31(init_slice('h31)),
	.INIT_32(init_slice('h32)),
	.INIT_33(init_slice('h33)),
	.INIT_34(init_slice('h34)),
	.INIT_35(init_slice('h35)),
	.INIT_36(init_slice('h36)),
	.INIT_37(init_slice('h37)),
	.INIT_38(init_slice('h38)),
	.INIT_39(init_slice('h39)),
	.INIT_3A(init_slice('h3a)),
	.INIT_3B(init_slice('h3b)),
	.INIT_3C(init_slice('h3c)),
	.INIT_3D(init_slice('h3d)),
	.INIT_3E(init_slice('h3e)),
	.INIT_3F(init_slice('h3f)),
	.INIT_40(init_slice('h40)),
	.INIT_41(init_slice('h41)),
	.INIT_42(init_slice('h42)),
	.INIT_43(init_slice('h43)),
	.INIT_44(init_slice('h44)),
	.INIT_45(init_slice('h45)),
	.INIT_46(init_slice('h46)),
	.INIT_47(init_slice('h47)),
	.INIT_48(init_slice('h48)),
	.INIT_49(init_slice('h49)),
	.INIT_4A(init_slice('h4a)),
	.INIT_4B(init_slice('h4b)),
	.INIT_4C(init_slice('h4c)),
	.INIT_4D(init_slice('h4d)),
	.INIT_4E(init_slice('h4e)),
	.INIT_4F(init_slice('h4f)),
	.INIT_50(init_slice('h50)),
	.INIT_51(init_slice('h51)),
	.INIT_52(init_slice('h52)),
	.INIT_53(init_slice('h53)),
	.INIT_54(init_slice('h54)),
	.INIT_55(init_slice('h55)),
	.INIT_56(init_slice('h56)),
	.INIT_57(init_slice('h57)),
	.INIT_58(init_slice('h58)),
	.INIT_59(init_slice('h59)),
	.INIT_5A(init_slice('h5a)),
	.INIT_5B(init_slice('h5b)),
	.INIT_5C(init_slice('h5c)),
	.INIT_5D(init_slice('h5d)),
	.INIT_5E(init_slice('h5e)),
	.INIT_5F(init_slice('h5f)),
	.INIT_60(init_slice('h60)),
	.INIT_61(init_slice('h61)),
	.INIT_62(init_slice('h62)),
	.INIT_63(init_slice('h63)),
	.INIT_64(init_slice('h64)),
	.INIT_65(init_slice('h65)),
	.INIT_66(init_slice('h66)),
	.INIT_67(init_slice('h67)),
	.INIT_68(init_slice('h68)),
	.INIT_69(init_slice('h69)),
	.INIT_6A(init_slice('h6a)),
	.INIT_6B(init_slice('h6b)),
	.INIT_6C(init_slice('h6c)),
	.INIT_6D(init_slice('h6d)),
	.INIT_6E(init_slice('h6e)),
	.INIT_6F(init_slice('h6f)),
	.INIT_70(init_slice('h70)),
	.INIT_71(init_slice('h71)),
	.INIT_72(init_slice('h72)),
	.INIT_73(init_slice('h73)),
	.INIT_74(init_slice('h74)),
	.INIT_75(init_slice('h75)),
	.INIT_76(init_slice('h76)),
	.INIT_77(init_slice('h77)),
	.INIT_78(init_slice('h78)),
	.INIT_79(init_slice('h79)),
	.INIT_7A(init_slice('h7a)),
	.INIT_7B(init_slice('h7b)),
	.INIT_7C(init_slice('h7c)),
	.INIT_7D(init_slice('h7d)),
	.INIT_7E(init_slice('h7e)),
	.INIT_7F(init_slice('h7f)),
	.MODE("DP16K"),
	.DATA_WIDTH_A($sformatf("%d", PORT_A_WIDTH)),
	.DATA_WIDTH_B($sformatf("%d", PORT_B_WIDTH)),
	.REGMODE_A("NOREG"),
	.REGMODE_B("NOREG"),
	.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
	.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
	.CLKAMUX(PORT_A_CLK_POL ? "SIG" : "INV"),
	.CLKBMUX(PORT_B_CLK_POL ? "SIG" : "INV"),
) _TECHMAP_REPLACE_ (
	.clka(PORT_A_CLK),
	.csa(PORT_A_CLK_EN),
	.wea(|PORT_A_WR_EN),
	.ocea(1'b1),
	.rsta(1'b0),
	.addra(PORT_A_ADDR[11:1]),
	.bytea(BYTE_A),
	.bytewea(BYTEWE_A),
	.dia(DIA),
	.doa(DOA),

	.clkb(PORT_B_CLK),
	.csb(PORT_B_CLK_EN),
	.web(|PORT_B_WR_EN),
	.ocea(1'b1),
	.rsta(1'b0),
	.addrb(PORT_B_ADDR[11:1]),
	.byteb(BYTE_B),
	.byteweb(BYTEWE_B),
	.dib(DIB),
	.dob(DOB),
);

endmodule