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/*
    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

#include "ch.h"
#include "test.h"

/**
 * @page test_msg Messages test
 *
 * File: @ref testmsg.c
 *
 * <h2>Description</h2>
 * This module implements the test sequence for the @ref messages subsystem.
 *
 * <h2>Objective</h2>
 * Objective of the test module is to cover 100% of the @ref messages
 * subsystem code.
 *
 * <h2>Preconditions</h2>
 * The module requires the following kernel options:
 * - @p CH_CFG_USE_MESSAGES
 * .
 * In case some of the required options are not enabled then some or all tests
 * may be skipped.
 *
 * <h2>Test Cases</h2>
 * - @subpage test_msg_001
 * .
 * @file testmsg.c
 * @brief Messages test source file
 * @file testmsg.h
 * @brief Messages header file
 */

#if CH_CFG_USE_MESSAGES || defined(__DOXYGEN__)

/**
 * @page test_msg_001 Messages Server loop
 *
 * <h2>Description</h2>
 * A thread is spawned that sends four messages back to the tester thread.<br>
 * The test expect to receive the messages in the correct sequence and to
 * not find a fifth message waiting.
 */

static msg_t thread(void *p) {

  chMsgSend(p, 'A');
  chMsgSend(p, 'B');
  chMsgSend(p, 'C');
  return 0;
}

static void msg1_execute(void) {
  thread_t *tp;
  msg_t msg;

  /*
   * Testing the whole messages loop.
   */
  threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriorityX() + 1,
                                 thread, chThdGetSelfX());
  tp = chMsgWait();
  msg = chMsgGet(tp);
  chMsgRelease(tp, msg);
  test_emit_token(msg);
  tp = chMsgWait();
  msg = chMsgGet(tp);
  chMsgRelease(tp, msg);
  test_emit_token(msg);
  tp = chMsgWait();
  msg = chMsgGet(tp);
  chMsgRelease(tp, msg);
  test_emit_token(msg);
  test_assert_sequence(1, "ABC");
}

ROMCONST struct testcase testmsg1 = {
  "Messages, loop",
  NULL,
  NULL,
  msg1_execute
};

#endif /* CH_CFG_USE_MESSAGES */

/**
 * @brief   Test sequence for messages.
 */
ROMCONST struct testcase * ROMCONST patternmsg[] = {
#if CH_CFG_USE_MESSAGES || defined(__DOXYGEN__)
  &testmsg1,
#endif
  NULL
};
p">#define STM32_ADC_USE_SDADC3 FALSE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_SDADC1_DMA_PRIORITY 2 #define STM32_ADC_SDADC2_DMA_PRIORITY 2 #define STM32_ADC_SDADC3_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #define STM32_ADC_SDADC1_IRQ_PRIORITY 5 #define STM32_ADC_SDADC2_IRQ_PRIORITY 5 #define STM32_ADC_SDADC3_IRQ_PRIORITY 5 #define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 #define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. */ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 /* * EXT driver system settings. */ #define STM32_EXT_EXTI0_IRQ_PRIORITY 6 #define STM32_EXT_EXTI1_IRQ_PRIORITY 6 #define STM32_EXT_EXTI2_IRQ_PRIORITY 6 #define STM32_EXT_EXTI3_IRQ_PRIORITY 6 #define STM32_EXT_EXTI4_IRQ_PRIORITY 6 #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 #define STM32_EXT_EXTI16_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI20_23_IRQ_PRIORITY 6 #define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 #define STM32_EXT_EXTI33_IRQ_PRIORITY 6 /* * GPT driver system settings. */ #define STM32_GPT_USE_TIM2 FALSE #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM7 FALSE #define STM32_GPT_USE_TIM12 FALSE #define STM32_GPT_USE_TIM14 FALSE #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 #define STM32_GPT_TIM5_IRQ_PRIORITY 7 #define STM32_GPT_TIM6_IRQ_PRIORITY 7 #define STM32_GPT_TIM7_IRQ_PRIORITY 7 #define STM32_GPT_TIM12_IRQ_PRIORITY 7 #define STM32_GPT_TIM14_IRQ_PRIORITY 7 /* * I2C driver system settings. */ #define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C2 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_IRQ_PRIORITY 10 #define STM32_I2C_I2C2_IRQ_PRIORITY 10 #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* * ICU driver system settings. */ #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM3 FALSE #define STM32_ICU_USE_TIM4 FALSE #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_TIM2_IRQ_PRIORITY 7 #define STM32_ICU_TIM3_IRQ_PRIORITY 7 #define STM32_ICU_TIM4_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7 /* * PWM driver system settings. */ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 #define STM32_PWM_TIM4_IRQ_PRIORITY 7 #define STM32_PWM_TIM5_IRQ_PRIORITY 7 /* * SERIAL driver system settings. */ #define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 FALSE #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 /* * SPI driver system settings. */ #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* * ST driver system settings. */ #define STM32_ST_IRQ_PRIORITY 8 #define STM32_ST_USE_TIMER 2 /* * UART driver system settings. */ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART3 FALSE #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* * USB driver system settings. */ #define STM32_USB_USE_USB1 FALSE #define STM32_USB_LOW_POWER_ON_SUSPEND FALSE #define STM32_USB_USB1_HP_IRQ_PRIORITY 13 #define STM32_USB_USB1_LP_IRQ_PRIORITY 14