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/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
                 2011,2012 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

/**
 * @file    chregistry.c
 * @brief   Threads registry code.
 *
 * @addtogroup registry
 * @details Threads Registry related APIs and services.
 *
 *          <h2>Operation mode</h2>
 *          The Threads Registry is a double linked list that holds all the
 *          active threads in the system.<br>
 *          Operations defined for the registry:
 *          - <b>First</b>, returns the first, in creation order, active thread
 *            in the system.
 *          - <b>Next</b>, returns the next, in creation order, active thread
 *            in the system.
 *          .
 *          The registry is meant to be mainly a debug feature, for example,
 *          using the registry a debugger can enumerate the active threads
 *          in any given moment or the shell can print the active threads
 *          and their state.<br>
 *          Another possible use is for centralized threads memory management,
 *          terminating threads can pulse an event source and an event handler
 *          can perform a scansion of the registry in order to recover the
 *          memory.
 * @pre     In order to use the threads registry the @p CH_USE_REGISTRY option
 *          must be enabled in @p chconf.h.
 * @{
 */
#include "ch.h"

#if CH_USE_REGISTRY || defined(__DOXYGEN__)

/**
 * @brief   Returns the first thread in the system.
 * @details Returns the most ancient thread in the system, usually this is
 *          the main thread unless it terminated. A reference is added to the
 *          returned thread in order to make sure its status is not lost.
 * @note    This function cannot return @p NULL because there is always at
 *          least one thread in the system.
 *
 * @return              A reference to the most ancient thread.
 *
 * @api
 */
Thread *chRegFirstThread(void) {
  Thread *tp;

  chSysLock();
  tp = rlist.r_newer;
#if CH_USE_DYNAMIC
  tp->p_refs++;
#endif
  chSysUnlock();
  return tp;
}

/**
 * @brief   Returns the thread next to the specified one.
 * @details The reference counter of the specified thread is decremented and
 *          the reference counter of the returned thread is incremented.
 *
 * @param[in] tp        pointer to the thread
 * @return              A reference to the next thread.
 * @retval NULL         if there is no next thread.
 *
 * @api
 */
Thread *chRegNextThread(Thread *tp) {
  Thread *ntp;

  chSysLock();
  ntp = tp->p_newer;
  if (ntp == (Thread *)&rlist)
    ntp = NULL;
#if CH_USE_DYNAMIC
  else {
    chDbgAssert(ntp->p_refs < 255, "chRegNextThread(), #1",
                "too many references");
    ntp->p_refs++;
  }
#endif
  chSysUnlock();
#if CH_USE_DYNAMIC
  chThdRelease(tp);
#endif
  return ntp;
}

#endif /* CH_USE_REGISTRY */

/** @} */
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/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/consteval.h"
#include "kernel/log.h"
#include <sstream>
#include <stdlib.h>
#include <stdio.h>

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
{
	RTLIL::SigSpec lvalue;

	for (auto sync : proc->syncs)
	for (auto &action : sync->actions)
		if (action.first.size() > 0) {
			lvalue = action.first;
			lvalue.sort_and_unify();
			break;
		}

	for (auto sync : proc->syncs) {
		RTLIL::SigSpec this_lvalue;
		for (auto &action : sync->actions)
			this_lvalue.append(action.first);
		this_lvalue.sort_and_unify();
		RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue);
		if (common_sig.size() > 0)
			lvalue = common_sig;
	}

	return lvalue;
}

void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
		std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
{
	RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size());
	RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size());

	for (auto &it : async_rules)
	{
		RTLIL::SigSpec sync_value = it.first;
		RTLIL::SigSpec sync_value_inv;
		RTLIL::SigSpec sync_high_signals;
		RTLIL::SigSpec sync_low_signals;

		for (auto &it2 : it.second)
			if (it2->type == RTLIL::SyncType::ST0)
				sync_low_signals.append(it2->signal);
			else if (it2->type == RTLIL::SyncType::ST1)
				sync_high_signals.append(it2->signal);
			else
				log_abort();

		if (sync_low_signals.size() > 1) {
			RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
			cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
			cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
			cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
			cell->setPort(ID::A, sync_low_signals);
			cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID));
		}

		if (sync_low_signals.size() > 0) {
			RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($not));
			cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
			cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
			cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
			cell->setPort(ID::A, sync_low_signals);
			cell->setPort(ID::Y, mod->addWire(NEW_ID));
			sync_high_signals.append(cell->getPort(ID::Y));
		}

		if (sync_high_signals.size() > 1) {
			RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
			cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
			cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_high_signals.size());
			cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
			cell->setPort(ID::A, sync_high_signals);
			cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID));
		}

		RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, ID($not));
		inv_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
		inv_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_d.size());
		inv_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_d.size());
		inv_cell->setPort(ID::A, sync_value);
		inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));

		RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, ID($mux));
		mux_set_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
		mux_set_cell->setPort(ID::A, sig_sr_set);
		mux_set_cell->setPort(ID::B, sync_value);
		mux_set_cell->setPort(ID::S, sync_high_signals);
		mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));

		RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, ID($mux));
		mux_clr_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
		mux_clr_cell->setPort(ID::A, sig_sr_clr);
		mux_clr_cell->setPort(ID::B, sync_value_inv);
		mux_clr_cell->setPort(ID::S, sync_high_signals);
		mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
	}

	std::stringstream sstr;
	sstr << "$procdff$" << (autoidx++);

	RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
	cell->attributes = proc->attributes;
	cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
	cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
	cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
	cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
	cell->setPort(ID::D, sig_d);
	cell->setPort(ID::Q, sig_q);
	cell->setPort(ID::CLK, clk);
	cell->setPort(ID::SET, sig_sr_set);
	cell->setPort(ID::CLR, sig_sr_clr);

	log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
}

void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_out,
		bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)
{
	std::stringstream sstr;
	sstr << "$procdff$" << (autoidx++);

	RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size());
	RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
	RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size());

	RTLIL::Cell *inv_set = mod->addCell(NEW_ID, ID($not));
	inv_set->parameters[ID::A_SIGNED] = RTLIL::Const(0);
	inv_set->parameters[ID::A_WIDTH] = RTLIL::Const(sig_in.size());
	inv_set->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_in.size());
	inv_set->setPort(ID::A, sig_set);
	inv_set->setPort(ID::Y, sig_set_inv);

	RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, ID($mux));
	mux_sr_set->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
	mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
	mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set);
	mux_sr_set->setPort(ID::Y, sig_sr_set);
	mux_sr_set->setPort(ID::S, set);

	RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, ID($mux));
	mux_sr_clr->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
	mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
	mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv);
	mux_sr_clr->setPort(ID::Y, sig_sr_clr);
	mux_sr_clr->setPort(ID::S, set);

	RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
	cell->attributes = proc->attributes;
	cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
	cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
	cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
	cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
	cell->setPort(ID::D, sig_in);
	cell->setPort(ID::Q, sig_out);
	cell->setPort(ID::CLK, clk);
	cell->setPort(ID::SET, sig_sr_set);
	cell->setPort(ID::CLR, sig_sr_clr);

	log("  created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
			clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
}

void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RTLIL::SigSpec sig_out,
		bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc)
{
	std::stringstream sstr;
	sstr << "$procdff$" << (autoidx++);

	RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff));
	cell->attributes = proc->attributes;

	cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
	if (arst) {
		cell->parameters[ID::ARST_POLARITY] = RTLIL::Const(arst_polarity, 1);
		cell->parameters[ID::ARST_VALUE] = val_rst;
	}
	if (!clk.empty()) {
		cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
	}

	cell->setPort(ID::D, sig_in);
	cell->setPort(ID::Q, sig_out);
	if (arst)
		cell->setPort(ID::ARST, *arst);
	if (!clk.empty())
		cell->setPort(ID::CLK, clk);

	if (!clk.empty())
		log("  created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
	else
		log("  created %s cell `%s' with global clock", cell->type.c_str(), cell->name.c_str());
	if (arst)
		log(" and %s level reset", arst_polarity ? "positive" : "negative");
	log(".\n");
}

void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
{
	while (1)
	{
		RTLIL::SigSpec sig = find_any_lvalue(proc);
		bool free_sync_level = false;

		if (sig.size() == 0)
			break;

		log("Creating register for signal `%s.%s' using process `%s.%s'.\n",
				mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str());

		RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
		RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
		RTLIL::SyncRule *sync_level = NULL;
		RTLIL::SyncRule *sync_edge = NULL;
		RTLIL::SyncRule *sync_always = NULL;
		bool global_clock = false;

		std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> many_async_rules;

		for (auto sync : proc->syncs)
		for (auto &action : sync->actions)
		{
			if (action.first.extract(sig).size() == 0)
				continue;

			if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {
				if (sync_level != NULL && sync_level != sync) {
					// log_error("Multiple level sensitive events found for this signal!\n");
					many_async_rules[rstval].insert(sync_level);
					rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
				}
				rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());