demos/STM32/RT-STM32L152RE-NUCLEO/Makefile


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generated by cgit v1.2.3 (git 2.25.1) at 2026-01-07 12:21:02 +0000
 

class="o">-1)) begin
			\$__mem_4x1_generator #(
				.ABITS(ABITS-1),
				.SIZE(SIZE - 2**(ABITS-1))
			) part_high (
				.CLK(CLK),
				.RD_ADDR(RD_ADDR[ABITS-2:0]),
				.RD_DATA(high_rd_data),
				.WR_ADDR(WR_ADDR[ABITS-2:0]),
				.WR_DATA(WR_DATA),
				.WR_EN(WR_EN && WR_ADDR[ABITS-1])
			);
		end else begin
			assign high_rd_data = 1'bx;
		end
		\$__mem_4x1_generator #(
			.ABITS(ABITS-1),
			.SIZE(SIZE > 2**(ABITS-1) ? 2**(ABITS-1) : SIZE)
		) part_low (
			.CLK(CLK),
			.RD_ADDR(RD_ADDR[ABITS-2:0]),
			.RD_DATA(low_rd_data),
			.WR_ADDR(WR_ADDR[ABITS-2:0]),
			.WR_DATA(WR_DATA),
			.WR_EN(WR_EN && !WR_ADDR[ABITS-1])
		);
		reg delayed_abit;
		always @(posedge CLK)
			delayed_abit <= RD_ADDR[ABITS-1];
		assign RD_DATA = delayed_abit ? high_rd_data : low_rd_data;
	  end else begin
	  	MEM4X1 _TECHMAP_REPLACE_ (
			.CLK(CLK),
			.RD_ADDR(RD_ADDR),
			.RD_DATA(RD_DATA),
			.WR_ADDR(WR_ADDR),
			.WR_DATA(WR_DATA),
			.WR_EN(WR_EN)
		);
	  end
	endgenerate
endmodule