aboutsummaryrefslogtreecommitdiffstats
path: root/demos/ARM7-LPC214x-G++/main.cpp
blob: b6b7c83ba4e3abb5aa405b1d37fc36e35ce69142 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

#include "ch.hpp"
#include "hal.h"
#include "test.h"
#include "evtimer.h"

#define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2))

using namespace chibios_rt;

/*
 * LED blink sequences.
 * NOTE: Sequences must always be terminated by a GOTO instruction.
 * NOTE: The sequencer language could be easily improved but this is outside
 *       the scope of this demo.
 */
#define SLEEP           0
#define GOTO            1
#define STOP            2
#define BITCLEAR        3
#define BITSET          4

typedef struct {
  uint8_t       action;
  uint32_t      value;
} seqop_t;

// Flashing sequence for LED1.
static const seqop_t LED1_sequence[] =
{
  {BITCLEAR, PAL_PORT_BIT(PA_LED1)},
  {SLEEP,    200},
  {BITSET,   PAL_PORT_BIT(PA_LED1)},
  {SLEEP,    1800},
  {GOTO,     0}
};

// Flashing sequence for LED2.
static const seqop_t LED2_sequence[] =
{
  {SLEEP,    1000},
  {BITCLEAR, PAL_PORT_BIT(PA_LED2)},
  {SLEEP,    200},
  {BITSET,   PAL_PORT_BIT(PA_LED2)},
  {SLEEP,    1800},
  {GOTO,     1}
};

// Flashing sequence for LED3.
static const seqop_t LED3_sequence[] =
{
  {BITCLEAR, PAL_PORT_BIT(PA_LEDUSB)},
  {SLEEP,    200},
  {BITSET,   PAL_PORT_BIT(PA_LEDUSB)},
  {SLEEP,    300},
  {GOTO,     0}
};

/*
 * Sequencer thread class. It can drive LEDs or other output pins.
 * Any sequencer is just an instance of this class, all the details are
 * totally encapsulated and hidden to the application level.
 */
class SequencerThread : public EnhancedThread<128> {
private:
  const seqop_t *base, *curr;                   // Thread local variables.

protected:
  virtual msg_t Main(void) {
    while (true) {
      switch(curr->action) {
      case SLEEP:
        Sleep(curr->value);
        break;
      case GOTO:
        curr = &base[curr->value];
        continue;
      case STOP:
        return 0;
      case BITCLEAR:
        palClearPort(IOPORT1, curr->value);
        break;
      case BITSET:
        palSetPort(IOPORT1, curr->value);
        break;
      }
      curr++;
    }
  }

public:
  SequencerThread(const seqop_t *sequence) : EnhancedThread<128>("sequencer") {

    base = curr = sequence;
  }
};

/*
 * Tester thread class. This thread executes the test suite.
 */
class TesterThread : public EnhancedThread<128> {

protected:
  virtual msg_t Main(void) {

    return TestThread(&SD1);
  }

public:
  TesterThread(void) : EnhancedThread<128>("tester") {
  }
};

/*
 * Executed as an event handler at 500mS intervals.
 */
static void TimerHandler(eventid_t id) {

  (void)id;
  if (!(palReadPort(IOPORT1) & BOTH_BUTTONS)) { // Both buttons
    TesterThread tester;
    tester.Wait();
  };
}

/*
 * Entry point, note, the main() function is already a thread in the system
 * on entry.
 */
int main(int argc, char **argv) {
  static const evhandler_t evhndl[] = {
    TimerHandler
  };
  static EvTimer evt;
  struct EventListener el0;

  (void)argc;
  (void)argv;

  /*
   * Activates the serial driver 2 using the driver default configuration.
   */
  sdStart(&SD1, NULL);

  evtInit(&evt, 500);                   // Initializes an event timer.
  evtStart(&evt);                       // Starts the event timer.
  chEvtRegister(&evt.et_es, &el0, 0);   // Registers a listener on the source.

  /*
   * Starts several instances of the SequencerThread class, each one operating
   * on a different LED.
   */
  SequencerThread blinker1(LED1_sequence);
  SequencerThread blinker2(LED2_sequence);
  SequencerThread blinker3(LED3_sequence);

  /*
   * Serves timer events.
   */
  while (true)
    Event::Dispatch(evhndl, Event::WaitOne(ALL_EVENTS));

  return 0;
}
class="kt">void *opaque, target_phys_addr_t offset) { integratorcm_state *s = (integratorcm_state *)opaque; offset -= 0x10000000; if (offset >= 0x100 && offset < 0x200) { /* CM_SPD */ if (offset >= 0x180) return 0; return integrator_spd[offset >> 2]; } switch (offset >> 2) { case 0: /* CM_ID */ return 0x411a3001; case 1: /* CM_PROC */ return 0; case 2: /* CM_OSC */ return s->cm_osc; case 3: /* CM_CTRL */ return s->cm_ctrl; case 4: /* CM_STAT */ return 0x00100000; case 5: /* CM_LOCK */ if (s->cm_lock == 0xa05f) { return 0x1a05f; } else { return s->cm_lock; } case 6: /* CM_LMBUSCNT */ /* ??? High frequency timer. */ cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT"); case 7: /* CM_AUXOSC */ return s->cm_auxosc; case 8: /* CM_SDRAM */ return s->cm_sdram; case 9: /* CM_INIT */ return s->cm_init; case 10: /* CM_REFCT */ /* ??? High frequency timer. */ cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT"); case 12: /* CM_FLAGS */ return s->cm_flags; case 14: /* CM_NVFLAGS */ return s->cm_nvflags; case 16: /* CM_IRQ_STAT */ return s->int_level & s->irq_enabled; case 17: /* CM_IRQ_RSTAT */ return s->int_level; case 18: /* CM_IRQ_ENSET */ return s->irq_enabled; case 20: /* CM_SOFT_INTSET */ return s->int_level & 1; case 24: /* CM_FIQ_STAT */ return s->int_level & s->fiq_enabled; case 25: /* CM_FIQ_RSTAT */ return s->int_level; case 26: /* CM_FIQ_ENSET */ return s->fiq_enabled; case 32: /* CM_VOLTAGE_CTL0 */ case 33: /* CM_VOLTAGE_CTL1 */ case 34: /* CM_VOLTAGE_CTL2 */ case 35: /* CM_VOLTAGE_CTL3 */ /* ??? Voltage control unimplemented. */ return 0; default: cpu_abort (cpu_single_env, "integratorcm_read: Unimplemented offset 0x%x\n", offset); return 0; } } static void integratorcm_do_remap(integratorcm_state *s, int flash) { if (flash) { cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM); } else { cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM); } //??? tlb_flush (cpu_single_env, 1); } static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value) { if (value & 8) { cpu_abort(cpu_single_env, "Board reset\n"); } if ((s->cm_init ^ value) & 4) { integratorcm_do_remap(s, (value & 4) == 0); } if ((s->cm_init ^ value) & 1) { printf("Green LED %s\n", (value & 1) ? "on" : "off"); } s->cm_init = (s->cm_init & ~ 5) | (value ^ 5); } static void integratorcm_update(integratorcm_state *s) { /* ??? The CPU irq/fiq is raised when either the core module or base PIC are active. */ if (s->int_level & (s->irq_enabled | s->fiq_enabled)) cpu_abort(cpu_single_env, "Core module interrupt\n"); } static void integratorcm_write(void *opaque, target_phys_addr_t offset, uint32_t value) { integratorcm_state *s = (integratorcm_state *)opaque; offset -= 0x10000000; switch (offset >> 2) { case 2: /* CM_OSC */ if (s->cm_lock == 0xa05f) s->cm_osc = value; break; case 3: /* CM_CTRL */ integratorcm_set_ctrl(s, value); break; case 5: /* CM_LOCK */ s->cm_lock = value & 0xffff; break; case 7: /* CM_AUXOSC */ if (s->cm_lock == 0xa05f) s->cm_auxosc = value; break; case 8: /* CM_SDRAM */ s->cm_sdram = value; break; case 9: /* CM_INIT */ /* ??? This can change the memory bus frequency. */ s->cm_init = value; break; case 12: /* CM_FLAGSS */ s->cm_flags |= value; break; case 13: /* CM_FLAGSC */ s->cm_flags &= ~value; break; case 14: /* CM_NVFLAGSS */ s->cm_nvflags |= value; break; case 15: /* CM_NVFLAGSS */ s->cm_nvflags &= ~value; break; case 18: /* CM_IRQ_ENSET */ s->irq_enabled |= value; integratorcm_update(s); break; case 19: /* CM_IRQ_ENCLR */ s->irq_enabled &= ~value; integratorcm_update(s); break; case 20: /* CM_SOFT_INTSET */ s->int_level |= (value & 1); integratorcm_update(s); break; case 21: /* CM_SOFT_INTCLR */ s->int_level &= ~(value & 1); integratorcm_update(s); break; case 26: /* CM_FIQ_ENSET */ s->fiq_enabled |= value; integratorcm_update(s); break; case 27: /* CM_FIQ_ENCLR */ s->fiq_enabled &= ~value; integratorcm_update(s); break; case 32: /* CM_VOLTAGE_CTL0 */ case 33: /* CM_VOLTAGE_CTL1 */ case 34: /* CM_VOLTAGE_CTL2 */ case 35: /* CM_VOLTAGE_CTL3 */ /* ??? Voltage control unimplemented. */ break; default: cpu_abort (cpu_single_env, "integratorcm_write: Unimplemented offset 0x%x\n", offset); break; } } /* Integrator/CM control registers. */ static CPUReadMemoryFunc *integratorcm_readfn[] = { integratorcm_read, integratorcm_read, integratorcm_read }; static CPUWriteMemoryFunc *integratorcm_writefn[] = { integratorcm_write, integratorcm_write, integratorcm_write }; static void integratorcm_init(int memsz, uint32_t flash_offset) { int iomemtype; integratorcm_state *s; s = (integratorcm_state *)qemu_mallocz(sizeof(integratorcm_state)); s->cm_osc = 0x01000048; /* ??? What should the high bits of this value be? */ s->cm_auxosc = 0x0007feff; s->cm_sdram = 0x00011122; if (memsz >= 256) { integrator_spd[31] = 64; s->cm_sdram |= 0x10; } else if (memsz >= 128) { integrator_spd[31] = 32; s->cm_sdram |= 0x0c; } else if (memsz >= 64) { integrator_spd[31] = 16; s->cm_sdram |= 0x08; } else if (memsz >= 32) { integrator_spd[31] = 4; s->cm_sdram |= 0x04; } else { integrator_spd[31] = 2; } memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); s->cm_init = 0x00000112; s->flash_offset = flash_offset; iomemtype = cpu_register_io_memory(0, integratorcm_readfn, integratorcm_writefn, s); cpu_register_physical_memory(0x10000000, 0x007fffff, iomemtype); integratorcm_do_remap(s, 1); /* ??? Save/restore. */ } /* Integrator/CP hardware emulation. */ /* Primary interrupt controller. */ typedef struct icp_pic_state { arm_pic_handler handler; uint32_t base; uint32_t level; uint32_t irq_enabled; uint32_t fiq_enabled; void *parent; int parent_irq; int parent_fiq; } icp_pic_state; static void icp_pic_update(icp_pic_state *s) { uint32_t flags; if (s->parent_irq != -1) { flags = (s->level & s->irq_enabled); pic_set_irq_new(s->parent, s->parent_irq, flags != 0); } if (s->parent_fiq != -1) { flags = (s->level & s->fiq_enabled); pic_set_irq_new(s->parent, s->parent_fiq, flags != 0); } } static void icp_pic_set_irq(void *opaque, int irq, int level) { icp_pic_state *s = (icp_pic_state *)opaque; if (level) s->level |= 1 << irq; else s->level &= ~(1 << irq); icp_pic_update(s); } static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset) { icp_pic_state *s = (icp_pic_state *)opaque; offset -= s->base; switch (offset >> 2) { case 0: /* IRQ_STATUS */ return s->level & s->irq_enabled; case 1: /* IRQ_RAWSTAT */ return s->level; case 2: /* IRQ_ENABLESET */ return s->irq_enabled; case 4: /* INT_SOFTSET */ return s->level & 1; case 8: /* FRQ_STATUS */ return s->level & s->fiq_enabled; case 9: /* FRQ_RAWSTAT */ return s->level; case 10: /* FRQ_ENABLESET */ return s->fiq_enabled; case 3: /* IRQ_ENABLECLR */ case 5: /* INT_SOFTCLR */ case 11: /* FRQ_ENABLECLR */ default: printf ("icp_pic_read: Bad register offset 0x%x\n", offset); return 0; } } static void icp_pic_write(void *opaque, target_phys_addr_t offset, uint32_t value) { icp_pic_state *s = (icp_pic_state *)opaque; offset -= s->base; switch (offset >> 2) { case 2: /* IRQ_ENABLESET */ s->irq_enabled |= value; break; case 3: /* IRQ_ENABLECLR */ s->irq_enabled &= ~value; break; case 4: /* INT_SOFTSET */ if (value & 1) pic_set_irq_new(s, 0, 1); break; case 5: /* INT_SOFTCLR */ if (value & 1) pic_set_irq_new(s, 0, 0); break; case 10: /* FRQ_ENABLESET */ s->fiq_enabled |= value; break; case 11: /* FRQ_ENABLECLR */ s->fiq_enabled &= ~value; break; case 0: /* IRQ_STATUS */ case 1: /* IRQ_RAWSTAT */ case 8: /* FRQ_STATUS */ case 9: /* FRQ_RAWSTAT */ default: printf ("icp_pic_write: Bad register offset 0x%x\n", offset); return; } icp_pic_update(s); } static CPUReadMemoryFunc *icp_pic_readfn[] = { icp_pic_read, icp_pic_read, icp_pic_read }; static CPUWriteMemoryFunc *icp_pic_writefn[] = { icp_pic_write, icp_pic_write, icp_pic_write }; static icp_pic_state *icp_pic_init(uint32_t base, void *parent, int parent_irq, int parent_fiq) { icp_pic_state *s; int iomemtype; s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state)); if (!s) return NULL; s->handler = icp_pic_set_irq; s->base = base; s->parent = parent; s->parent_irq = parent_irq; s->parent_fiq = parent_fiq; iomemtype = cpu_register_io_memory(0, icp_pic_readfn, icp_pic_writefn, s); cpu_register_physical_memory(base, 0x007fffff, iomemtype); /* ??? Save/restore. */ return s; } /* CP control registers. */ typedef struct { uint32_t base; } icp_control_state; static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset) { icp_control_state *s = (icp_control_state *)opaque; offset -= s->base; switch (offset >> 2) { case 0: /* CP_IDFIELD */ return 0x41034003; case 1: /* CP_FLASHPROG */ return 0; case 2: /* CP_INTREG */ return 0; case 3: /* CP_DECODE */ return 0x11; default: cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", offset); return 0; } } static void icp_control_write(void *opaque, target_phys_addr_t offset, uint32_t value) { icp_control_state *s = (icp_control_state *)opaque; offset -= s->base; switch (offset >> 2) { case 1: /* CP_FLASHPROG */ case 2: /* CP_INTREG */ case 3: /* CP_DECODE */ /* Nothing interesting implemented yet. */ break; default: cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", offset); } } static CPUReadMemoryFunc *icp_control_readfn[] = { icp_control_read, icp_control_read, icp_control_read }; static CPUWriteMemoryFunc *icp_control_writefn[] = { icp_control_write, icp_control_write, icp_control_write }; static void icp_control_init(uint32_t base) { int iomemtype; icp_control_state *s; s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state)); iomemtype = cpu_register_io_memory(0, icp_control_readfn, icp_control_writefn, s); cpu_register_physical_memory(base, 0x007fffff, iomemtype); s->base = base; /* ??? Save/restore. */ } /* Board init. */ static void integratorcp_init(int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, uint32_t cpuid) { CPUState *env; uint32_t bios_offset; icp_pic_state *pic; void *cpu_pic; env = cpu_init(); cpu_arm_set_model(env, cpuid); bios_offset = ram_size + vga_ram_size; /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ /* ??? RAM shoud repeat to fill physical memory space. */ /* SDRAM at address zero*/ cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); /* And again at address 0x80000000 */ cpu_register_physical_memory(0x80000000, ram_size, IO_MEM_RAM); integratorcm_init(ram_size >> 20, bios_offset); cpu_pic = arm_pic_init_cpu(env); pic = icp_pic_init(0x14000000, cpu_pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ); icp_pic_init(0xca000000, pic, 26, -1); icp_pit_init(0x13000000, pic, 5); pl011_init(0x16000000, pic, 1, serial_hds[0]); pl011_init(0x17000000, pic, 2, serial_hds[1]); icp_control_init(0xcb000000); pl050_init(0x18000000, pic, 3, 0); pl050_init(0x19000000, pic, 4, 1); if (nd_table[0].vlan) { if (nd_table[0].model == NULL || strcmp(nd_table[0].model, "smc91c111") == 0) { smc91c111_init(&nd_table[0], 0xc8000000, pic, 27); } else { fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); exit (1); } } pl110_init(ds, 0xc0000000, pic, 22, 0); arm_load_kernel(ram_size, kernel_filename, kernel_cmdline, initrd_filename, 0x113); } static void integratorcp926_init(int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename) { integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename, snapshot, kernel_filename, kernel_cmdline, initrd_filename, ARM_CPUID_ARM926); } static void integratorcp1026_init(int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename) { integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename, snapshot, kernel_filename, kernel_cmdline, initrd_filename, ARM_CPUID_ARM1026); } QEMUMachine integratorcp926_machine = { "integratorcp926", "ARM Integrator/CP (ARM926EJ-S)", integratorcp926_init, }; QEMUMachine integratorcp1026_machine = { "integratorcp1026", "ARM Integrator/CP (ARM1026EJ-S)", integratorcp1026_init, };