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* Fixed bug #1010.Giovanni Di Sirio2019-02-071-0/+1
| | | | git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_19.1.x@12641 110e8d01-0319-4d1e-a829-52ad28d1bb01
* Mass update of all drivers to use the new DMA API. What could possibly go wrong?Giovanni Di Sirio2019-01-022-50/+60
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* Dynamic DMA allocation for STM32H7xx.Giovanni Di Sirio2018-12-282-1/+17
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* DMA rework.Giovanni Di Sirio2018-12-282-117/+300
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* git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12412 ↵Giovanni Di Sirio2018-11-091-0/+4
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* Mass update of the Apache 2.0 license statement.Giovanni Di Sirio2018-01-202-2/+2
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* Defaulted all STM32 drivers to enable peripheral clocks during stop/sleep ↵Giovanni Di Sirio2018-01-171-2/+2
| | | | | | modes. Now RCC macros are able to set or clear the LP bit of a peripheral. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11300 35acf78f-673a-0410-8e92-d51de3d6d3f4
* SPIv1 and SPIv2 circular mode added. Rework of RCC files and all ↵Giovanni Di Sirio2018-01-101-2/+2
| | | | | | dependencies inside STM32 drivers. Documentation fixes in some HAL modules. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11247 35acf78f-673a-0410-8e92-d51de3d6d3f4
* Unified MPU handler.Giovanni Di Sirio2018-01-081-2/+0
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* Added unified cache handler for Cortex-M devices.Giovanni Di Sirio2018-01-082-71/+2
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* SPI driver works, probably optimizations are possible.Giovanni Di Sirio2018-01-051-0/+1
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* Documentation fixes.Giovanni Di Sirio2017-10-041-1/+1
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* Added new macro to DMAv2 dmaStreamGetCurrentTarget().Giovanni Di Sirio2017-09-241-0/+14
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* DMAv2 fixes for STM32F76x/77x.Giovanni Di Sirio2017-04-021-1/+1
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* Introduced modularized driver makefiles.gdisirio2017-01-161-0/+2
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* Updated header guards for STM32 files.Giovanni Di Sirio2016-04-021-3/+3
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* Mass license update.Giovanni Di Sirio2016-03-182-2/+2
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* SDMMC1 now compilable on STM32L4.Giovanni Di Sirio2015-12-161-3/+12
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* Restored original dmaStreamDisable() macro.gdisirio2015-09-021-3/+4
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* Improved M7 cache handling.Giovanni Di Sirio2015-08-272-13/+159
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* git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8242 ↵Giovanni Di Sirio2015-08-262-0/+33
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* SPI working on F7 but cache handling unfinished.Giovanni Di Sirio2015-08-262-14/+6
| | | | git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8241 35acf78f-673a-0410-8e92-d51de3d6d3f4
* git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8212 ↵gdisirio2015-08-131-6/+12
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* git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8210 ↵gdisirio2015-08-131-19/+0
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* Added cache handling to DMAv2 driver.gdisirio2015-08-132-0/+42
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* New STM32 ADCv2 driver.Giovanni Di Sirio2015-08-051-0/+17
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* STM32 DMAv2 driver added.Giovanni Di Sirio2015-08-042-0/+991
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8156 35acf78f-673a-0410-8e92-d51de3d6d3f4
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