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/* Name: usbdrvasm18.inc
 * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
 * Author: Lukas Schrittwieser (based on 20 MHz usbdrvasm20.inc by Jeroen Benschop)
 * Creation Date: 2009-01-20
 * Tabsize: 4
 * Copyright: (c) 2008 by Lukas Schrittwieser and OBJECTIVE DEVELOPMENT Software GmbH
 * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
 * Revision: $Id: usbdrvasm18-crc.inc 740 2009-04-13 18:23:31Z cs $
 */

/* Do not link this file! Link usbdrvasm.S instead, which includes the
 * appropriate implementation!
 */

/*
General Description:
This file is the 18 MHz version of the asssembler part of the USB driver. It
requires a 18 MHz crystal (not a ceramic resonator and not a calibrated RC
oscillator).

See usbdrv.h for a description of the entire driver.

Since almost all of this code is timing critical, don't change unless you
really know what you are doing! Many parts require not only a maximum number
of CPU cycles, but even an exact number of cycles!
*/


;max stack usage: [ret(2), YL, SREG, YH, [sofError], bitcnt(x5), shift, x1, x2, x3, x4, cnt, ZL, ZH] = 14 bytes
;nominal frequency: 18 MHz -> 12 cycles per bit
; Numbers in brackets are clocks counted from center of last sync bit
; when instruction starts
;register use in receive loop to receive the data bytes:
; shift assembles the byte currently being received
; x1 holds the D+ and D- line state
; x2 holds the previous line state
; cnt holds the number of bytes left in the receive buffer
; x3 holds the higher crc byte (see algorithm below)
; x4 is used as temporary register for the crc algorithm
; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further
;    unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted
; zl lower crc value and crc table index
; zh used for crc table accesses

;--------------------------------------------------------------------------------------------------------------
; CRC mods:
;  table driven crc checker, Z points to table in prog space
;   ZL is the lower crc byte, x3 is the higher crc byte
;	x4 is used as temp register to store different results
;	the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the
;	first data byte an virtual zero data byte is added to the crc register, this results in the correct initial
;	value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc.
;	The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and
;	tabL[0x54] = 0x01  ->  crcL = 0x01 xor 0xFE = 0xFF
;  bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version
;--------------------------------------------------------------------------------------------------------------
; CRC algorithm:
;	The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form
;	i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order
;	bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i
;	propose a research on CRC :-) )
;	Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc
;	table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3
;	(its destination).
;	Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as
;	we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored
;	to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc
; 	calculation is done.
;	Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec)
;	however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized
;	to a magic number which results in a crc value of 0xFFFF after the first complete byte.
;
;	This algorithm is split into the extra cycles of the different bits:
;	bit7:	XOR the received byte to ZL
;	bit5:	load the new high byte to x4
;	bit6:	load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value)
;			move x4 (the new high byte) to x3, the crc value is ready
;


macro POP_STANDARD ; 18 cycles
    pop		ZH
    pop		ZL
	pop     cnt
    pop     x5
    pop     x3
    pop     x2
    pop     x1
    pop     shift
    pop     x4
    endm
macro POP_RETI     ; 7 cycles
    pop     YH
    pop     YL
    out     SREG, YL
    pop     YL
    endm

macro CRC_CLEANUP_AND_CHECK
	; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor
	; x3 is the higher crc byte, zl the lower one
	ldi		ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table
	lpm		x2, Z				;[+2][+3][+4]
	ldi		ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table
	lpm		ZL, Z				;[+6][+7][+8]
	eor		ZL, x3				;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value
	cpi		ZL, 0x01			;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec)
	brne	ignorePacket		;[+9] detected a crc fault -> paket is ignored and retransmitted by the host
	cpi		x2, 0xb0			;[+10]
	brne	ignorePacket		;[+11] detected a crc fault -> paket is ignored and retransmitted by the host
    endm


USB_INTR_VECTOR:
;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH
    push    YL                  ;[-28] push only what is necessary to sync with edge ASAP
    in      YL, SREG            ;[-26]
    push    YL                  ;[-25]
    push    YH                  ;[-23]
;----------------------------------------------------------------------------
; Synchronize with sync pattern:
;----------------------------------------------------------------------------
;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
;sync up with J to K edge during sync pattern -- use fastest possible loops
;The first part waits at most 1 bit long since we must be in sync pattern.
;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
;waitForJ, ensure that this prerequisite is met.
waitForJ:
    inc     YL
    sbis    USBIN, USBMINUS
    brne    waitForJ        ; just make sure we have ANY timeout
waitForK:
;The following code results in a sampling window of < 1/4 bit which meets the spec.
    sbis    USBIN, USBMINUS     ;[-17]
    rjmp    foundK              ;[-16]
    sbis    USBIN, USBMINUS
    rjmp    foundK
    sbis    USBIN, USBMINUS
    rjmp    foundK
    sbis    USBIN, USBMINUS
    rjmp    foundK
    sbis    USBIN, USBMINUS
    rjmp    foundK
    sbis    USBIN, USBMINUS
    rjmp    foundK
    sbis    USBIN, USBMINUS
    rjmp    foundK
    sbis    USBIN, USBMINUS
    rjmp    foundK
    sbis    USBIN, USBMINUS
    rjmp    foundK
#if USB_COUNT_SOF
    lds     YL, usbSofCount
    inc     YL
    sts     usbSofCount, YL
#endif  /* USB_COUNT_SOF */
#ifdef USB_SOF_HOOK
    USB_SOF_HOOK
#endif
    rjmp    sofError
foundK:                         ;[-15]
;{3, 5} after falling D- edge, average delay: 4 cycles
;bit0 should be at 30  (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample
;use 1 bit time for setup purposes, then sample again. Numbers in brackets
;are cycles from center of first sync (double K) bit after the instruction
    push    x4                  ;[-14]
;   [---]                       ;[-13]
    lds     YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers
;   [---]                       ;[-11]
    clr     YH                  ;[-10]
    subi    YL, lo8(-(usbRxBuf));[-9] [rx loop init]
    sbci    YH, hi8(-(usbRxBuf));[-8] [rx loop init]
    push    shift               ;[-7]
;   [---]                       ;[-6]
    ldi		shift, 0x80			;[-5] the last bit is the end of byte marker for the pid receiver loop
    clc			      	      	;[-4] the carry has to be clear for receipt of pid bit 0
    sbis    USBIN, USBMINUS     ;[-3] we want two bits K (sample 3 cycles too early)
    rjmp    haveTwoBitsK        ;[-2]
    pop     shift               ;[-1] undo the push from before
    pop     x4                  ;[1]
    rjmp    waitForK            ;[3] this was not the end of sync, retry
; The entire loop from waitForK until rjmp waitForK above must not exceed two
; bit times (= 24 cycles).

;----------------------------------------------------------------------------
; push more registers and initialize values while we sample the first bits:
;----------------------------------------------------------------------------
haveTwoBitsK:
    push    x1                  ;[0]
    push    x2                  ;[2]
    push    x3                  ;[4] crc high byte
    ldi     x2, 1<<USBPLUS      ;[6] [rx loop init] current line state is K state. D+=="1", D-=="0"
    push    x5                  ;[7]
    push    cnt                 ;[9]
    ldi     cnt, USB_BUFSIZE    ;[11]


;--------------------------------------------------------------------------------------------------------------
; receives the pid byte
; there is no real unstuffing algorithm implemented here as a stuffing bit is impossible in the pid byte.
; That's because the last four bits of the byte are the inverted of the first four bits. If we detect a
; unstuffing condition something went wrong and abort
; shift has to be initialized to 0x80
;--------------------------------------------------------------------------------------------------------------

; pid bit 0 - used for even more register saving (we need the z pointer)
	in      x1, USBIN           ;[0] sample line state
    andi    x1, USBMASK         ;[1] filter only D+ and D- bits
    eor		x2, x1				;[2] generate inverted of actual bit
	sbrc	x2, USBMINUS		;[3] if the bit is set we received a zero
	sec							;[4]
	ror		shift				;[5] we perform no unstuffing check here as this is the first bit
	mov		x2, x1				;[6]
	push	ZL					;[7]
								;[8]
	push	ZH					;[9]
								;[10]
	ldi		x3, 0xFE			;[11] x3 is the high order crc value


bitloopPid:						
	in      x1, USBIN           ;[0] sample line state
   	andi    x1, USBMASK         ;[1] filter only D+ and D- bits
    breq    nse0                ;[2] both lines are low so handle se0	
	eor		x2, x1				;[3] generate inverted of actual bit
	sbrc	x2, USBMINUS		;[4] set the carry if we received a zero
	sec							;[5]
	ror		shift				;[6]
	ldi		ZL, 0x54			;[7] ZL is the low order crc value
	ser		x4					;[8] the is no bit stuffing check here as the pid bit can't be stuffed. if so
								; some error occured. In this case the paket is discarded later on anyway.
	mov		x2, x1				;[9] prepare for the next cycle
	brcc	bitloopPid			;[10] while 0s drop out of shift we get the next bit
	eor		x4, shift			;[11] invert all bits in shift and store result in x4

;--------------------------------------------------------------------------------------------------------------
; receives data bytes and calculates the crc
; the last USBIN state has to be in x2
; this is only the first half, due to branch distanc limitations the second half of the loop is near the end
; of this asm file
;--------------------------------------------------------------------------------------------------------------

rxDataStart:
    in      x1, USBIN           ;[0] sample line state (note: a se0 check is not useful due to bit dribbling)
    ser		x5					;[1] prepare the unstuff marker register
    eor		x2, x1             	;[2] generates the inverted of the actual bit


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