diff options
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/LPC17xx/mac_lld.c | 784 | ||||
| -rw-r--r-- | os/hal/platforms/LPC17xx/mac_lld.h | 661 | ||||
| -rw-r--r-- | os/hal/platforms/LPC17xx/platform.mk | 3 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1766.ld | 9 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1769.ld | 11 |
5 files changed, 1466 insertions, 2 deletions
diff --git a/os/hal/platforms/LPC17xx/mac_lld.c b/os/hal/platforms/LPC17xx/mac_lld.c new file mode 100644 index 000000000..bdf1c9a91 --- /dev/null +++ b/os/hal/platforms/LPC17xx/mac_lld.c @@ -0,0 +1,784 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + This file has been contributed by: + Marcin Jokel. +*/ + +/** + * @file LPC17xx/mac_lld.c + * @brief LPC17xx low level MAC driver code. + * + * @addtogroup MAC + * @{ + */ + +#include <string.h> + +#include "ch.h" +#include "hal.h" +#include "mii.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define BUFFER_SIZE ((((LPC17xx_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) + +/* MII divider optimal value.*/ +#if (LPC17xx_CCLK <= 50000000) +#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_20 +#elif (LPC17xx_CCLK <= 70000000) +#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_28 +#elif (LPC17xx_CCLK <= 80000000) +#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_36 +#elif (LPC17xx_CCLK <= 90000000) +#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_40 +#elif (LPC17xx_CCLK <= 100000000) +#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_44 +#elif (LPC17xx_CCLK <= 120000000) +#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_48 +#else +#error "LPC17xx_CCLK over maximum frequency for ETH operations (120MHz)" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Ethernet driver 1. + */ +MACDriver ETHD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, + 0x37, 0x01, 0x10}; + +static lpc17xx_eth_rx_descriptor_t rd[LPC17xx_MAC_RECEIVE_BUFFERS] + __attribute__((aligned(4))) __attribute__((section(".eth_ram"))); +static lpc17xx_eth_tx_descriptor_t td[LPC17xx_MAC_TRANSMIT_BUFFERS] + __attribute__((aligned(4))) __attribute__((section(".eth_ram"))); + +static lpc17xx_eth_tx_descriptor_t td_tmp[LPC17xx_MAC_TRANSMIT_BUFFERS] + __attribute__((aligned(4))) __attribute__((section(".eth_ram"))); + +static lpc17xx_eth_rx_status_t rd_stat[LPC17xx_MAC_RECEIVE_BUFFERS] + __attribute__((aligned(8))) __attribute__((section(".eth_ram"))); +static lpc17xx_eth_tx_status_t td_stat[LPC17xx_MAC_TRANSMIT_BUFFERS] + __attribute__((aligned(4))) __attribute__((section(".eth_ram"))); + +static uint32_t rb[LPC17xx_MAC_RECEIVE_BUFFERS][BUFFER_SIZE] + __attribute__((aligned(4))) __attribute__((section(".eth_ram"))); +static uint32_t tb[LPC17xx_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE] + __attribute__((aligned(4))) __attribute__((section(".eth_ram"))); + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Writes a PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * @param[in] value new register value + */ +void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) { + + LPC_EMAC->MCMD = 0; + LPC_EMAC->MADR = macp->phyaddr | reg; /* Write PHY address and register address */ + LPC_EMAC->MWTD = value; /* Write data */ + while((LPC_EMAC->MIND & EMAC_MIND_BUSY) != 0) + ; /* Wait for busy bit to be cleared in MIND */ + +} + +/** + * @brief Reads a PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * + * @return The PHY register content. + */ +uint32_t mii_read(MACDriver *macp, uint32_t reg) { + + LPC_EMAC->MCMD = 1; + LPC_EMAC->MADR = macp->phyaddr | reg; /* Write PHY address and register address */ + while((LPC_EMAC->MIND & EMAC_MIND_BUSY) != 0) + ; /* Wait for busy bit to be cleared in MIND */ + LPC_EMAC->MCMD = 0; + return LPC_EMAC->MRDD; +} + +#if !defined(BOARD_PHY_ADDRESS) +/** + * @brief PHY address detection. + * + * @param[in] macp pointer to the @p MACDriver object + */ +void mii_find_phy(MACDriver *macp) { + uint32_t i; + +#if LPC17xx_MAC_PHY_TIMEOUT > 0 + halrtcnt_t start = halGetCounterValue(); + halrtcnt_t timeout = start + MS2RTT(LPC17xx_MAC_PHY_TIMEOUT); + while (halIsCounterWithin(start, timeout)) { +#endif + for (i = 0; i < 31; i++) { + macp->phyaddr = i << 8; + if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) && + ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { + return; + } + } +#if LPC17xx_MAC_PHY_TIMEOUT > 0 + } +#endif + /* Wrong or defective board.*/ + chSysHalt(); +} +#endif + +/** + * @brief MAC address setup. + * + * @param[in] p pointer to a six bytes buffer containing the MAC + * address + */ +static void mac_lld_set_address(const uint8_t *p) { + + /* MAC address configuration, only a single address comparator is used, + hash table not used.*/ + + LPC_EMAC->SA0 = ((uint32_t)p[5] << 8) | + ((uint32_t)p[4] << 0); + LPC_EMAC->SA1 = ((uint32_t)p[3] << 8) | + ((uint32_t)p[2] << 0); + LPC_EMAC->SA2 = ((uint32_t)p[1] << 8) | + ((uint32_t)p[0] << 0); + + LPC_EMAC->HashFilterL = 0; + LPC_EMAC->HashFilterH = 0; + + LPC_EMAC->RxFilterCtrl = EMAC_RXFILCTRL_PERFECT_EN | EMAC_RXFILCTRL_BROADCAST_EN; + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +CH_IRQ_HANDLER(VectorB0) { + + uint32_t intstatus; + uint32_t consume_index; + uint32_t txdescn; + + CH_IRQ_PROLOGUE(); + + intstatus = LPC_EMAC->IntStatus; + LPC_EMAC->IntClear = intstatus; + + if (intstatus & EMAC_INTSTAT_RX_OVERRUN) { + /* Reset receive logic. */ + LPC_EMAC->MAC1 |= EMAC_MAC1_RESET_RX | EMAC_MAC1_RESET_MCS_RX; + __NOP(); + LPC_EMAC->MAC1 &= ~(EMAC_MAC1_RESET_RX | EMAC_MAC1_RESET_MCS_RX); + } + + if (intstatus & EMAC_INTSTAT_TX_UNDERRUN) { + /* Reset transmit logic. */ + LPC_EMAC->MAC1 |= EMAC_MAC1_RESET_TX | EMAC_MAC1_RESET_MCS_TX; + __NOP(); + LPC_EMAC->MAC1 &= ~(EMAC_MAC1_RESET_TX | EMAC_MAC1_RESET_MCS_TX); + } + + if (intstatus & EMAC_INTSTAT_RX_DONE) { + /* Data Received.*/ + chSysLockFromIsr(); + chSemResetI(ÐD1.rdsem, 0); +#if MAC_USE_EVENTS + chEvtBroadcastI(ÐD1.rdevent); +#endif + chSysUnlockFromIsr(); + } + + if (intstatus & EMAC_INTSTAT_TX_DONE) { + /* Data Transmitted.*/ + consume_index = LPC_EMAC->TxConsumeIndex; + if (consume_index == 0) + consume_index = LPC17xx_MAC_TRANSMIT_BUFFERS - 1; + else + consume_index--; + txdescn = (td[consume_index].control >> 12) & 0x000000FF; + td_tmp[txdescn].control = 0; /* Unlock temporary descriptor. */ + chSysLockFromIsr(); + chSemResetI(ÐD1.tdsem, 0); + chSysUnlockFromIsr(); + } + + CH_IRQ_EPILOGUE(); + +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) { + unsigned i; + + macObjectInit(ÐD1); + ETHD1.link_up = FALSE; + + LPC_SC->PCONP |= (1 << 30); /* Power up MAC */ + + /* Rx desciptor and Rx status tables are initialized. */ + for (i = 0; i < LPC17xx_MAC_RECEIVE_BUFFERS; i++) { + rd[i].packet = (uint32_t) &rb[i]; + rd[i].control = EMAC_RXSTATUS_CTRL_INT | (LPC17xx_MAC_BUFFERS_SIZE - 1); + + rd_stat[i].info = 0; + rd_stat[i].hashcrc = 0; + } + + /* Tx desciptor and Tx status tables are cleared. They are set up every time + when transmission starts. */ + for (i = 0; i < LPC17xx_MAC_TRANSMIT_BUFFERS; i++) { + td[i].packet = 0; + td[i].control = 0; + td_stat[i] = 0; + + td_tmp[i].packet = (uint32_t) &tb[i]; + td_tmp[i].control = 0; + } + + /* Reset all EMAC internal modules. */ + LPC_EMAC->MAC1 = EMAC_MAC1_RESET_TX | EMAC_MAC1_RESET_MCS_TX | EMAC_MAC1_RESET_RX | + EMAC_MAC1_RESET_MCS_RX | EMAC_MAC1_SIM_RESET | EMAC_MAC1_SOFT_RESET; + LPC_EMAC->Command = EMAC_COMMAND_REG_RESET | EMAC_COMMAND_TX_RESET | EMAC_COMMAND_RX_RESET; + LPC_EMAC->MCFG = EMAC_MCFG_RESET_MII_MGMT; /* Reset MII Managment hardware. */ + + halPolledDelay(LPC17XX_MAC_RESET_DELAY); + + LPC_EMAC->MAC1 = 0; /* MAC reset de-asserted. */ + + /* Selection of the RMII or MII mode based on info exported by board.h.*/ +#if defined(BOARD_PHY_RMII) + LPC_EMAC->Command = EMAC_COMMAND_RMII | EMAC_COMMAND_PASS_RUN_FRAME; +#else + LPC_EMAC->Command = EMAC_COMMAND_PASS_RUN_FRAME; +#endif + + LPC_EMAC->MCFG = MAC_MII_MCFG_CLK_SEL; /* Set MII clock divider. */ + + /* PHY address setup.*/ +#if defined(BOARD_PHY_ADDRESS) + ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11; +#else + mii_find_phy(ÐD1); +#endif + +#if defined(BOARD_PHY_RESET) + /* PHY board-specific reset procedure.*/ + BOARD_PHY_RESET(); +#else + /* PHY soft reset procedure.*/ + mii_write(ÐD1, MII_BMCR, BMCR_RESET); +#if defined(BOARD_PHY_RESET_DELAY) + halPolledDelay(BOARD_PHY_RESET_DELAY); +#endif + while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET) + ; +#endif + +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + + /* PHY in power up mode.*/ + mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); + + /* MAC registers configuration.*/ + LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL_REC; + LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_CRC_EN; + LPC_EMAC->MAXF = LPC17XX_MAC_MAX_FLEN; + LPC_EMAC->CLRT = LPC17XX_MAC_CLRT_DEF; + LPC_EMAC->IPGR = LPC17XX_MAC_IPGR_DEF; + + /* MAC descriptor registers configuration. */ + macp->rxsoftindex = 0; + LPC_EMAC->RxDescriptor = (uint32_t) &rd[0]; + LPC_EMAC->RxDescriptorNumber = LPC17xx_MAC_RECEIVE_BUFFERS - 1; + LPC_EMAC->RxConsumeIndex = 0; + LPC_EMAC->RxStatus = (uint32_t) &rd_stat[0]; + + macp->txsoftindex = 0; + LPC_EMAC->TxDescriptor = (uint32_t) &td[0]; + LPC_EMAC->TxDescriptorNumber = LPC17xx_MAC_TRANSMIT_BUFFERS - 1; + LPC_EMAC->TxProduceIndex = 0; + LPC_EMAC->TxStatus = (uint32_t) &td_stat[0]; + + /* MAC address setup.*/ + if (macp->config->mac_address == NULL) + mac_lld_set_address(default_mac_address); + else + mac_lld_set_address(macp->config->mac_address); + + /* Enable EMAC interrupts. */ + LPC_EMAC->IntEnable = EMAC_INTEN_TX_DONE | EMAC_INTEN_RX_DONE | + EMAC_INTEN_RX_OVERRUN | EMAC_INTEN_TX_UNDERRUN; + + /* Reset all interrupts. */ + LPC_EMAC->IntClear = 0xFFFF; + + /* ISR vector enabled.*/ + nvicEnableVector(ENET_IRQn, CORTEX_PRIORITY_MASK(LPC17xx_MAC_ETH_IRQ_PRIORITY)); + + /* Enable receive and transmit mode. */ + LPC_EMAC->Command |= EMAC_COMMAND_TX_ENABLE | EMAC_COMMAND_RX_ENABLE; + LPC_EMAC->MAC1 |= EMAC_MAC1_RECEIVE_EN; + +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { + + if (macp->state != MAC_STOP) { + + /* MAC and DMA stopped.*/ + LPC_EMAC->MAC1 = 0; + LPC_EMAC->Command = 0; + LPC_EMAC->IntEnable = 0; + + /* PHY in power down mode until the driver will be restarted.*/ + mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); + + /* ISR vector disabled.*/ + nvicDisableVector(ENET_IRQn); + } + +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) { + uint32_t produce_index; + uint32_t produce_index_next; + + if (!macp->link_up) + return RDY_TIMEOUT; + + chSysLock(); + + /* Get Current TX descriptor.*/ + produce_index = macp->txsoftindex; + + produce_index_next = (produce_index + 1) % LPC17xx_MAC_TRANSMIT_BUFFERS; + if (produce_index_next == LPC_EMAC->TxConsumeIndex) { + /* Full */ + chSysUnlock(); + return RDY_TIMEOUT; + } + + /* Ensure that descriptor isn't locked by the Ethernet DMA or + another thread.*/ + if (td_tmp[produce_index].control == EMAC_TXSTATUS_CTRL_LOCK) { + chSysUnlock(); + return RDY_TIMEOUT; + } + + /* Marks the current descriptor as locked using a reserved bit.*/ + td_tmp[produce_index].control = EMAC_TXSTATUS_CTRL_LOCK; + + /* Next TX descriptor to use.*/ + macp->txsoftindex = produce_index_next; + + chSysUnlock(); + + /* Set the buffer size and configuration.*/ + tdp->offset = 0; + tdp->size = LPC17xx_MAC_BUFFERS_SIZE; + tdp->txdescn = produce_index; + + return RDY_OK; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { + + uint32_t produce_index; + uint32_t descn; + + chSysLock(); + + produce_index = LPC_EMAC->TxProduceIndex; + descn = tdp->txdescn; + + /* Set control bits and save temporary descriptor number. */ + td[produce_index].control = EMAC_TXSTATUS_CTRL_INT | EMAC_TXSTATUS_CTRL_LAST | (descn << 12) | + (tdp->offset - 1); + + td[produce_index].packet = td_tmp[descn].packet; + LPC_EMAC->TxProduceIndex = (LPC_EMAC->TxProduceIndex + 1) % LPC17xx_MAC_TRANSMIT_BUFFERS; + chSysUnlock(); +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) { + uint32_t consume_index; + uint32_t status; + + chSysLock(); + + /* Get current rx descriptor number.*/ + consume_index = macp->rxsoftindex; + + if (LPC_EMAC->RxProduceIndex != consume_index) { + status = rd_stat[consume_index].info; + if (status != EMAC_RXSTATUS_INFO_ERROR) { + /* Found a valid one.*/ + rdp->offset = 0; + rdp->size = (status & EMAC_RXSTATUS_INFO_SIZE_MASK) + 1; + rdp->rxdescn = consume_index; + + macp->rxsoftindex = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS; + + chSysUnlock(); + return RDY_OK; + } + else { + /* Invalid frame found. */ + if (LPC_EMAC->RxConsumeIndex == consume_index) { + consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS; + LPC_EMAC->RxConsumeIndex = consume_index; + } + else { + rd[consume_index].control |= EMAC_RXSTATUS_CTRL_READY; + consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS; + } + macp->rxsoftindex = consume_index; + } + } + + chSysUnlock(); + + return RDY_TIMEOUT; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { + + uint32_t consume_index; + + chSysLock(); + + /* Only descriptor with number match RxConsumeIndex can release receive descriptors. */ + consume_index = LPC_EMAC->RxConsumeIndex; + + if (rdp->rxdescn == consume_index) { + consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS; + + while (LPC_EMAC->RxProduceIndex != consume_index) { + if (rd[consume_index].control & EMAC_RXSTATUS_CTRL_READY) { + rd[consume_index].control &= ~EMAC_RXSTATUS_CTRL_READY; + consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS; + } + else { + break; + } + } + + LPC_EMAC->RxConsumeIndex = consume_index; + } + else { + rd[rdp->rxdescn].control |= EMAC_RXSTATUS_CTRL_READY; + } + + chSysUnlock(); +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool_t mac_lld_poll_link_status(MACDriver *macp) { + uint32_t mac2, cmd, ipgt, supp, bmsr, bmcr; + + mac2 = LPC_EMAC->MAC2; + cmd = LPC_EMAC->Command; + + /* PHY CR and SR registers read.*/ + (void)mii_read(macp, MII_BMSR); + bmsr = mii_read(macp, MII_BMSR); + bmcr = mii_read(macp, MII_BMCR); + + /* Check on auto-negotiation mode.*/ + if (bmcr & BMCR_ANENABLE) { + uint32_t lpa; + + /* Auto-negotiation must be finished without faults and link established.*/ + if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != + (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) + return macp->link_up = FALSE; + + /* Auto-negotiation enabled, checks the LPA register.*/ + lpa = mii_read(macp, MII_LPA); + + /* Check on link speed.*/ + if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) + supp = EMAC_SUPP_SPEED; + else + supp = 0; + + /* Check on link mode.*/ + if (lpa & (LPA_10FULL | LPA_100FULL)) { + mac2 |= EMAC_MAC2_FULL_DUPLEX; + cmd |= EMAC_COMMAND_FULL_DUPLEX; + ipgt = LPC17XX_MAC_IPGT_FULL_DUPLEX_DEF; + } + else { + mac2 &= ~EMAC_MAC2_FULL_DUPLEX; + cmd &= ~EMAC_COMMAND_FULL_DUPLEX; + ipgt = LPC17XX_MAC_IPGT_HALF_DUPLEX_DEF; + } + } + else { + /* Link must be established.*/ + if (!(bmsr & BMSR_LSTATUS)) + return macp->link_up = FALSE; + + /* Check on link speed.*/ + if (bmcr & BMCR_SPEED100) + supp = EMAC_SUPP_SPEED; + else + supp = 0; + + /* Check on link mode.*/ + if (bmcr & BMCR_FULLDPLX) { + mac2 |= EMAC_MAC2_FULL_DUPLEX; + cmd |= EMAC_COMMAND_FULL_DUPLEX; + ipgt = LPC17XX_MAC_IPGT_FULL_DUPLEX_DEF; + } + else { + mac2 &= ~EMAC_MAC2_FULL_DUPLEX; + cmd &= ~EMAC_COMMAND_FULL_DUPLEX; + ipgt = LPC17XX_MAC_IPGT_HALF_DUPLEX_DEF; + } + } + + LPC_EMAC->MAC2 = mac2; + LPC_EMAC->SUPP = supp; + LPC_EMAC->Command = cmd; + LPC_EMAC->IPGT = ipgt; + + /* Returns the link status.*/ + return macp->link_up = TRUE; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) { + + if (size > tdp->size - tdp->offset) + size = tdp->size - tdp->offset; + + if (size > 0) { + memcpy((uint8_t *)td_tmp[tdp->txdescn].packet + tdp->offset, buf, size); + tdp->offset += size; + } + return size; + +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) { + + if (size > rdp->size - rdp->offset) + size = rdp->size - rdp->offset; + + if (size > 0) { + memcpy(buf, (uint8_t *)rd[rdp->rxdescn].packet + rdp->offset, size); + rdp->offset += size; + } + + return size; +} + +#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) +/** + * @brief Returns a pointer to the next transmit buffer in the descriptor + * chain. + * @note The API guarantees that enough buffers can be requested to fill + * a whole frame. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] size size of the requested buffer. Specify the frame size + * on the first call then scale the value down subtracting + * the amount of data already copied into the previous + * buffers. + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * Note that a returned size lower than the amount + * requested means that more buffers must be requested + * in order to fill the frame data entirely. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep) { + + if (tdp->offset == 0) { + *sizep = tdp->size; + tdp->offset = size; + return (uint8_t *)td_tmp[tdp->txdescn].packet; + } + *sizep = 0; + return NULL; +} + +/** + * @brief Returns a pointer to the next receive buffer in the descriptor + * chain. + * @note The API guarantees that the descriptor chain contains a whole + * frame. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep) { + + if (rdp->size > 0) { + *sizep = rdp->size; + rdp->offset = rdp->size; + rdp->size = 0; + return (uint8_t *)rd[rdp->rxdescn].packet; + } + *sizep = 0; + return NULL; +} +#endif /* MAC_USE_ZERO_COPY */ + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/platforms/LPC17xx/mac_lld.h b/os/hal/platforms/LPC17xx/mac_lld.h new file mode 100644 index 000000000..bc9382c5c --- /dev/null +++ b/os/hal/platforms/LPC17xx/mac_lld.h @@ -0,0 +1,661 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + This file has been contributed by: + Marcin Jokel. +*/ + +/** + * @file LPC17xx/mac_lld.h + * @brief LPC17xx low level MAC driver header. + * + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_LLD_H_ +#define _MAC_LLD_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This implementation supports the zero-copy mode API. + */ +#define MAC_SUPPORTS_ZERO_COPY TRUE + +/** + * @name MAC Configuration Register 1 bits + * @{ + */ +#define EMAC_MAC1_RECEIVE_EN (1UL << 0) +#define EMAC_MAC1_PASS_ALL_REC (1UL << 1) +#define EMAC_MAC1_RX_FLOW_CTRL (1UL << 2) +#define EMAC_MAC1_TX_FLOW_CTRL (1UL << 3) +#define EMAC_MAC1_LOOPBACK (1UL << 4) +#define EMAC_MAC1_RESET_TX (1UL << 8) +#define EMAC_MAC1_RESET_MCS_TX (1UL << 9) +#define EMAC_MAC1_RESET_RX (1UL << 10) +#define EMAC_MAC1_RESET_MCS_RX (1UL << 11) +#define EMAC_MAC1_SIM_RESET (1UL << 14) +#define EMAC_MAC1_SOFT_RESET (1UL << 15) + +/** + * @name MAC Configuration Register 2 bits + * @{ + */ +#define EMAC_MAC2_FULL_DUPLEX (1UL << 0) +#define EMAC_MAC2_FRAME_LEN_CHECK (1UL << 1) +#define EMAC_MAC2_HUGE_FRAME_EN (1UL << 2) +#define EMAC_MAC2_DELAYED_CRC (1UL << 3) +#define EMAC_MAC2_CRC_EN (1UL << 4) +#define EMAC_MAC2_PAD_CRC_EN (1UL << 5) +#define EMAC_MAC2_VLAN_PAN_EN (1UL << 6) +#define EMAC_MAC2_AUTO_DET_PAD_EN (1UL << 7) +#define EMAC_MAC2_PURE_PREA_ENF (1UL << 8) +#define EMAC_MAC2_LONG_PRE_ENF (1UL << 9) +#define EMAC_MAC2_NO_BACKOFF (1UL << 12) +#define EMAC_MAC2_BACK_PRESSURE (1UL << 13) +#define EMAC_MAC2_EXCESS_DEFFER (1UL << 14) +/** @} */ + +/** + * @name PHY Support Register bits + * @{ + */ +#define EMAC_SUPP_SPEED (1UL << 8) +/** @} */ + +/** + * @name Test Register bits + * @{ + */ +#define EMAC_TEST_SHORTCUT_PAUSE_QUANTA (1UL << 0) +#define EMAC_TEST_PAUSE (1UL << 1) +#define EMAC_TEST_BACKPRESSURE (1UL << 2) +/** @} */ + +/** + * @name Test Register bits + * @{ + */ +#define EMAC_TEST_SHORTCUT_PAUSE_QUANTA (1UL << 0) +#define EMAC_TEST_PAUSE (1UL << 1) +#define EMAC_TEST_BACKPRESSURE (1UL << 2) +/** @} */ + +/** + * @name MII Mgmt Configuration Register bits + * @{ + */ +#define EMAC_MCFG_SCAN_INCR (1UL << 0) +#define EMAC_MCFG_SUPPRESS_PREAMBLE (1UL << 1) +#define EMAC_MCFG_CLK_DIV_4 (1UL << 2) +#define EMAC_MCFG_CLK_DIV_6 (2UL << 2) +#define EMAC_MCFG_CLK_DIV_8 (3UL << 2) +#define EMAC_MCFG_CLK_DIV_10 (4UL << 2) +#define EMAC_MCFG_CLK_DIV_14 (5UL << 2) +#define EMAC_MCFG_CLK_DIV_20 (6UL << 2) +#define EMAC_MCFG_CLK_DIV_28 (7UL << 2) +#define EMAC_MCFG_CLK_DIV_36 (8UL << 2) +#define EMAC_MCFG_CLK_DIV_40 (9UL << 2) +#define EMAC_MCFG_CLK_DIV_44 (10UL << 2) +#define EMAC_MCFG_CLK_DIV_48 (11UL << 2) +#define EMAC_MCFG_CLK_DIV_52 (12UL << 2) +#define EMAC_MCFG_CLK_DIV_56 (13UL << 2) +#define EMAC_MCFG_CLK_DIV_60 (14UL << 2) +#define EMAC_MCFG_CLK_DIV_64 (15UL << 2) +#define EMAC_MCFG_RESET_MII_MGMT (1UL << 15) +/** @} */ + + +/** + * @name MII Mgmt Command Register bits + * @{ + */ +#define EMAC_MCMD_READ (1UL << 0) +#define EMAC_MCMD_SCAN (1UL << 1) +/** @} */ + +/** + * @name MIND MII Mgmt Indicators Register bits + * @{ + */ +#define EMAC_MIND_BUSY (1UL << 0) +#define EMAC_MIND_SCANNING (1UL << 1) +#define EMAC_MIND_NOT_VALID (1UL << 2) +#define EMAC_MIND_LINK_FAIL (1UL << 3) +/** @} */ + +/** + * @name Command Register bits + * @{ + */ +#define EMAC_COMMAND_RX_ENABLE (1UL << 0) +#define EMAC_COMMAND_TX_ENABLE (1UL << 1) +#define EMAC_COMMAND_REG_RESET (1UL << 3) +#define EMAC_COMMAND_TX_RESET (1UL << 4) +#define EMAC_COMMAND_RX_RESET (1UL << 5) +#define EMAC_COMMAND_PASS_RUN_FRAME (1UL << 6) +#define EMAC_COMMAND_PASS_RX_FILTER (1UL << 7) +#define EMAC_COMMAND_PASS_TX_FLOW_CTRL (1UL << 8) +#define EMAC_COMMAND_RMII (1UL << 9) +#define EMAC_COMMAND_FULL_DUPLEX (1UL << 10) +/** @} */ + +/** + * @name Status Register bits + * @{ + */ +#define EMAC_STATUS_RX (1UL << 0) +#define EMAC_STATUS_TX (1UL << 1) +/** @} */ + +/** + * @name Transmit Status Vector 0 Register bits + * @{ + */ +#define EMAC_TSV0_CRC_ERROR (1UL << 0) +#define EMAC_TSV0_LEN_CHECK_ERROR (1UL << 1) +#define EMAC_TSV0_LEN_OUT_OF_RANGE (1UL << 2) +#define EMAC_TSV0_DONE (1UL << 3) +#define EMAC_TSV0_MULTICAST (1UL << 4) +#define EMAC_TSV0_BROADCAST (1UL << 5) +#define EMAC_TSV0_PACKET_DEFER (1UL << 6) +#define EMAC_TSV0_EXCESSIVE_DEFER (1UL << 7) +#define EMAC_TSV0_EXCESSIVE_COLLISION (1UL << 8) +#define EMAC_TSV0_LATE_COLLISION (1UL << 9) +#define EMAC_TSV0_GIANT (1UL << 10) +#define EMAC_TSV0_UNDERRUN (1UL << 11) +#define EMAC_TSV0_CONTROL_FRAME (1UL << 28) +#define EMAC_TSV0_PAUSE (1UL << 29) +#define EMAC_TSV0_BACKPRESSURE (1UL << 30) +#define EMAC_TSV0_VLAN (1UL << 31) +/** @} */ + +/** + * @name Receive Status Vector Register bits + * @{ + */ +#define EMAC_RSV_PACKET_PREV_IGN (1UL << 16) +#define EMAC_RSV_RXDV_EVENT (1UL << 17) +#define EMAC_RSV_CARRIER_EVENT (1UL << 18) +#define EMAC_RSV_RECEIVE_CODE (1UL << 19) +#define EMAC_RSV_CRC_ERROR (1UL << 20) +#define EMAC_RSV_LEN_CHECK_ERROR (1UL << 21) +#define EMAC_RSV_LEN_OUT_OF_RANGE (1UL << 22) +#define EMAC_RSV_RECEIVE_OK (1UL << 23) +#define EMAC_RSV_MULTICAST (1UL << 24) +#define EMAC_RSV_BROADCAST (1UL << 25) +#define EMAC_RSV_DRIBBLE_NIBBLE (1UL << 26) +#define EMAC_RSV_CTRL_FRAME (1UL << 27) +#define EMAC_RSV_PAUSE (1UL << 28) +#define EMAC_RSV_UNSUPPORTED_OPCODE (1UL << 29) +#define EMAC_RSV_VLAN (1UL << 30) +/** @} */ + +/** + * @name Receive Filter Control Register bits + * @{ + */ +#define EMAC_RXFILCTRL_UNICAST_EN (1UL << 0) +#define EMAC_RXFILCTRL_BROADCAST_EN (1UL << 1) +#define EMAC_RXFILCTRL_MULTICAST_EN (1UL << 2) +#define EMAC_RXFILCTRL_UNICAST_HASH_EN (1UL << 3) +#define EMAC_RXFILCTRL_MULTICAST_HASH_EN (1UL << 4) +#define EMAC_RXFILCTRL_PERFECT_EN (1UL << 5) +#define EMAC_RXFILCTRL_MAGIC_PACKET_EN (1UL << 12) +#define EMAC_RXFILCTRL_RX_FILTER_EN (1UL << 13) +/** @} */ + +/** + * @name Receive Filter WoL Status bits + * @{ + */ +#define EMAC_RXFILWOLSTAT_UNICAST (1UL << 0) +#define EMAC_RXFILWOLSTAT_BROADCAST (1UL << 1) +#define EMAC_RXFILWOLSTAT_MULTICAST (1UL << 2) +#define EMAC_RXFILWOLSTAT_UNICAST_HASH (1UL << 3) +#define EMAC_RXFILWOLSTAT_MULTICAST_HASH (1UL << 4) +#define EMAC_RXFILWOLSTAT_PERFECT (1UL << 5) +#define EMAC_RXFILWOLSTAT_RX_FILTER (1UL << 7) +#define EMAC_RXFILWOLSTAT_MAGIC_PACKET (1UL << 8) +/** @} */ + +/** + * @name Receive Filter WoL Clear bits + * @{ + */ +#define EMAC_RXFILWOLCLR_UNICAST (1UL << 0) +#define EMAC_RXFILWOLCLR_BROADCAST (1UL << 1) +#define EMAC_RXFILWOLCLR_MULTICAST (1UL << 2) +#define EMAC_RXFILWOLCLR_UNICAST_HASH (1UL << 3) +#define EMAC_RXFILWOLCLR_MULTICAST_HASH (1UL << 4) +#define EMAC_RXFILWOLCLR_PERFECT (1UL << 5) +#define EMAC_RXFILWOLCLR_RX_FILTER (1UL << 7) +#define EMAC_RXFILWOLCLR_MAGIC_PACKET (1UL << 8) +/** @} */ + +/** + * @name Interrupt Status Register bits + * @{ + */ +#define EMAC_INTSTAT_RX_OVERRUN (1UL << 0) +#define EMAC_INTSTAT_RX_ERROR (1UL << 1) +#define EMAC_INTSTAT_RX_FINISHED (1UL << 2) +#define EMAC_INTSTAT_RX_DONE (1UL << 3) +#define EMAC_INTSTAT_TX_UNDERRUN (1UL << 4) +#define EMAC_INTSTAT_TX_ERROR (1UL << 5) +#define EMAC_INTSTAT_TX_FINISHED (1UL << 6) +#define EMAC_INTSTAT_TX_DONE (1UL << 7) +#define EMAC_INTSTAT_SOFT (1UL << 12) +#define EMAC_INTSTAT_WAKEUP (1UL << 13) +/** @} */ + +/** + * @name Interrupt Enable Register bits + * @{ + */ +#define EMAC_INTEN_RX_OVERRUN (1UL << 0) +#define EMAC_INTEN_RX_ERROR (1UL << 1) +#define EMAC_INTEN_RX_FINISHED (1UL << 2) +#define EMAC_INTEN_RX_DONE (1UL << 3) +#define EMAC_INTEN_TX_UNDERRUN (1UL << 4) +#define EMAC_INTEN_TX_ERROR (1UL << 5) +#define EMAC_INTEN_TX_FINISHED (1UL << 6) +#define EMAC_INTEN_TX_DONE (1UL << 7) +#define EMAC_INTEN_SOFT (1UL << 12) +#define EMAC_INTEN_WAKEUP (1UL << 13) +/** @} */ + +/** + * @name Interrupt Clear Register bits + * @{ + */ +#define EMAC_INTCLR_RX_OVERRUN (1UL << 0) +#define EMAC_INTCLR_RX_ERROR (1UL << 1) +#define EMAC_INTCLR_RX_FINISHED (1UL << 2) +#define EMAC_INTCLR_RX_DONE (1UL << 3) +#define EMAC_INTCLR_TX_UNDERRUN (1UL << 4) +#define EMAC_INTCLR_TX_ERROR (1UL << 5) +#define EMAC_INTCLR_TX_FINISHED (1UL << 6) +#define EMAC_INTCLR_TX_DONE (1UL << 7) +#define EMAC_INTCLR_SOFT (1UL << 12) +#define EMAC_INTCLR_WAKEUP (1UL << 13) +/** @} */ + +/** + * @name Interrupt Set Register bits + * @{ + */ +#define EMAC_INTSET_RX_OVERRUN (1UL << 0) +#define EMAC_INTSET_RX_ERROR (1UL << 1) +#define EMAC_INTSET_RX_FINISHED (1UL << 2) +#define EMAC_INTSET_RX_DONE (1UL << 3) +#define EMAC_INTSET_TX_UNDERRUN (1UL << 4) +#define EMAC_INTSET_TX_ERROR (1UL << 5) +#define EMAC_INTSET_TX_FINISHED (1UL << 6) +#define EMAC_INTSET_TX_DONE (1UL << 7) +#define EMAC_INTSET_SOFT (1UL << 12) +#define EMAC_INTSET_WAKEUP (1UL << 13) +/** @} */ + +/** + * @name Power-Down Register bits + * @{ + */ +#define EMAC_PWRDOWN_MAC_AHB (1UL << 31) +/** @} */ + +/** + * @name Receive Descriptor Control bits + * @{ + */ +#define EMAC_RXSTATUS_CTRL_SIZE_MASK 0x000007FF +#define EMAC_RXSTATUS_CTRL_LOCK (1UL << 11) +#define EMAC_RXSTATUS_CTRL_READY (1UL << 12) +#define EMAC_RXSTATUS_RELEASE (1UL << 12) +#define EMAC_RXSTATUS_CTRL_INT (1UL << 31) +/** @} */ + +/** + * @name Receive Descriptor Status bits + * @{ + */ +#define EMAC_RXSTATUS_INFO_SIZE_MASK 0x000007FF +#define EMAC_RXSTATUS_INFO_CTRL_FRAME (1UL << 18) +#define EMAC_RXSTATUS_INFO_VLAN (1UL << 19) +#define EMAC_RXSTATUS_INFO_FAIL_FILTER (1UL << 20) +#define EMAC_RXSTATUS_INFO_MULTICAST (1UL << 21) +#define EMAC_RXSTATUS_INFO_BROADCAST (1UL << 22) +#define EMAC_RXSTATUS_INFO_CRC_ERROR (1UL << 23) +#define EMAC_RXSTATUS_INFO_SYMBOL_ERROR (1UL << 24) +#define EMAC_RXSTATUS_INFO_LENGTH_ERROR (1UL << 25) +#define EMAC_RXSTATUS_INFO_RANGE_ERROR (1UL << 26) +#define EMAC_RXSTATUS_INFO_ALLIG_ERROR (1UL << 27) +#define EMAC_RXSTATUS_INFO_OVERRUN (1UL << 28) +#define EMAC_RXSTATUS_INFO_NO_DESCRIPTOR (1UL << 29) +#define EMAC_RXSTATUS_INFO_LAST_FLAG (1UL << 30) +#define EMAC_RXSTATUS_INFO_ERROR (1UL << 31) +/** @} */ + +/** + * @name Transmit Descriptor Control bits + * @{ + */ +#define EMAC_TXSTATUS_CTRL_SIZE_MASK 0x000007FF +#define EMAC_TXSTATUS_CTRL_LOCK (1UL << 11) +#define EMAC_TXSTATUS_CTRL_OVERRIDE (1UL << 26) +#define EMAC_TXSTATUS_CTRL_HUGE (1UL << 27) +#define EMAC_TXSTATUS_CTRL_PAD (1UL << 28) +#define EMAC_TXSTATUS_CTRL_CRC (1UL << 29) +#define EMAC_TXSTATUS_CTRL_LAST (1UL << 30) +#define EMAC_TXSTATUS_CTRL_INT (1UL << 31) +/** @} */ + +/** + * @name Transmit Descriptor Status bits + * @{ + */ +#define EMAC_RXSTATUS_INFO_COL_COUNT_MASK (0x0FUL << 21) +#define EMAC_RXSTATUS_INFO_DEFER (1UL << 25) +#define EMAC_RXSTATUS_INFO_EXC_DEFER (1UL << 26) +#define EMAC_RXSTATUS_INFO_EXC_COL (1UL << 27) +#define EMAC_RXSTATUS_INFO_LATE_COL (1UL << 28) +#define EMAC_RXSTATUS_INFO_UNDERRUN (1UL << 29) +#define EMAC_RXSTATUS_INFO_NO_DESC (1UL << 30) +#define EMAC_RXSTATUS_INFO_ERROR (1UL << 31) +/** @} */ + +/** + * @brief Collision Window / Retry register default value + */ +#define LPC17XX_MAC_CLRT_DEF 0x0000370F + +/** + * @brief Non Back-to-Back Inter-Packet-Gap register default value + */ +#define LPC17XX_MAC_IPGR_DEF 0x00000015 + +/** + * @brief Back-to-Back Inter-Packet-Gap register default value + */ +#define LPC17XX_MAC_IPGT_FULL_DUPLEX_DEF 0x00000015 +#define LPC17XX_MAC_IPGT_HALF_DUPLEX_DEF 0x00000012 + +/** @} */ +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Number of available transmit buffers. + */ +#if !defined(LPC17xx_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) +#define LPC17xx_MAC_TRANSMIT_BUFFERS 2 +#endif + +/** + * @brief Number of available receive buffers. + */ +#if !defined(LPC17xx_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) +#define LPC17xx_MAC_RECEIVE_BUFFERS 4 +#endif + +/** + * @brief Maximum supported frame size. + */ +#if !defined(LPC17xx_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define LPC17xx_MAC_BUFFERS_SIZE 1522 +#endif + +/** + * @brief PHY detection timeout. + * @details Timeout, in milliseconds, for PHY address detection, if a PHY + * is not detected within the timeout then the driver halts during + * initialization. This setting applies only if the PHY address is + * not explicitly set in the board header file using + * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a + * single search path is performed. + */ +#if !defined(LPC17xx_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) +#define LPC17xx_MAC_PHY_TIMEOUT 100 +#endif + +/** + * @brief Change the PHY power state inside the driver. + */ +#if !defined(LPC17xx_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__) +#define LPC17xx_MAC_ETH1_CHANGE_PHY_STATE TRUE +#endif + +/** + * @brief ETHD1 interrupt priority level setting. + */ +#if !defined(LPC17xx_MAC_ETH_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC17xx_MAC_ETH_IRQ_PRIORITY 13 +#endif + +/** + * @brief MAC number of ticks of delay after reset. + */ +#if !defined(LPC17XX_MAC_RESET_DELAY) || defined(__DOXYGEN__) +#define LPC17XX_MAC_RESET_DELAY 100 +#endif + +/** + * @brief MAC maximum frame length. + */ +#if !defined(LPC17XX_MAC_MAX_FLEN) || defined(__DOXYGEN__) +#define LPC17XX_MAC_MAX_FLEN 1536 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC17xx_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS +#error "LPC17xx_MAC_PHY_TIMEOUT requires the realtime counter service" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an LPC17xx Ethernet receive descriptor. + */ +typedef struct { + volatile uint32_t packet; + volatile uint32_t control; +} lpc17xx_eth_rx_descriptor_t; + +/** + * @brief Type of an LPC17xx Ethernet transmit descriptor. + */ +typedef struct { + volatile uint32_t packet; + volatile uint32_t control; +} lpc17xx_eth_tx_descriptor_t; + +/** + * @brief Type of an LPC17xx Ethernet receive status. + */ +typedef struct { + volatile uint32_t info; + volatile uint32_t hashcrc; +} lpc17xx_eth_rx_status_t; + +/** + * @brief Type of an LPC17xx Ethernet transmit status. + */ +typedef volatile uint32_t lpc17xx_eth_tx_status_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Link status flag. + */ + bool_t link_up; + /** + * @brief PHY address (pre shifted). + */ + uint32_t phyaddr; + /** + * @brief Software receive descriptor number. + */ + uint32_t rxsoftindex; + /** + * @brief Software transmit descriptor number. + */ + uint32_t txsoftindex; + +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct { + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Physical descriptor number. + */ + uint32_t txdescn; +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct { + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Physical descriptor number. + */ + uint32_t rxdescn; +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern MACDriver ETHD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool_t mac_lld_poll_link_status(MACDriver *macp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); + + uint32_t mii_read(MACDriver *macp, uint32_t reg); + void mii_write(MACDriver *macp, uint32_t reg, uint32_t value); + void mii_find_phy(MACDriver *macp); +#if MAC_USE_ZERO_COPY + uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep); + const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep); +#endif /* MAC_USE_ZERO_COPY */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC17xx/platform.mk b/os/hal/platforms/LPC17xx/platform.mk index 1cc18db5b..9e5f855de 100644 --- a/os/hal/platforms/LPC17xx/platform.mk +++ b/os/hal/platforms/LPC17xx/platform.mk @@ -8,7 +8,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC17xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/LPC17xx/rtc_lld.c \ ${CHIBIOS}/os/hal/platforms/LPC17xx/i2c_lld.c \ ${CHIBIOS}/os/hal/platforms/LPC17xx/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC17xx/dac_lld.c + ${CHIBIOS}/os/hal/platforms/LPC17xx/dac_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC17xx/mac_lld.c # Required include directories diff --git a/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1766.ld b/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1766.ld index 2a12d97e3..594fd40b2 100644 --- a/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1766.ld +++ b/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1766.ld @@ -104,6 +104,15 @@ SECTIONS _etext = .; _textdata = _etext; + .eth_ram (NOLOAD) : + { + . = ALIGN(4); + PROVIDE(_eth_ram_start = .); + *(.eth_ram) + . = ALIGN(4); + PROVIDE(_eth_ram_end = .); + } > ramahb + .stacks : { . = ALIGN(8); diff --git a/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1769.ld b/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1769.ld index dc5c1feb8..cd195baba 100644 --- a/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1769.ld +++ b/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1769.ld @@ -19,7 +19,7 @@ */ /* - * LPC1766 memory setup. + * LPC1769 memory setup. */ __main_stack_size__ = 0x0200; __process_stack_size__ = 0x0200; @@ -103,6 +103,15 @@ SECTIONS _etext = .; _textdata = _etext; + + .eth_ram (NOLOAD) : + { + . = ALIGN(4); + PROVIDE(_eth_ram_start = .); + *(.eth_ram) + . = ALIGN(4); + PROVIDE(_eth_ram_end = .); + } > ramahb .stacks : { |