diff options
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.c | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.h | 2 |
3 files changed, 7 insertions, 3 deletions
diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c index db85041e4..8dadd1193 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c @@ -726,7 +726,7 @@ void sd_lld_init(void) { #endif
#if STM32_SERIAL_USE_LPUART1
- sdObjectInit(&LPSD1, NULL, notifylp1);
+ sdObjectInit(&LPSD1);
iqObjectInit(&LPSD1.iqueue, sd_in_buflp1, sizeof sd_in_buflp1, NULL, &LPSD1);
oqObjectInit(&LPSD1.oqueue, sd_out_buflp1, sizeof sd_out_buflp1, notifylp1, &LPSD1);
LPSD1.usart = LPUART1;
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index bb7ccc69d..f02d2a3ba 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -156,7 +156,11 @@ void stm32_clock_init(void) { #if !STM32_NO_INIT
/* PWR clock enable.*/
- RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
+#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN)
+ RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
+#else
+ RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
+#endif
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fall back clock when PLL the fails.
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index 476c288be..d78b157f2 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -72,7 +72,7 @@ * @{
*/
#define STM32_HSI16CLK 16000000 /**< High speed internal clock. */
-#define STM32_LSICLK 38000 /**< Low speed internal clock. */
+#define STM32_LSICLK 32000 /**< Low speed internal clock. */
/** @} */
/**
|