diff options
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/STM32F2xx/adc_lld.c | 6 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/adc_lld.c | 6 |
2 files changed, 8 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F2xx/adc_lld.c b/os/hal/platforms/STM32F2xx/adc_lld.c index fd91ba76a..6d889d4c5 100644 --- a/os/hal/platforms/STM32F2xx/adc_lld.c +++ b/os/hal/platforms/STM32F2xx/adc_lld.c @@ -174,8 +174,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { */
void adc_lld_init(void) {
- ADC->CCR = STM32_ADC_ADCPRE;
-
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
@@ -270,6 +268,10 @@ void adc_lld_start(ADCDriver *adcp) { }
#endif /* STM32_ADC_USE_ADC3 */
+ /* This is a common register but apparently it requires that at least one
+ of the ADCs is clocked in order to allow writing, see bug 3575297.*/
+ ADC->CCR = STM32_ADC_ADCPRE << 16;
+
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR1 = 0;
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index bf0788dea..9f447f9a6 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -174,8 +174,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { */
void adc_lld_init(void) {
- ADC->CCR = STM32_ADC_ADCPRE;
-
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
@@ -270,6 +268,10 @@ void adc_lld_start(ADCDriver *adcp) { }
#endif /* STM32_ADC_USE_ADC3 */
+ /* This is a common register but apparently it requires that at least one
+ of the ADCs is clocked in order to allow writing, see bug 3575297.*/
+ ADC->CCR = STM32_ADC_ADCPRE << 16;
+
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR1 = 0;
|