2 files changed, 33 insertions, 1 deletions
diff --git a/os/hal/ports/STM32/STM32F3xx/adc_lld.c b/os/hal/ports/STM32/STM32F3xx/adc_lld.c
index f19765b96..35f79b20a 100644
--- a/os/hal/ports/STM32/STM32F3xx/adc_lld.c
+++ b/os/hal/ports/STM32/STM32F3xx/adc_lld.c
@@ -93,7 +93,7 @@ static void adc_lld_vreg_on(ADCDriver *adcp) {
 #if STM32_ADC_DUAL_MODE
   adcp->adcs->CR = ADC_CR_ADVREGEN_0;
 #endif
-  osalSysPolledDelayX(US2RTC(STM32_HCLK, 10));
+  osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10));
 }
 
 /**
@@ -326,7 +326,11 @@ void adc_lld_init(void) {
 #if STM32_ADC_USE_ADC1
   /* Driver initialization.*/
   adcObjectInit(&ADCD1);
+#if defined(ADC1_2_COMMON)
   ADCD1.adcc = ADC1_2_COMMON;
+#else
+  ADCD1.adcc = ADC1_COMMON;
+#endif
   ADCD1.adcm = ADC1;
 #if STM32_ADC_DUAL_MODE
   ADCD1.adcs = ADC2;
@@ -343,7 +347,11 @@ void adc_lld_init(void) {
 #if STM32_ADC_USE_ADC3
   /* Driver initialization.*/
   adcObjectInit(&ADCD3);
+#if defined(ADC3_4_COMMON)
   ADCD3.adcc = ADC3_4_COMMON;
+#else
+  ADCD3.adcc = ADC3_COMMON;
+#endif
   ADCD3.adcm = ADC3;
 #if STM32_ADC_DUAL_MODE
   ADCD3.adcs = ADC4;
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
index 19aa6850a..253d4c115 100644
--- a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
@@ -171,7 +171,11 @@
  *
  * @api
  */
+#if defined(RCC_AHBENR_ADC12EN) || defined(__DOXYGEN__)
 #define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
+#else
+#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC1EN, lp)
+#endif
 
 /**
  * @brief   Disables the ADC1/ADC2 peripheral clock.
@@ -180,14 +184,22 @@
  *
  * @api
  */
+#if defined(RCC_AHBENR_ADC12EN) || defined(__DOXYGEN__)
 #define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
+#else
+#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC1EN, lp)
+#endif
 
 /**
  * @brief   Resets the ADC1/ADC2 peripheral.
  *
  * @api
  */
+#if defined(RCC_AHBRSTR_ADC12RST) || defined(__DOXYGEN__)
 #define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
+#else
+#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC1RST)
+#endif
 
 /**
  * @brief   Enables the ADC3/ADC4 peripheral clock.
@@ -196,7 +208,11 @@
  *
  * @api
  */
+#if defined(RCC_AHBENR_ADC34EN) || defined(__DOXYGEN__)
 #define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
+#else
+#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC3EN, lp)
+#endif
 
 /**
  * @brief   Disables the ADC3/ADC4 peripheral clock.
@@ -205,14 +221,22 @@
  *
  * @api
  */
+#if defined(RCC_AHBENR_ADC34EN) || defined(__DOXYGEN__)
 #define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
+#else
+#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC3EN, lp)
+#endif
 
 /**
  * @brief   Resets the ADC3/ADC4 peripheral.
  *
  * @api
  */
+#if defined(RCC_AHBRSTR_ADC34RST) || defined(__DOXYGEN__)
 #define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
+#else
+#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC3RST)
+#endif
 /** @} */
 
 /**