diff options
Diffstat (limited to 'os/ports')
36 files changed, 400 insertions, 133 deletions
diff --git a/os/ports/GCC/ARM/chcore.h b/os/ports/GCC/ARM/chcore.h index c2d2892cd..f23048e4c 100644 --- a/os/ports/GCC/ARM/chcore.h +++ b/os/ports/GCC/ARM/chcore.h @@ -249,7 +249,7 @@ struct context { #define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
sizeof(struct intctx) + \
sizeof(struct extctx) + \
- (n) + (PORT_INT_REQUIRED_STACK))
+ (n) + (PORT_INT_REQUIRED_STACK))
/**
* @brief Static working area allocation.
diff --git a/os/ports/GCC/ARM/chcoreasm.s b/os/ports/GCC/ARM/chcoreasm.s index 41bd29a90..9b65c14b0 100644 --- a/os/ports/GCC/ARM/chcoreasm.s +++ b/os/ports/GCC/ARM/chcoreasm.s @@ -28,6 +28,9 @@ #include "chconf.h"
+#define FALSE 0
+#define TRUE 1
+
#if !defined(__DOXYGEN__)
.set MODE_USR, 0x10
@@ -143,12 +146,12 @@ _port_switch_arm: * | R0 | |
* | PC | | (user code return address)
* | PSR_USR | -+ (user code status)
- * | .... | <- mk_DoRescheduleI() stack frame, optimize it for space
+ * | .... | <- chSchDoReschedule() stack frame, optimize it for space
* | LR | -+ (system code return address)
* | R11 | |
* | R10 | |
* | R9 | |
- * | R8 | | Internal context: mk_SwitchI() frame
+ * | R8 | | Internal context: chSysSwitch() frame
* | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE)
* | R6 | |
* | R5 | |
@@ -161,7 +164,7 @@ _port_switch_arm: .thumb_func
.globl _port_irq_common
_port_irq_common:
- bl chSchIsRescRequiredExI
+ bl chSchIsPreemptionRequired
mov lr, pc
bx lr
.code 32
@@ -169,7 +172,7 @@ _port_irq_common: .code 32
.globl _port_irq_common
_port_irq_common:
- bl chSchIsRescRequiredExI
+ bl chSchIsPreemptionRequired
#endif /* !THUMB_NO_INTERWORKING */
cmp r0, #0 // Simply returns if a
ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not
@@ -190,12 +193,24 @@ _port_irq_common: add r0, pc, #1
bx r0
.code 16
- bl chSchDoRescheduleI
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
mov lr, pc
bx lr
.code 32
#else /* !THUMB_NO_INTERWORKING */
- bl chSchDoRescheduleI
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
#endif /* !THUMB_NO_INTERWORKING */
// Re-establish the IRQ conditions again.
@@ -210,12 +225,18 @@ _port_irq_common: /*
* Threads trampoline code.
- * NOTE: The threads always start in ARM mode then switch to the thread-function mode.
+ * NOTE: The threads always start in ARM mode and then switches to the
+ * thread-function mode.
*/
.balign 16
.code 32
.globl _port_thread_start
_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ mov r0, #0
+ ldr r1, =dbg_lock_cnt
+ str r0, [r1]
+#endif
msr CPSR_c, #MODE_SYS
#ifndef THUMB_NO_INTERWORKING
mov r0, r5
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld index 7e6b8ee56..2dd7ca7a2 100644 --- a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld +++ b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld @@ -26,8 +26,8 @@ __process_stack_size__ = 0x0400; MEMORY
{
- flash : org = 0x08000000, len = 1m
- ram : org = 0x20000000, len = 96k
+ flash : org = 0x08000000, len = 512k
+ ram : org = 0x20000000, len = 64k
}
__ram_start__ = ORIGIN(ram);
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld new file mode 100644 index 000000000..a3577b314 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld @@ -0,0 +1,144 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * ST32F103xG memory setup.
+ */
+__main_stack_size__ = 0x0400;
+__process_stack_size__ = 0x0400;
+
+MEMORY
+{
+ flash : org = 0x08000000, len = 1m
+ ram : org = 0x20000000, len = 96k
+}
+
+__ram_start__ = ORIGIN(ram);
+__ram_size__ = LENGTH(ram);
+__ram_end__ = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+ . = 0;
+ _text = .;
+
+ startup : ALIGN(16) SUBALIGN(16)
+ {
+ KEEP(*(vectors))
+ } > flash
+
+ constructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__fini_array_start = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .text : ALIGN(16) SUBALIGN(16)
+ {
+ *(.text.startup.*)
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ .ARM.exidx : {
+ PROVIDE(__exidx_start = .);
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ PROVIDE(__exidx_end = .);
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ . = ALIGN(4);
+ _etext = .;
+ _textdata = _etext;
+
+ .stacks :
+ {
+ . = ALIGN(8);
+ __main_stack_base__ = .;
+ . += __main_stack_size__;
+ . = ALIGN(8);
+ __main_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .data :
+ {
+ PROVIDE(_data = .);
+ *(.data)
+ . = ALIGN(4);
+ *(.data.*)
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ PROVIDE(_edata = .);
+ } > ram AT > flash
+
+ .bss :
+ {
+ PROVIDE(_bss_start = .);
+ *(.bss)
+ . = ALIGN(4);
+ *(.bss.*)
+ . = ALIGN(4);
+ *(COMMON)
+ . = ALIGN(4);
+ PROVIDE(_bss_end = .);
+ } > ram
+}
+
+PROVIDE(end = .);
+_end = .;
+
+__heap_base__ = _end;
+__heap_end__ = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c index d47eeb72e..43faa0ed0 100644 --- a/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c +++ b/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c @@ -25,6 +25,18 @@ * @defgroup ARMCMx_STM32F1xx_VECTORS STM32F1xx Interrupt Vectors
* @ingroup ARMCMx_SPECIFIC
* @details Interrupt vectors for the STM32F1xx family.
+ * One of the following macros must be defined on the
+ * compiler command line or in a file named <tt>board.h</tt>:
+ * - @p STM32F10X_LD
+ * - @p STM32F10X_LD_VL
+ * - @p STM32F10X_MD
+ * - @p STM32F10X_MD_VL
+ * - @p STM32F10X_HD
+ * - @p STM32F10X_XL
+ * - @p STM32F10X_CL
+ * .
+ * This is required in order to include a vectors table with
+ * the correct length for the specified STM32 model.
* @{
*/
diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h index 5d47a6699..944094925 100644 --- a/os/ports/GCC/ARMCMx/chcore.h +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -116,7 +116,7 @@ * separate interrupt stack and the stack space between @p intctx and
* @p extctx is known to be zero.
* @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
+ * @p chSchDoReschedule() can have a stack frame, expecially with
* compiler optimizations disabled.
*/
#ifndef PORT_INT_REQUIRED_STACK
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c index 2183a9ded..453bc2c65 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.c +++ b/os/ports/GCC/ARMCMx/chcore_v6m.c @@ -90,8 +90,8 @@ __attribute__((naked)) #endif
void _port_switch_from_isr(void) {
- if (chSchIsRescRequiredExI())
- chSchDoRescheduleI();
+ if (chSchIsPreemptionRequired())
+ chSchDoReschedule();
#if CORTEX_ALTERNATE_SWITCH
SCB_ICSR = ICSR_PENDSVSET;
port_unlock();
@@ -176,7 +176,7 @@ void _port_irq_epilogue(regarm_t lr) { */
void _port_thread_start(void) {
- port_unlock();
+ chSysUnlock();
asm volatile ("mov r0, r5 \n\t"
"blx r4 \n\t"
"bl chThdExit");
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c index 39711ce79..e8a1ff16e 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.c +++ b/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -141,8 +141,10 @@ __attribute__((naked)) #endif
void _port_switch_from_isr(void) {
- if (chSchIsRescRequiredExI())
- chSchDoRescheduleI();
+ dbg_check_lock();
+ if (chSchIsPreemptionRequired())
+ chSchDoReschedule();
+ dbg_check_unlock();
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
asm volatile ("svc #0");
#else /* CORTEX_SIMPLIFIED_PRIORITY */
@@ -183,7 +185,7 @@ void _port_switch(Thread *ntp, Thread *otp) { */
void _port_thread_start(void) {
- port_unlock();
+ chSysUnlock();
asm volatile ("mov r0, r5 \n\t"
"blx r4 \n\t"
"bl chThdExit");
diff --git a/os/ports/GCC/ARMCMx/crt0.c b/os/ports/GCC/ARMCMx/crt0.c index 6e4524fa9..e2cb2b3de 100644 --- a/os/ports/GCC/ARMCMx/crt0.c +++ b/os/ports/GCC/ARMCMx/crt0.c @@ -33,6 +33,15 @@ typedef void (*funcp_t)(void);
typedef funcp_t * funcpp_t;
+#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
+
+/*===========================================================================*/
+/**
+ * @name Startup settings
+ * @{
+ */
+/*===========================================================================*/
+
/**
* @brief Control special register initialization value.
* @details The system is setup to run in privileged mode using the PSP
@@ -84,7 +93,13 @@ typedef funcp_t * funcpp_t; #define CRT0_CALL_DESTRUCTORS TRUE
#endif
-#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Symbols from the scatter file
+ */
+/*===========================================================================*/
/**
* @brief Main stack lower boundary.
@@ -94,6 +109,7 @@ typedef funcp_t * funcpp_t; extern uint32_t __main_stack_base__;
/**
+ *
* @brief Main stack initial position.
* @details This symbol must be exported by the linker script and represents
* the main stack initial position.
@@ -168,6 +184,8 @@ extern funcp_t __fini_array_start; */
extern funcp_t __fini_array_end;
+/** @} */
+
/**
* @brief Application @p main() function.
*/
diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox index 8f5efc9aa..13ab36d8a 100644 --- a/os/ports/GCC/ARMCMx/port.dox +++ b/os/ports/GCC/ARMCMx/port.dox @@ -126,19 +126,6 @@ * stack where all the interrupts and exceptions are processed.
* - The threads are started in thread-privileged mode.
* - Interrupt nesting and the other advanced core/NVIC features are supported.
- * - When using an STM32 one of the following macros must be defined on the
- * compiler command line or in a file named <tt>board.h</tt>:
- * - @p STM32F10X_LD
- * - @p STM32F10X_LD_VL
- * - @p STM32F10X_MD
- * - @p STM32F10X_MD_VL
- * - @p STM32F10X_HD
- * - @p STM32F10X_XL
- * - @p STM32F10X_CL
- * .
- * This is required in order to include a vectors table with the correct
- * length for the STM32 model, see the file
- * <tt>./os/ports/GCC/ARMCMx/STM32/vectors.c</tt>.
* - The Cortex-Mx port is perfectly generic, support for more devices can be
* easily added by adding a subdirectory under <tt>./os/ports/GCC/ARMCMx</tt>
* and giving it the name of the new device, then copy the files from another
@@ -211,25 +198,27 @@ * @section ARMCMx_STARTUP_1 Startup Process
* The startup process, as implemented, is the following:
* -# Interrupts are masked globally.
- * -# The two stacks are initialized by assigning them the sizes defined in the
- * linker script (usually named @p ch.ld). Stack areas are allocated from
- * the highest RAM location downward.
+ * -# The two stacks are initialized by assigning them the sizes defined in
+ * the linker script (also known as scatter file).
* -# The CPU state is switched to Privileged and the PSP stack is used.
* -# An early initialization routine @p __early_init() is invoked, if the
* symbol is not defined then an empty default routine is executed
* (weak symbol).
* -# DATA and BSS segments are initialized.
+ * -# Constructors are invoked.
* -# The @p main() function is invoked with no parameters.
- * -# Should the @p main() function return a branch is performed to the weak
- * symbol _main_exit_handler. The default code is an endless empty loop.
+ * -# Destructors are invoked.
+ * -# A branch is performed to the weak symbol @p _default_exit(). The
+ * default code is an endless empty loop.
* .
* @section ARMCMx_STARTUP_2 Expected linker symbols
* The startup code starts at the symbol @p ResetHandler and expects the
* following symbols to be defined in the linker script:
* - @p __ram_end__ End of RAM.
- * - @p __main_stack_size__ Exception stack size.
- * - @p __process_stack_size__ Process stack size. This is the stack area used
- * by the @p main() function.
+ * - @p __main_stack_base__ Main stack lower boundary.
+ * - @p __main_stack_end__ Main stack initial position.
+ * - @p __process_stack_base__ Process stack lower boundary.
+ * - @p __process_stack_end__ Process stack initial position.
* - @p _textdata Address of the data segment source read only data.
* - @p _data Start of the data segment.
* - @p _edata End of the data segment end location.
diff --git a/os/ports/GCC/AVR/chcore.c b/os/ports/GCC/AVR/chcore.c index 7cb0dda07..58663cd9c 100644 --- a/os/ports/GCC/AVR/chcore.c +++ b/os/ports/GCC/AVR/chcore.c @@ -123,7 +123,7 @@ void port_halt(void) { */
void _port_thread_start(void) {
- asm volatile ("sei");
+ chSysUnlock();
asm volatile ("movw r24, r4");
asm volatile ("movw r30, r2");
asm volatile ("icall");
diff --git a/os/ports/GCC/AVR/chcore.h b/os/ports/GCC/AVR/chcore.h index 2d33b205d..744502825 100644 --- a/os/ports/GCC/AVR/chcore.h +++ b/os/ports/GCC/AVR/chcore.h @@ -142,15 +142,15 @@ struct context { * @details This code usually setup the context switching frame represented
* by an @p intctx structure.
*/
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.sp = (struct intctx*)((uint8_t *)workspace + wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.sp->r2 = (int)pf; \
- tp->p_ctx.sp->r3 = (int)pf >> 8; \
- tp->p_ctx.sp->r4 = (int)arg; \
- tp->p_ctx.sp->r5 = (int)arg >> 8; \
- tp->p_ctx.sp->pcl = (int)_port_thread_start >> 8; \
- tp->p_ctx.sp->pch = (int)_port_thread_start; \
+#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
+ tp->p_ctx.sp = (struct intctx*)((uint8_t *)workspace + wsize - \
+ sizeof(struct intctx)); \
+ tp->p_ctx.sp->r2 = (int)pf; \
+ tp->p_ctx.sp->r3 = (int)pf >> 8; \
+ tp->p_ctx.sp->r4 = (int)arg; \
+ tp->p_ctx.sp->r5 = (int)arg >> 8; \
+ tp->p_ctx.sp->pcl = (int)_port_thread_start >> 8; \
+ tp->p_ctx.sp->pch = (int)_port_thread_start; \
}
/**
@@ -185,9 +185,9 @@ struct context { /**
* @brief Computes the thread working area global size.
*/
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
- (sizeof(struct intctx) - 1) + \
- (sizeof(struct extctx) - 1) + \
+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
+ (sizeof(struct intctx) - 1) + \
+ (sizeof(struct extctx) - 1) + \
(n) + (PORT_INT_REQUIRED_STACK))
/**
@@ -204,9 +204,9 @@ struct context { * @note This code tricks the compiler to save all the specified registers
* by "touching" them.
*/
-#define PORT_IRQ_PROLOGUE() { \
- asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24", \
- "r25", "r26", "r27", "r30", "r31"); \
+#define PORT_IRQ_PROLOGUE() { \
+ asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24", \
+ "r25", "r26", "r27", "r30", "r31"); \
}
/**
@@ -214,9 +214,11 @@ struct context { * @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_EPILOGUE() { \
- if (chSchIsRescRequiredExI()) \
- chSchDoRescheduleI(); \
+#define PORT_IRQ_EPILOGUE() { \
+ dbg_check_lock(); \
+ if (chSchIsPreemptionRequired()) \
+ chSchDoReschedule(); \
+ dbg_check_unlock(); \
}
/**
diff --git a/os/ports/GCC/MSP430/chcore.c b/os/ports/GCC/MSP430/chcore.c index d9192177d..ef8ae4967 100644 --- a/os/ports/GCC/MSP430/chcore.c +++ b/os/ports/GCC/MSP430/chcore.c @@ -93,8 +93,8 @@ void port_halt(void) { */
void _port_thread_start(void) {
- asm volatile ("eint \n\t" \
- "mov r11, r15 \n\t" \
+ chSysUnlock();
+ asm volatile ("mov r11, r15 \n\t" \
"call r10 \n\t" \
"call #chThdExit");
}
diff --git a/os/ports/GCC/MSP430/chcore.h b/os/ports/GCC/MSP430/chcore.h index 3e3d5b5d1..3fb0f3591 100644 --- a/os/ports/GCC/MSP430/chcore.h +++ b/os/ports/GCC/MSP430/chcore.h @@ -119,13 +119,13 @@ struct context { * @details This code usually setup the context switching frame represented
* by an @p intctx structure.
*/
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.sp->r10 = pf; \
- tp->p_ctx.sp->r11 = arg; \
- tp->p_ctx.sp->pc = _port_thread_start; \
+#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
+ tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace + \
+ wsize - \
+ sizeof(struct intctx)); \
+ tp->p_ctx.sp->r10 = pf; \
+ tp->p_ctx.sp->r11 = arg; \
+ tp->p_ctx.sp->pc = _port_thread_start; \
}
/**
@@ -159,10 +159,10 @@ struct context { /**
* @brief Computes the thread working area global size.
*/
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
- sizeof(struct intctx) + \
- sizeof(struct extctx) + \
- (n) + (PORT_INT_REQUIRED_STACK))
+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
+ sizeof(struct intctx) + \
+ sizeof(struct extctx) + \
+ (n) + (PORT_INT_REQUIRED_STACK))
/**
* @brief Static working area allocation.
@@ -183,9 +183,11 @@ struct context { * @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_EPILOGUE() { \
- if (chSchIsRescRequiredExI()) \
- chSchDoRescheduleI(); \
+#define PORT_IRQ_EPILOGUE() { \
+ dbg_check_lock(); \
+ if (chSchIsPreemptionRequired()) \
+ chSchDoReschedule(); \
+ dbg_check_unlock(); \
}
/**
@@ -220,7 +222,11 @@ struct context { /**
* @brief Kernel-lock action from an interrupt handler.
* @details This function is invoked before invoking I-class APIs from
- * interrupt handlers. The implementation is architecture dependent,
+ * interrupt handlers. The implementation is architecture dependen#define PORT_IRQ_EPILOGUE() { \
+ if (chSchIsPreemptionRequired()) \
+ chSchDoReschedule(); \
+}
+ * t,
* in its simplest form it is void.
* @note This function is empty in this port.
*/
@@ -270,8 +276,8 @@ struct context { */
#if ENABLE_WFI_IDLE != 0
#ifndef port_wait_for_interrupt
-#define port_wait_for_interrupt() { \
- asm volatile ("nop" : : : "memory"); \
+#define port_wait_for_interrupt() { \
+ asm volatile ("nop" : : : "memory"); \
}
#endif
#else
diff --git a/os/ports/GCC/PPC/SPC56x/ivor.s b/os/ports/GCC/PPC/SPC56x/ivor.s index 7f470d26a..f572db1b5 100644 --- a/os/ports/GCC/PPC/SPC56x/ivor.s +++ b/os/ports/GCC/PPC/SPC56x/ivor.s @@ -25,8 +25,13 @@ * @addtogroup PPC_CORE
* @{
*/
-/** @cond never */
+#include "chconf.h"
+
+#define FALSE 0
+#define TRUE 1
+
+#if !defined(__DOXYGEN__)
/*
* INTC registers address.
*/
@@ -71,12 +76,15 @@ IVOR10: lis %r3, 0x0800 /* DIS bit mask. */
mtspr 336, %r3 /* TSR register. */
- /* System tick handler invokation.*/
+ /* System tick handler invocation.*/
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_lock
+#endif
bl chSysTimerHandlerI
- bl chSchIsRescRequiredExI
+ bl chSchIsPreemptionRequired
cmpli cr0, %r3, 0
beq cr0, .ctxrestore
- bl chSchDoRescheduleI
+ bl chSchDoReschedule
b .ctxrestore
/*
@@ -138,13 +146,19 @@ IVOR4: stw %r3, 0(%r3) /* Writing any value should do. */
/* Verifies if a reschedule is required.*/
- bl chSchIsRescRequiredExI
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_lock
+#endif
+ bl chSchIsPreemptionRequired
cmpli cr0, %r3, 0
beq cr0, .ctxrestore
- bl chSchDoRescheduleI
+ bl chSchDoReschedule
/* Context restore.*/
.ctxrestore:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */
lwz %r4, 40(%sp)
lwz %r5, 44(%sp)
@@ -171,5 +185,6 @@ IVOR4: addi %sp, %sp, 80 /* Back to the previous frame. */
rfi
-/** @endcond */
+#endif /* !defined(__DOXYGEN__) */
+
/** @} */
diff --git a/os/ports/GCC/PPC/chcore.c b/os/ports/GCC/PPC/chcore.c index c68d5e07c..7fb5dd578 100644 --- a/os/ports/GCC/PPC/chcore.c +++ b/os/ports/GCC/PPC/chcore.c @@ -81,7 +81,8 @@ void port_switch(Thread *ntp, Thread *otp) { * invoked.
*/
void _port_thread_start(void) {
- asm ("wrteei 1");
+
+ chSysUnlock();
asm ("mr %r3, %r31"); /* Thread parameter. */
asm ("mtctr %r30");
asm ("bctrl"); /* Invoke thread function. */
diff --git a/os/ports/GCC/PPC/chcore.h b/os/ports/GCC/PPC/chcore.h index 6504532ac..01b31bbb7 100644 --- a/os/ports/GCC/PPC/chcore.h +++ b/os/ports/GCC/PPC/chcore.h @@ -221,10 +221,10 @@ struct context { /**
* @brief Computes the thread working area global size.
*/
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
- sizeof(struct intctx) + \
- sizeof(struct extctx) + \
- (n) + (PORT_INT_REQUIRED_STACK))
+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
+ sizeof(struct intctx) + \
+ sizeof(struct extctx) + \
+ (n) + (PORT_INT_REQUIRED_STACK))
/**
* @brief Static working area allocation.
@@ -307,8 +307,8 @@ struct context { */
#if ENABLE_WFI_IDLE != 0
#ifndef port_wait_for_interrupt
-#define port_wait_for_interrupt() { \
- asm volatile ("wait" : : : "memory"); \
+#define port_wait_for_interrupt() { \
+ asm volatile ("wait" : : : "memory"); \
}
#endif
#else
diff --git a/os/ports/GCC/SIMIA32/chcore.h b/os/ports/GCC/SIMIA32/chcore.h index 3d5c62b23..2a9d3d452 100644 --- a/os/ports/GCC/SIMIA32/chcore.h +++ b/os/ports/GCC/SIMIA32/chcore.h @@ -144,7 +144,7 @@ struct context { sizeof(void *) * 4 + \
sizeof(struct intctx) + \
sizeof(struct extctx) + \
- (n) + (PORT_INT_REQUIRED_STACK))
+ (n) + (PORT_INT_REQUIRED_STACK))
/**
* Macro used to allocate a thread working area aligned as both position and
diff --git a/os/ports/IAR/ARMCMx/STM32/cmparams.h b/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h index 3e18146c0..8f9795822 100644 --- a/os/ports/IAR/ARMCMx/STM32/cmparams.h +++ b/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h @@ -19,13 +19,13 @@ */
/**
- * @file IAR/ARMCMx/STM32/cmparams.h
- * @brief ARM Cortex-M3 parameters for the STM32.
+ * @file IAR/ARMCMx/STM32F1xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32F1xx.
*
- * @defgroup IAR_ARMCMx_STM32 STM32 Specific Parameters
+ * @defgroup IAR_ARMCMx_STM32F1xx STM32F1xx Specific Parameters
* @ingroup IAR_ARMCMx_SPECIFIC
* @details This file contains the Cortex-M3 specific parameters for the
- * STM32 platform.
+ * STM32F1xx platform.
* @{
*/
diff --git a/os/ports/IAR/ARMCMx/STM32/vectors.s b/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s index 85c889267..85c889267 100644 --- a/os/ports/IAR/ARMCMx/STM32/vectors.s +++ b/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s diff --git a/os/ports/IAR/ARMCMx/chcore.h b/os/ports/IAR/ARMCMx/chcore.h index 5eff85f51..c3e91cc02 100644 --- a/os/ports/IAR/ARMCMx/chcore.h +++ b/os/ports/IAR/ARMCMx/chcore.h @@ -116,7 +116,7 @@ * separate interrupt stack and the stack space between @p intctx and
* @p extctx is known to be zero.
* @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
+ * @p chSchDoReschedule() can have a stack frame, expecially with
* compiler optimizations disabled.
*/
#ifndef PORT_INT_REQUIRED_STACK
diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h index a25fde1ef..0480451c0 100644 --- a/os/ports/IAR/ARMCMx/chcore_v6m.h +++ b/os/ports/IAR/ARMCMx/chcore_v6m.h @@ -240,7 +240,7 @@ struct intctx { #define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
- if ((void *)(__get_SP() - sizeof(struct intctx)) < (void *)(otp + 1)) \
+ if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \
chDbgPanic("stack overflow"); \
_port_switch(ntp, otp); \
}
diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.h b/os/ports/IAR/ARMCMx/chcore_v7m.h index 059f29711..086a99d39 100644 --- a/os/ports/IAR/ARMCMx/chcore_v7m.h +++ b/os/ports/IAR/ARMCMx/chcore_v7m.h @@ -306,7 +306,7 @@ struct intctx { #define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
- if ((void *)(__get_SP() - sizeof(struct intctx)) < (void *)(otp + 1)) \
+ if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \
chDbgPanic("stack overflow"); \
_port_switch(ntp, otp); \
}
diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s index a05ce3aa1..56e62d16f 100644 --- a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s +++ b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s @@ -37,8 +37,12 @@ SCB_ICSR SET 0xE000ED04 SECTION .text:CODE:NOROOT(2)
EXTERN chThdExit
- EXTERN chSchIsRescRequiredExI
- EXTERN chSchDoRescheduleI
+ EXTERN chSchIsPreemptionRequired
+ EXTERN chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ EXTERN dbg_check_unlock
+ EXTERN dbg_check_lock
+#endif
THUMB
@@ -70,6 +74,9 @@ _port_switch: */
PUBLIC _port_thread_start
_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
cpsie i
mov r0, r5
blx r4
@@ -110,11 +117,17 @@ PendSVVector: */
PUBLIC _port_switch_from_isr
_port_switch_from_isr:
- bl chSchIsRescRequiredExI
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_lock
+#endif
+ bl chSchIsPreemptionRequired
cmp r0, #0
beq noresch
- bl chSchDoRescheduleI
+ bl chSchDoReschedule
noresch:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
ldr r2, =SCB_ICSR
movs r3, #128
#if CORTEX_ALTERNATE_SWITCH
diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v7m.s b/os/ports/IAR/ARMCMx/chcoreasm_v7m.s index 8367fcdb0..4c40babc5 100644 --- a/os/ports/IAR/ARMCMx/chcoreasm_v7m.s +++ b/os/ports/IAR/ARMCMx/chcoreasm_v7m.s @@ -39,8 +39,12 @@ ICSR_PENDSVSET SET 0x10000000 SECTION .text:CODE:NOROOT(2)
EXTERN chThdExit
- EXTERN chSchIsRescRequiredExI
- EXTERN chSchDoRescheduleI
+ EXTERN chSchIsPreemptionRequired
+ EXTERN chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ EXTERN dbg_check_unlock
+ EXTERN dbg_check_lock
+#endif
THUMB
@@ -60,6 +64,9 @@ _port_switch: */
PUBLIC _port_thread_start
_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
#if CORTEX_SIMPLIFIED_PRIORITY
cpsie i
#else
@@ -76,10 +83,16 @@ _port_thread_start: */
PUBLIC _port_switch_from_isr
_port_switch_from_isr:
- bl chSchIsRescRequiredExI
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_lock
+#endif
+ bl chSchIsPreemptionRequired
cbz r0, .L2
- bl chSchDoRescheduleI
+ bl chSchDoReschedule
.L2:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
#if CORTEX_SIMPLIFIED_PRIORITY
mov r3, #LWRD SCB_ICSR
movt r3, #HWRD SCB_ICSR
diff --git a/os/ports/RC/STM8/chcore.c b/os/ports/RC/STM8/chcore.c index d7034e38a..a45f4c27f 100644 --- a/os/ports/RC/STM8/chcore.c +++ b/os/ports/RC/STM8/chcore.c @@ -54,8 +54,8 @@ void _port_switch(Thread *otp) { */
void _port_thread_start(void) {
+ chSysUnlock();
#pragma ASM
- RIM
POPW X
#pragma ENDASM
}
diff --git a/os/ports/RC/STM8/chcore.h b/os/ports/RC/STM8/chcore.h index 07b7fa0b6..c8c2ebb16 100644 --- a/os/ports/RC/STM8/chcore.h +++ b/os/ports/RC/STM8/chcore.h @@ -206,8 +206,10 @@ struct stm8_startctx { * enabled to invoke system APIs.
*/
#define PORT_IRQ_EPILOGUE() { \
- if (chSchIsRescRequiredExI()) \
- chSchDoRescheduleI(); \
+ dbg_check_lock(); \
+ if (chSchIsPreemptionRequired()) \
+ chSchDoReschedule(); \
+ dbg_check_unlock(); \
}
/**
diff --git a/os/ports/RVCT/ARMCMx/STM32/cmparams.h b/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h index 73a3f2357..2bd7715a4 100644 --- a/os/ports/RVCT/ARMCMx/STM32/cmparams.h +++ b/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h @@ -19,13 +19,13 @@ */
/**
- * @file RVCT/ARMCMx/STM32/cmparams.h
- * @brief ARM Cortex-M3 parameters for the STM32.
+ * @file RVCT/ARMCMx/STM32F1xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32F1xx.
*
- * @defgroup RVCT_ARMCMx_STM32 STM32 Specific Parameters
+ * @defgroup RVCT_ARMCMx_STM32F1xx STM32F1xx Specific Parameters
* @ingroup RVCT_ARMCMx_SPECIFIC
* @details This file contains the Cortex-M3 specific parameters for the
- * STM32 platform.
+ * STM32F1xx platform.
* @{
*/
diff --git a/os/ports/RVCT/ARMCMx/STM32/vectors.s b/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s index 330f34bf8..330f34bf8 100644 --- a/os/ports/RVCT/ARMCMx/STM32/vectors.s +++ b/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s diff --git a/os/ports/RVCT/ARMCMx/chcore.h b/os/ports/RVCT/ARMCMx/chcore.h index 42b397e93..7c4e82613 100644 --- a/os/ports/RVCT/ARMCMx/chcore.h +++ b/os/ports/RVCT/ARMCMx/chcore.h @@ -116,7 +116,7 @@ * separate interrupt stack and the stack space between @p intctx and
* @p extctx is known to be zero.
* @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
+ * @p chSchDoReschedule() can have a stack frame, expecially with
* compiler optimizations disabled.
*/
#ifndef PORT_INT_REQUIRED_STACK
@@ -227,6 +227,7 @@ struct intctx { /**
* @brief Platform dependent part of the @p Thread structure.
+
* @details In this port the structure just holds a pointer to the @p intctx
* structure representing the stack pointer at context switch time.
*/
diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h index 7241d462f..bdeec1674 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v6m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h @@ -240,8 +240,8 @@ struct intctx { #define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
- struct intctx *r13 = (struct intctx *)__current_sp(); \
- if ((void *)(r13 - 1) < (void *)(otp + 1)) \
+ uint8_t *r13 = (uint8_t *)__current_sp(); \
+ if ((stkalign_t *)(r13 - sizeof(struct intctx)) < otp->p_stklimit) \
chDbgPanic("stack overflow"); \
_port_switch(ntp, otp); \
}
diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h index fdf855f77..17447476f 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v7m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -314,8 +314,8 @@ struct intctx { #define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
- struct intctx *r13 = (struct intctx *)__current_sp(); \
- if ((void *)(r13 - 1) < (void *)(otp + 1)) \
+ uint8_t *r13 = (uint8_t *)__current_sp(); \
+ if ((stkalign_t *)(r13 - sizeof(struct intctx)) < otp->p_stklimit) \
chDbgPanic("stack overflow"); \
_port_switch(ntp, otp); \
}
diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s index 579680421..83878805e 100644 --- a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s +++ b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s @@ -34,8 +34,12 @@ SCB_ICSR EQU 0xE000ED04 AREA |.text|, CODE, READONLY
IMPORT chThdExit
- IMPORT chSchIsRescRequiredExI
- IMPORT chSchDoRescheduleI
+ IMPORT chSchIsPreemptionRequired
+ IMPORT chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ IMPORT dbg_check_unlock
+ IMPORT dbg_check_lock
+#endif
/*
* Performs a context switch between two threads.
@@ -66,6 +70,9 @@ _port_switch PROC */
EXPORT _port_thread_start
_port_thread_start PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
cpsie i
mov r0, r5
blx r4
@@ -109,11 +116,17 @@ PendSVVector PROC */
EXPORT _port_switch_from_isr
_port_switch_from_isr PROC
- bl chSchIsRescRequiredExI
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_lock
+#endif
+ bl chSchIsPreemptionRequired
cmp r0, #0
- beq noresch
- bl chSchDoRescheduleI
-noresch
+ beq noreschedule
+ bl chSchDoReschedule
+noreschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
ldr r2, =SCB_ICSR
movs r3, #128
#if CORTEX_ALTERNATE_SWITCH
diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s index f6acf2968..6be194737 100644 --- a/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s +++ b/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s @@ -36,8 +36,12 @@ ICSR_PENDSVSET EQU 0x10000000 AREA |.text|, CODE, READONLY
IMPORT chThdExit
- IMPORT chSchIsRescRequiredExI
- IMPORT chSchDoRescheduleI
+ IMPORT chSchIsPreemptionRequired
+ IMPORT chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ IMPORT dbg_check_unlock
+ IMPORT dbg_check_lock
+#endif
/*
* Performs a context switch between two threads.
@@ -56,6 +60,9 @@ _port_switch PROC */
EXPORT _port_thread_start
_port_thread_start PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
#if CORTEX_SIMPLIFIED_PRIORITY
cpsie i
#else
@@ -73,10 +80,16 @@ _port_thread_start PROC */
EXPORT _port_switch_from_isr
_port_switch_from_isr PROC
- bl chSchIsRescRequiredExI
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_lock
+#endif
+ bl chSchIsPreemptionRequired
cbz r0, noreschedule
- bl chSchDoRescheduleI
+ bl chSchDoReschedule
noreschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl dbg_check_unlock
+#endif
#if CORTEX_SIMPLIFIED_PRIORITY
mov r3, #SCB_ICSR :AND: 0xFFFF
movt r3, #SCB_ICSR :SHR: 16
diff --git a/os/ports/cosmic/STM8/chcore.c b/os/ports/cosmic/STM8/chcore.c index c5f1de2d6..3c1807330 100644 --- a/os/ports/cosmic/STM8/chcore.c +++ b/os/ports/cosmic/STM8/chcore.c @@ -50,8 +50,8 @@ void _port_switch(Thread *otp) { */
void _port_thread_start(void) {
- _asm(" rim \n"
- " popw x \n");
+ chSysUnlock();
+ _asm(" popw x \n");
}
/**
diff --git a/os/ports/cosmic/STM8/chcore.h b/os/ports/cosmic/STM8/chcore.h index 93a4c24f0..9073592aa 100644 --- a/os/ports/cosmic/STM8/chcore.h +++ b/os/ports/cosmic/STM8/chcore.h @@ -203,8 +203,10 @@ struct stm8_startctx { * enabled to invoke system APIs.
*/
#define PORT_IRQ_EPILOGUE() { \
- if (chSchIsRescRequiredExI()) \
- chSchDoRescheduleI(); \
+ dbg_check_lock(); \
+ if (chSchIsPreemptionRequired()) \
+ chSchDoReschedule(); \
+ dbg_check_unlock(); \
}
/**
|