diff options
Diffstat (limited to 'os/ports/GCC')
| -rw-r--r-- | os/ports/GCC/ARMCMx/chcore_v7m.c | 2 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCMx/chcore_v7m.h | 14 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCMx/port.dox | 2 |
3 files changed, 9 insertions, 9 deletions
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c index be6888ce5..29d02761c 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.c +++ b/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -123,7 +123,7 @@ void _port_init(void) { CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
}
-#if !CH_OPTIMIZE_SPEED
+#if !CH_CFG_OPTIMIZE_SPEED
void _port_lock(void) {
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index 2d99db7a0..8829872a9 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -373,16 +373,16 @@ struct context { * @note In this port this it raises the base priority to kernel level.
*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
+#if CH_CFG_OPTIMIZE_SPEED || defined(__DOXYGEN__)
#define port_lock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
}
-#else /* !CH_OPTIMIZE_SPEED */
+#else /* !CH_CFG_OPTIMIZE_SPEED */
#define port_lock() { \
asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \
}
-#endif /* !CH_OPTIMIZE_SPEED */
+#endif /* !CH_CFG_OPTIMIZE_SPEED */
#else /* CORTEX_SIMPLIFIED_PRIORITY */
#define port_lock() asm volatile ("cpsid i" : : : "memory")
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
@@ -394,16 +394,16 @@ struct context { * @note In this port this it lowers the base priority to user level.
*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
+#if CH_CFG_OPTIMIZE_SPEED || defined(__DOXYGEN__)
#define port_unlock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
}
-#else /* !CH_OPTIMIZE_SPEED */
+#else /* !CH_CFG_OPTIMIZE_SPEED */
#define port_unlock() { \
asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \
}
-#endif /* !CH_OPTIMIZE_SPEED */
+#endif /* !CH_CFG_OPTIMIZE_SPEED */
#else /* CORTEX_SIMPLIFIED_PRIORITY */
#define port_unlock() asm volatile ("cpsie i" : : : "memory")
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
@@ -510,7 +510,7 @@ extern "C" { void _port_exit_from_isr(void);
void _port_switch(thread_t *ntp, thread_t *otp);
void _port_thread_start(void);
-#if !CH_OPTIMIZE_SPEED
+#if !CH_CFG_OPTIMIZE_SPEED
void _port_lock(void);
void _port_unlock(void);
#endif
diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox index 4f209e654..1d6260b12 100644 --- a/os/ports/GCC/ARMCMx/port.dox +++ b/os/ports/GCC/ARMCMx/port.dox @@ -237,7 +237,7 @@ * stack checking is enabled (<tt>CH_DBG_ENABLE_STACK_CHECK==TRUE</tt>),
* it is an alias of @p __process_stack_base__ in this port.
* - @p __heap_base__ and @p __heap_end__, those symbols are required
- * if the memory core manager is enabled (<tt>CH_USE_MEMCORE==TRUE</tt>)
+ * if the memory core manager is enabled (<tt>CH_CFG_USE_MEMCORE==TRUE</tt>)
* with a default core size set to zero (<tt>CH_MEMCORE_SIZE==0</tt>).
* .
* @ingroup ARMCMx
|