diff options
Diffstat (limited to 'os/hal/boards/SEEED_ARCH_MAX')
| -rwxr-xr-x | os/hal/boards/SEEED_ARCH_MAX/board.c | 266 | ||||
| -rwxr-xr-x | os/hal/boards/SEEED_ARCH_MAX/board.h | 1380 | ||||
| -rwxr-xr-x | os/hal/boards/SEEED_ARCH_MAX/board.mk | 9 | ||||
| -rwxr-xr-x | os/hal/boards/SEEED_ARCH_MAX/cfg/board.chcfg | 342 | ||||
| -rw-r--r-- | os/hal/boards/SEEED_ARCH_MAX/cfg/board.fmpp | 15 |
5 files changed, 2012 insertions, 0 deletions
diff --git a/os/hal/boards/SEEED_ARCH_MAX/board.c b/os/hal/boards/SEEED_ARCH_MAX/board.c new file mode 100755 index 000000000..1796841ac --- /dev/null +++ b/os/hal/boards/SEEED_ARCH_MAX/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB1(STM32_GPIO_EN_MASK);
+ rccEnableAHB1(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+ static bool last_status = false; + + if (blkIsTransferring(sdcp)) + return last_status; + return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+ + (void)sdcp; + return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/SEEED_ARCH_MAX/board.h b/os/hal/boards/SEEED_ARCH_MAX/board.h new file mode 100755 index 000000000..9496df145 --- /dev/null +++ b/os/hal/boards/SEEED_ARCH_MAX/board.h @@ -0,0 +1,1380 @@ +/*
+ ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for Seeed Arch Max board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_SEEED_ARCH_MAX
+#define BOARD_NAME "Seeed Arch Max"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID MII_KS8721_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 330U
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F407xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON_WKUP 0U
+#define GPIOA_ETH_RMII_REF_CLK 1U
+#define GPIOA_ETH_RMII_MDIO 2U
+#define GPIOA_ETH_RMII_MDINT 3U
+#define GPIOA_PIN4 4U
+#define GPIOA_PIN5 5U
+#define GPIOA_PIN6 6U
+#define GPIOA_ETH_RMII_CRS_DV 7U
+#define GPIOA_USB_HS_BUSON 8U
+#define GPIOA_OTG_FS_VBUS 9U
+#define GPIOA_OTG_FS_ID 10U
+#define GPIOA_OTG_FS_DM 11U
+#define GPIOA_OTG_FS_DP 12U
+#define GPIOA_JTAG_TMS 13U
+#define GPIOA_JTAG_TCK 14U
+#define GPIOA_JTAG_TDI 15U
+
+#define GPIOB_USB_FS_BUSON 0U
+#define GPIOB_USB_HS_FAULT 1U
+#define GPIOB_BOOT1 2U
+#define GPIOB_JTAG_TDO 3U
+#define GPIOB_JTAG_TRST 4U
+#define GPIOB_PIN5 5U
+#define GPIOB_PIN6 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_I2C1_SCL 8U
+#define GPIOB_I2C1_SDA 9U
+#define GPIOB_SPI2_SCK 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_OTG_HS_ID 12U
+#define GPIOB_OTG_HS_VBUS 13U
+#define GPIOB_OTG_HS_DM 14U
+#define GPIOB_OTG_HS_DP 15U
+
+#define GPIOC_PIN0 0U
+#define GPIOC_ETH_RMII_MDC 1U
+#define GPIOC_SPI2_MISO 2U
+#define GPIOC_SPI2_MOSI 3U
+#define GPIOC_ETH_RMII_RXD0 4U
+#define GPIOC_ETH_RMII_RXD1 5U
+#define GPIOC_USART6_TX 6U
+#define GPIOC_USART6_RX 7U
+#define GPIOC_SD_D0 8U
+#define GPIOC_SD_D1 9U
+#define GPIOC_SD_D2 10U
+#define GPIOC_SD_D3 11U
+#define GPIOC_SD_CLK 12U
+#define GPIOC_LED 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_SD_CMD 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_PIN0 0U
+#define GPIOF_PIN1 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_USB_FS_FAULT 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+#define GPIOG_PIN0 0U
+#define GPIOG_PIN1 1U
+#define GPIOG_PIN2 2U
+#define GPIOG_PIN3 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_PIN6 6U
+#define GPIOG_PIN7 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_PIN9 9U
+#define GPIOG_SPI2_CS 10U
+#define GPIOG_ETH_RMII_TXEN 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_ETH_RMII_TXD0 13U
+#define GPIOG_ETH_RMII_TXD1 14U
+#define GPIOG_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+#define GPIOI_PIN0 0U
+#define GPIOI_PIN1 1U
+#define GPIOI_PIN2 2U
+#define GPIOI_PIN3 3U
+#define GPIOI_PIN4 4U
+#define GPIOI_PIN5 5U
+#define GPIOI_PIN6 6U
+#define GPIOI_PIN7 7U
+#define GPIOI_PIN8 8U
+#define GPIOI_PIN9 9U
+#define GPIOI_PIN10 10U
+#define GPIOI_PIN11 11U
+#define GPIOI_PIN12 12U
+#define GPIOI_PIN13 13U
+#define GPIOI_PIN14 14U
+#define GPIOI_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_BUTTON_WKUP PAL_LINE(GPIOA, 0U)
+#define LINE_ETH_RMII_REF_CLK PAL_LINE(GPIOA, 1U)
+#define LINE_ETH_RMII_MDIO PAL_LINE(GPIOA, 2U)
+#define LINE_ETH_RMII_MDINT PAL_LINE(GPIOA, 3U)
+#define LINE_ETH_RMII_CRS_DV PAL_LINE(GPIOA, 7U)
+#define LINE_USB_HS_BUSON PAL_LINE(GPIOA, 8U)
+#define LINE_OTG_FS_VBUS PAL_LINE(GPIOA, 9U)
+#define LINE_OTG_FS_ID PAL_LINE(GPIOA, 10U)
+#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U)
+#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U)
+#define LINE_JTAG_TMS PAL_LINE(GPIOA, 13U)
+#define LINE_JTAG_TCK PAL_LINE(GPIOA, 14U)
+#define LINE_JTAG_TDI PAL_LINE(GPIOA, 15U)
+#define LINE_USB_FS_BUSON PAL_LINE(GPIOB, 0U)
+#define LINE_USB_HS_FAULT PAL_LINE(GPIOB, 1U)
+#define LINE_BOOT1 PAL_LINE(GPIOB, 2U)
+#define LINE_JTAG_TDO PAL_LINE(GPIOB, 3U)
+#define LINE_JTAG_TRST PAL_LINE(GPIOB, 4U)
+#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U)
+#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U)
+#define LINE_SPI2_SCK PAL_LINE(GPIOB, 10U)
+#define LINE_OTG_HS_ID PAL_LINE(GPIOB, 12U)
+#define LINE_OTG_HS_VBUS PAL_LINE(GPIOB, 13U)
+#define LINE_OTG_HS_DM PAL_LINE(GPIOB, 14U)
+#define LINE_OTG_HS_DP PAL_LINE(GPIOB, 15U)
+#define LINE_ETH_RMII_MDC PAL_LINE(GPIOC, 1U)
+#define LINE_SPI2_MISO PAL_LINE(GPIOC, 2U)
+#define LINE_SPI2_MOSI PAL_LINE(GPIOC, 3U)
+#define LINE_ETH_RMII_RXD0 PAL_LINE(GPIOC, 4U)
+#define LINE_ETH_RMII_RXD1 PAL_LINE(GPIOC, 5U)
+#define LINE_USART6_TX PAL_LINE(GPIOC, 6U)
+#define LINE_USART6_RX PAL_LINE(GPIOC, 7U)
+#define LINE_SD_D0 PAL_LINE(GPIOC, 8U)
+#define LINE_SD_D1 PAL_LINE(GPIOC, 9U)
+#define LINE_SD_D2 PAL_LINE(GPIOC, 10U)
+#define LINE_SD_D3 PAL_LINE(GPIOC, 11U)
+#define LINE_SD_CLK PAL_LINE(GPIOC, 12U)
+#define LINE_LED PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_SD_CMD PAL_LINE(GPIOD, 2U)
+#define LINE_USB_FS_FAULT PAL_LINE(GPIOF, 11U)
+#define LINE_SPI2_CS PAL_LINE(GPIOG, 10U)
+#define LINE_ETH_RMII_TXEN PAL_LINE(GPIOG, 11U)
+#define LINE_ETH_RMII_TXD0 PAL_LINE(GPIOG, 13U)
+#define LINE_ETH_RMII_TXD1 PAL_LINE(GPIOG, 14U)
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - BUTTON_WKUP (input floating).
+ * PA1 - ETH_RMII_REF_CLK (alternate 11).
+ * PA2 - ETH_RMII_MDIO (alternate 11).
+ * PA3 - ETH_RMII_MDINT (input floating).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - PIN5 (input pullup).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - ETH_RMII_CRS_DV (alternate 11).
+ * PA8 - USB_HS_BUSON (output pushpull maximum).
+ * PA9 - OTG_FS_VBUS (input pulldown).
+ * PA10 - OTG_FS_ID (alternate 10).
+ * PA11 - OTG_FS_DM (alternate 10).
+ * PA12 - OTG_FS_DP (alternate 10).
+ * PA13 - JTAG_TMS (alternate 0).
+ * PA14 - JTAG_TCK (alternate 0).
+ * PA15 - JTAG_TDI (alternate 0).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) |\
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) |\
+ PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_INPUT(GPIOA_PIN5) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\
+ PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) | \
+ PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_WKUP) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_REF_CLK) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDIO) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDINT) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON_WKUP) | \
+ PIN_OSPEED_HIGH(GPIOA_ETH_RMII_REF_CLK) |\
+ PIN_OSPEED_HIGH(GPIOA_ETH_RMII_MDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_ETH_RMII_MDINT) |\
+ PIN_OSPEED_HIGH(GPIOA_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOA_ETH_RMII_CRS_DV) |\
+ PIN_OSPEED_HIGH(GPIOA_USB_HS_BUSON) | \
+ PIN_OSPEED_HIGH(GPIOA_OTG_FS_VBUS) | \
+ PIN_OSPEED_HIGH(GPIOA_OTG_FS_ID) | \
+ PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_HIGH(GPIOA_JTAG_TMS) | \
+ PIN_OSPEED_HIGH(GPIOA_JTAG_TCK) | \
+ PIN_OSPEED_HIGH(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON_WKUP) |\
+ PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_REF_CLK) |\
+ PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDIO) |\
+ PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDINT) |\
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\
+ PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\
+ PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) | \
+ PIN_PUPDR_FLOATING(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON_WKUP) | \
+ PIN_ODR_HIGH(GPIOA_ETH_RMII_REF_CLK) | \
+ PIN_ODR_HIGH(GPIOA_ETH_RMII_MDIO) | \
+ PIN_ODR_HIGH(GPIOA_ETH_RMII_MDINT) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_HIGH(GPIOA_PIN5) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) | \
+ PIN_ODR_LOW(GPIOA_USB_HS_BUSON) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \
+ PIN_ODR_HIGH(GPIOA_JTAG_TCK) | \
+ PIN_ODR_HIGH(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_WKUP, 0U) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11U) |\
+ PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11U) |\
+ PIN_AFIO_AF(GPIOA_ETH_RMII_MDINT, 0U) |\
+ PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0U) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0U) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TMS, 0U) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TCK, 0U) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TDI, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - USB_FS_BUSON (output pushpull maximum).
+ * PB1 - USB_HS_FAULT (input floating).
+ * PB2 - BOOT1 (input floating).
+ * PB3 - JTAG_TDO (alternate 0).
+ * PB4 - JTAG_TRST (alternate 0).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - PIN6 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - I2C1_SCL (alternate 4).
+ * PB9 - I2C1_SDA (alternate 4).
+ * PB10 - SPI2_SCK (alternate 5).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - OTG_HS_ID (alternate 12).
+ * PB13 - OTG_HS_VBUS (input pulldown).
+ * PB14 - OTG_HS_DM (alternate 12).
+ * PB15 - OTG_HS_DP (alternate 12).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) | \
+ PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \
+ PIN_MODE_INPUT(GPIOB_BOOT1) | \
+ PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \
+ PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_INPUT(GPIOB_PIN6) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
+ PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \
+ PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_BUSON) |\
+ PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\
+ PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\
+ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_USB_FS_BUSON) | \
+ PIN_OSPEED_HIGH(GPIOB_USB_HS_FAULT) | \
+ PIN_OSPEED_HIGH(GPIOB_BOOT1) | \
+ PIN_OSPEED_HIGH(GPIOB_JTAG_TDO) | \
+ PIN_OSPEED_HIGH(GPIOB_JTAG_TRST) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \
+ PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \
+ PIN_OSPEED_HIGH(GPIOB_SPI2_SCK) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOB_OTG_HS_ID) | \
+ PIN_OSPEED_HIGH(GPIOB_OTG_HS_VBUS) | \
+ PIN_OSPEED_HIGH(GPIOB_OTG_HS_DM) | \
+ PIN_OSPEED_HIGH(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_USB_FS_BUSON) |\
+ PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\
+ PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \
+ PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \
+ PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \
+ PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) | \
+ PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\
+ PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_USB_FS_BUSON) | \
+ PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) | \
+ PIN_ODR_HIGH(GPIOB_BOOT1) | \
+ PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \
+ PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_PIN6) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \
+ PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \
+ PIN_ODR_HIGH(GPIOB_SPI2_SCK) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_OTG_HS_ID) | \
+ PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \
+ PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \
+ PIN_ODR_HIGH(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0U) | \
+ PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0U) | \
+ PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \
+ PIN_AFIO_AF(GPIOB_JTAG_TDO, 0U) | \
+ PIN_AFIO_AF(GPIOB_JTAG_TRST, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \
+ PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \
+ PIN_AFIO_AF(GPIOB_SPI2_SCK, 5U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12U) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0U) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12U) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - ETH_RMII_MDC (alternate 11).
+ * PC2 - SPI2_MISO (alternate 5).
+ * PC3 - SPI2_MOSI (alternate 5).
+ * PC4 - ETH_RMII_RXD0 (alternate 11).
+ * PC5 - ETH_RMII_RXD1 (alternate 11).
+ * PC6 - USART6_TX (alternate 8).
+ * PC7 - USART6_RX (alternate 8).
+ * PC8 - SD_D0 (alternate 12).
+ * PC9 - SD_D1 (alternate 12).
+ * PC10 - SD_D2 (alternate 12).
+ * PC11 - SD_D3 (alternate 12).
+ * PC12 - SD_CLK (alternate 12).
+ * PC13 - LED (output pushpull maximum).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) |\
+ PIN_MODE_ALTERNATE(GPIOC_SPI2_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI2_MOSI) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) |\
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) |\
+ PIN_MODE_ALTERNATE(GPIOC_USART6_TX) | \
+ PIN_MODE_ALTERNATE(GPIOC_USART6_RX) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D0) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D1) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D2) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D3) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \
+ PIN_MODE_OUTPUT(GPIOC_LED) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_MDC) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MISO) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MOSI) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD0) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD1) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_USART6_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_USART6_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_LED) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOC_ETH_RMII_MDC) | \
+ PIN_OSPEED_HIGH(GPIOC_SPI2_MISO) | \
+ PIN_OSPEED_HIGH(GPIOC_SPI2_MOSI) | \
+ PIN_OSPEED_HIGH(GPIOC_ETH_RMII_RXD0) | \
+ PIN_OSPEED_HIGH(GPIOC_ETH_RMII_RXD1) | \
+ PIN_OSPEED_HIGH(GPIOC_USART6_TX) | \
+ PIN_OSPEED_HIGH(GPIOC_USART6_RX) | \
+ PIN_OSPEED_HIGH(GPIOC_SD_D0) | \
+ PIN_OSPEED_HIGH(GPIOC_SD_D1) | \
+ PIN_OSPEED_HIGH(GPIOC_SD_D2) | \
+ PIN_OSPEED_HIGH(GPIOC_SD_D3) | \
+ PIN_OSPEED_HIGH(GPIOC_SD_CLK) | \
+ PIN_OSPEED_HIGH(GPIOC_LED) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_MDC) |\
+ PIN_PUPDR_FLOATING(GPIOC_SPI2_MISO) | \
+ PIN_PUPDR_FLOATING(GPIOC_SPI2_MOSI) | \
+ PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD0) |\
+ PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD1) |\
+ PIN_PUPDR_FLOATING(GPIOC_USART6_TX) | \
+ PIN_PUPDR_FLOATING(GPIOC_USART6_RX) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D0) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D1) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D2) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D3) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_CLK) | \
+ PIN_PUPDR_FLOATING(GPIOC_LED) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_ETH_RMII_MDC) | \
+ PIN_ODR_HIGH(GPIOC_SPI2_MISO) | \
+ PIN_ODR_HIGH(GPIOC_SPI2_MOSI) | \
+ PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD0) | \
+ PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD1) | \
+ PIN_ODR_HIGH(GPIOC_USART6_TX) | \
+ PIN_ODR_HIGH(GPIOC_USART6_RX) | \
+ PIN_ODR_HIGH(GPIOC_SD_D0) | \
+ PIN_ODR_HIGH(GPIOC_SD_D1) | \
+ PIN_ODR_HIGH(GPIOC_SD_D2) | \
+ PIN_ODR_HIGH(GPIOC_SD_D3) | \
+ PIN_ODR_HIGH(GPIOC_SD_CLK) | \
+ PIN_ODR_HIGH(GPIOC_LED) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11U) | \
+ PIN_AFIO_AF(GPIOC_SPI2_MISO, 5U) | \
+ PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5U) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11U) |\
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11U) |\
+ PIN_AFIO_AF(GPIOC_USART6_TX, 8U) | \
+ PIN_AFIO_AF(GPIOC_USART6_RX, 8U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12U) | \
+ PIN_AFIO_AF(GPIOC_SD_D1, 12U) | \
+ PIN_AFIO_AF(GPIOC_SD_D2, 12U) | \
+ PIN_AFIO_AF(GPIOC_SD_D3, 12U) | \
+ PIN_AFIO_AF(GPIOC_SD_CLK, 12U) | \
+ PIN_AFIO_AF(GPIOC_LED, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - SD_CMD (alternate 12).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOD_SD_CMD) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_SD_CMD) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_SD_CMD, 12U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - PIN2 (input pullup).
+ * PE3 - PIN3 (input pullup).
+ * PE4 - PIN4 (input pullup).
+ * PE5 - PIN5 (input pullup).
+ * PE6 - PIN6 (input pullup).
+ * PE7 - PIN7 (input pullup).
+ * PE8 - PIN8 (input pullup).
+ * PE9 - PIN9 (input pullup).
+ * PE10 - PIN10 (input pullup).
+ * PE11 - PIN11 (input pullup).
+ * PE12 - PIN12 (input pullup).
+ * PE13 - PIN13 (input pullup).
+ * PE14 - PIN14 (input pullup).
+ * PE15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_PIN3) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input pullup).
+ * PF1 - PIN1 (input pullup).
+ * PF2 - PIN2 (input pullup).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - PIN4 (input pullup).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - PIN7 (input pullup).
+ * PF8 - PIN8 (input pullup).
+ * PF9 - PIN9 (input pullup).
+ * PF10 - PIN10 (input pullup).
+ * PF11 - USB_FS_FAULT (input floating).
+ * PF12 - PIN12 (input pullup).
+ * PF13 - PIN13 (input pullup).
+ * PF14 - PIN14 (input pullup).
+ * PF15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_USB_FS_FAULT) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT) |\
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOF_USB_FS_FAULT) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT) |\
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_USB_FS_FAULT) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_USB_FS_FAULT, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input pullup).
+ * PG1 - PIN1 (input pullup).
+ * PG2 - PIN2 (input pullup).
+ * PG3 - PIN3 (input pullup).
+ * PG4 - PIN4 (input pullup).
+ * PG5 - PIN5 (input pullup).
+ * PG6 - PIN6 (input pullup).
+ * PG7 - PIN7 (input pullup).
+ * PG8 - PIN8 (input pullup).
+ * PG9 - PIN9 (input pullup).
+ * PG10 - SPI2_CS (output pushpull maximum).
+ * PG11 - ETH_RMII_TXEN (alternate 11).
+ * PG12 - PIN12 (input pullup).
+ * PG13 - ETH_RMII_TXD0 (alternate 11).
+ * PG14 - ETH_RMII_TXD1 (alternate 11).
+ * PG15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_INPUT(GPIOG_PIN6) | \
+ PIN_MODE_INPUT(GPIOG_PIN7) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_OUTPUT(GPIOG_SPI2_CS) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXEN) |\
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) |\
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) |\
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_SPI2_CS) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXEN) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD0) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD1) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOG_SPI2_CS) | \
+ PIN_OSPEED_HIGH(GPIOG_ETH_RMII_TXEN) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOG_ETH_RMII_TXD0) | \
+ PIN_OSPEED_HIGH(GPIOG_ETH_RMII_TXD1) | \
+ PIN_OSPEED_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_SPI2_CS) | \
+ PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXEN) |\
+ PIN_PUPDR_PULLUP(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD0) |\
+ PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD1) |\
+ PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_SPI2_CS) | \
+ PIN_ODR_HIGH(GPIOG_ETH_RMII_TXEN) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD0) | \
+ PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD1) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOG_SPI2_CS, 0U) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11U) |\
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11U) |\
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11U) |\
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input pullup).
+ * PH3 - PIN3 (input pullup).
+ * PH4 - PIN4 (input pullup).
+ * PH5 - PIN5 (input pullup).
+ * PH6 - PIN6 (input pullup).
+ * PH7 - PIN7 (input pullup).
+ * PH8 - PIN8 (input pullup).
+ * PH9 - PIN9 (input pullup).
+ * PH10 - PIN10 (input pullup).
+ * PH11 - PIN11 (input pullup).
+ * PH12 - PIN12 (input pullup).
+ * PH13 - PIN13 (input pullup).
+ * PH14 - PIN14 (input pullup).
+ * PH15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input pullup).
+ * PI1 - PIN1 (input pullup).
+ * PI2 - PIN2 (input pullup).
+ * PI3 - PIN3 (input pullup).
+ * PI4 - PIN4 (input pullup).
+ * PI5 - PIN5 (input pullup).
+ * PI6 - PIN6 (input pullup).
+ * PI7 - PIN7 (input pullup).
+ * PI8 - PIN8 (input pullup).
+ * PI9 - PIN9 (input pullup).
+ * PI10 - PIN10 (input pullup).
+ * PI11 - PIN11 (input pullup).
+ * PI12 - PIN12 (input pullup).
+ * PI13 - PIN13 (input pullup).
+ * PI14 - PIN14 (input pullup).
+ * PI15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0U))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/os/hal/boards/SEEED_ARCH_MAX/board.mk b/os/hal/boards/SEEED_ARCH_MAX/board.mk new file mode 100755 index 000000000..4f0ee6156 --- /dev/null +++ b/os/hal/boards/SEEED_ARCH_MAX/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/SEEED_ARCH_MAX/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/SEEED_ARCH_MAX
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/SEEED_ARCH_MAX/cfg/board.chcfg b/os/hal/boards/SEEED_ARCH_MAX/cfg/board.chcfg new file mode 100755 index 000000000..22f24665a --- /dev/null +++ b/os/hal/boards/SEEED_ARCH_MAX/cfg/board.chcfg @@ -0,0 +1,342 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F4xx board Template -->
+<board xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+ <output_path>..</output_path>
+ <hal_version>5.0.x</hal_version>
+ </configuration_settings>
+ <board_name>Seeed Arch Max</board_name>
+ <board_id>SEEED_ARCH_MAX</board_id>
+ <board_functions>
+ <sdc_lld_is_card_inserted><![CDATA[ static bool last_status = false;
+
+ if (blkIsTransferring(sdcp))
+ return last_status;
+ return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
+ <sdc_lld_is_write_protected>
+<![CDATA[ (void)sdcp;
+ return false;]]></sdc_lld_is_write_protected>
+ </board_functions>
+ <ethernet_phy>
+ <identifier>MII_KS8721_ID</identifier>
+ <bus_type>RMII</bus_type>
+ </ethernet_phy>
+ <subtype>STM32F407xx</subtype>
+ <clocks
+ HSEFrequency="8000000"
+ HSEBypass="false"
+ LSEFrequency="32768"
+ LSEBypass="false"
+ VDD="330"
+ />
+ <ports>
+ <GPIOA>
+ <pin0 ID="BUTTON_WKUP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="ETH_RMII_REF_CLK" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin2 ID="ETH_RMII_MDIO" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin3 ID="ETH_RMII_MDINT" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="ETH_RMII_CRS_DV" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin8 ID="USB_HS_BUSON" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="Low" Mode="Output" Alternate="0" />
+ <pin9 ID="OTG_FS_VBUS" Type="PushPull" Speed="Maximum" Resistor="PullDown"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="OTG_FS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="10" />
+ <pin11 ID="OTG_FS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="10" />
+ <pin12 ID="OTG_FS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="10" />
+ <pin13 ID="JTAG_TMS" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="0" />
+ <pin14 ID="JTAG_TCK" Type="PushPull" Speed="Maximum" Resistor="PullDown"
+ Level="High" Mode="Alternate" Alternate="0" />
+ <pin15 ID="JTAG_TDI" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="0" />
+ </GPIOA>
+ <GPIOB>
+ <pin0 ID="USB_FS_BUSON" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="Low" Mode="Output" Alternate="0" />
+ <pin1 ID="USB_HS_FAULT" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="BOOT1" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="JTAG_TDO" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="0" />
+ <pin4 ID="JTAG_TRST" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="I2C1_SCL" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="4" />
+ <pin9 ID="I2C1_SDA" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="4" />
+ <pin10 ID="SPI2_SCK" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="5" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="OTG_HS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin13 ID="OTG_HS_VBUS" Type="PushPull" Speed="Maximum"
+ Resistor="PullDown" Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="OTG_HS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin15 ID="OTG_HS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ </GPIOB>
+ <GPIOC>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="ETH_RMII_MDC" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin2 ID="SPI2_MISO" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="5" />
+ <pin3 ID="SPI2_MOSI" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="5" />
+ <pin4 ID="ETH_RMII_RXD0" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin5 ID="ETH_RMII_RXD1" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin6 ID="USART6_TX" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="8" />
+ <pin7 ID="USART6_RX" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="8" />
+ <pin8 ID="SD_D0" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin9 ID="SD_D1" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin10 ID="SD_D2" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin11 ID="SD_D3" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin12 ID="SD_CLK" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin13 ID="LED" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Output" Alternate="0" />
+ <pin14 ID="OSC32_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="OSC32_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="SD_CMD" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="USB_FS_FAULT" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOF>
+ <GPIOG>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="SPI2_CS" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Output" Alternate="0" />
+ <pin11 ID="ETH_RMII_TXEN" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="ETH_RMII_TXD0" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin14 ID="ETH_RMII_TXD1" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOG>
+ <GPIOH>
+ <pin0 ID="OSC_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0"></pin0>
+ <pin1 ID="OSC_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOH>
+ <GPIOI>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOI>
+ </ports>
+</board>
diff --git a/os/hal/boards/SEEED_ARCH_MAX/cfg/board.fmpp b/os/hal/boards/SEEED_ARCH_MAX/cfg/board.fmpp new file mode 100644 index 000000000..41754c141 --- /dev/null +++ b/os/hal/boards/SEEED_ARCH_MAX/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32f4xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} |