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-rw-r--r--os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld156
-rw-r--r--os/common/ports/ARMCMx/devices/KL2x/cmparams.h87
-rw-r--r--os/ext/CMSIS/KINETIS/kl25z.h1147
-rw-r--r--os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c128
-rw-r--r--os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h44
-rw-r--r--os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk5
-rw-r--r--os/hal/ports/KINETIS/KL2x/hal_lld.c282
-rw-r--r--os/hal/ports/KINETIS/KL2x/hal_lld.h268
-rw-r--r--os/hal/ports/KINETIS/KL2x/kl25z.h1147
-rw-r--r--os/hal/ports/KINETIS/KL2x/pal_lld.c225
-rw-r--r--os/hal/ports/KINETIS/KL2x/pal_lld.h309
-rw-r--r--os/hal/ports/KINETIS/KL2x/platform.mk10
-rw-r--r--os/hal/ports/KINETIS/KL2x/serial_lld.c353
-rw-r--r--os/hal/ports/KINETIS/KL2x/serial_lld.h163
-rw-r--r--os/hal/ports/KINETIS/KL2x/st_lld.c98
-rw-r--r--os/hal/ports/KINETIS/KL2x/st_lld.h156
16 files changed, 4578 insertions, 0 deletions
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld
new file mode 100644
index 000000000..79acb2048
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld
@@ -0,0 +1,156 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * KL25Z128 memory setup.
+ */
+__main_stack_size__ = 0x0400;
+__process_stack_size__ = 0x0400;
+
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0xc0
+ flashcfg : org = 0x00000400, len = 0x10
+ flash : org = 0x00000410, len = 128k - 0x410
+ ram : org = 0x1FFFF000, len = 16k
+}
+
+__ram_start__ = ORIGIN(ram);
+__ram_size__ = LENGTH(ram);
+__ram_end__ = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+ . = 0;
+
+ .isr : ALIGN(4) SUBALIGN(4)
+ {
+ KEEP(*(vectors))
+ } > flash0
+
+ .cfmprotect : ALIGN(4) SUBALIGN(4)
+ {
+ KEEP(*(.cfmconfig))
+ } > flashcfg
+
+ _text = .;
+
+ constructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__fini_array_start = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .text : ALIGN(4) SUBALIGN(4)
+ {
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ .ARM.exidx : {
+ PROVIDE(__exidx_start = .);
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ PROVIDE(__exidx_end = .);
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .textalign : ONLY_IF_RO
+ {
+ . = ALIGN(8);
+ } > flash
+
+ _etext = .;
+ _textdata = _etext;
+
+ .stacks :
+ {
+ . = ALIGN(8);
+ __main_stack_base__ = .;
+ . += __main_stack_size__;
+ . = ALIGN(8);
+ __main_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .data :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data = .);
+ *(.data)
+ . = ALIGN(4);
+ *(.data.*)
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ PROVIDE(_edata = .);
+ } > ram AT > flash
+
+ .bss :
+ {
+ . = ALIGN(4);
+ PROVIDE(_bss_start = .);
+ *(.bss)
+ . = ALIGN(4);
+ *(.bss.*)
+ . = ALIGN(4);
+ *(COMMON)
+ . = ALIGN(4);
+ PROVIDE(_bss_end = .);
+ } > ram
+}
+
+PROVIDE(end = .);
+_end = .;
+
+__heap_base__ = _end;
+__heap_end__ = __ram_end__;
diff --git a/os/common/ports/ARMCMx/devices/KL2x/cmparams.h b/os/common/ports/ARMCMx/devices/KL2x/cmparams.h
new file mode 100644
index 000000000..00b68d1cb
--- /dev/null
+++ b/os/common/ports/ARMCMx/devices/KL2x/cmparams.h
@@ -0,0 +1,87 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file GCC/ARMCMx/KL2x/cmparams.h
+ * @brief ARM Cortex-M0+ parameters for the Kinetis KL2x.
+ *
+ * @defgroup ARMCMx_KL2x Kinetis KL2x Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0+ specific parameters for the
+ * Kinetis KL2x platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL CORTEX_M0PLUS
+
+/**
+ * @brief Systick unit presence.
+ */
+#define CORTEX_HAS_ST TRUE
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU FALSE
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU FALSE
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "kl25z.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/ext/CMSIS/KINETIS/kl25z.h b/os/ext/CMSIS/KINETIS/kl25z.h
new file mode 100644
index 000000000..5baa4dc3b
--- /dev/null
+++ b/os/ext/CMSIS/KINETIS/kl25z.h
@@ -0,0 +1,1147 @@
+/*
+ * Copyright © 2013-2014 Fabio Utzig, http://fabioutzig.com
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the “Software”),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _KL25Z_H_
+#define _KL25Z_H_
+
+/*
+ * ==============================================================
+ * ---------- Interrupt Number Definition -----------------------
+ * ==============================================================
+ */
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ****************/
+ Reset_IRQn = -15,
+ NonMaskableInt_IRQn = -14,
+ HardFault_IRQn = -13,
+ SVCall_IRQn = -5,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+
+/****** KL2x Specific Interrupt Numbers ***********************/
+ DMA0_IRQn = 0,
+ DMA1_IRQn = 1,
+ DMA2_IRQn = 2,
+ DMA3_IRQn = 3,
+ Reserved0_IRQn = 4,
+ FTFA_IRQn = 5,
+ PMC_IRQn = 6,
+ LLWU_IRQn = 7,
+ I2C0_IRQn = 8,
+ I2C1_IRQn = 9,
+ SPI0_IRQn = 10,
+ SPI1_IRQn = 11,
+ UART0_IRQn = 12,
+ UART1_IRQn = 13,
+ UART2_IRQn = 14,
+ ADC0_IRQn = 15,
+ CMP0_IRQn = 16,
+ TMP0_IRQn = 17,
+ TMP1_IRQn = 18,
+ TMP2_IRQn = 19,
+ RTC0_IRQn = 20,
+ RTC1_IRQn = 21,
+ PIT_IRQn = 22,
+ Reserved1_IRQn = 23,
+ USB_OTG_IRQn = 24,
+ DAC0_IRQn = 25,
+ TSI0_IRQn = 26,
+ MCG_IRQn = 27,
+ LPTMR0_IRQn = 28,
+ Reserved2_IRQn = 29,
+ PINA_IRQn = 30,
+ PIND_IRQn = 31,
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/**
+ * @brief STM32F0xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+
+typedef struct
+{
+ __IO uint32_t SOPT1;
+ __IO uint32_t SOPT1CFG;
+ uint32_t RESERVED0[1023];
+ __IO uint32_t SOPT2;
+ __I uint32_t RESERVED1[1];
+ __IO uint32_t SOPT4;
+ __IO uint32_t SOPT5;
+ uint32_t RESERVED2[1];
+ __IO uint32_t SOPT7;
+ uint32_t RESERVED3[2];
+ __IO uint32_t SDID;
+ uint32_t RESERVED4[3];
+ __IO uint32_t SCGC4;
+ __IO uint32_t SCGC5;
+ __IO uint32_t SCGC6;
+ __IO uint32_t SCGC7;
+ __IO uint32_t CLKDIV1;
+ uint32_t RESERVED5[1];
+ __IO uint32_t FCFG1;
+ __IO uint32_t FCFG2;
+ uint32_t RESERVED6[1];
+ __IO uint32_t UIDMH;
+ __IO uint32_t UIDML;
+ __IO uint32_t UIDL;
+ uint32_t RESERVED7[39];
+ __IO uint32_t COPC;
+ __IO uint32_t SRVCOP;
+} SIM_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t PE1;
+ __IO uint8_t PE2;
+ __IO uint8_t PE3;
+ __IO uint8_t PE4;
+ __IO uint8_t ME;
+ __IO uint8_t F1;
+ __IO uint8_t F2;
+ __I uint8_t F3;
+ __IO uint8_t FILT1;
+ __IO uint8_t FILT2;
+} LLWU_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t PCR[32];
+ __IO uint32_t GPCLR;
+ __IO uint32_t GPCHR;
+ uint32_t RESERVED0[6];
+ __IO uint32_t ISFR;
+} PORT_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t C1;
+ __IO uint8_t C2;
+ __IO uint8_t C3;
+ __IO uint8_t C4;
+ __IO uint8_t C5;
+ __IO uint8_t C6;
+ __IO uint8_t S;
+ uint8_t RESERVED0[1];
+ __IO uint8_t SC;
+ uint8_t RESERVED1[1];
+ __IO uint8_t ATCVH;
+ __IO uint8_t ATCVL;
+ __IO uint8_t C7;
+ __IO uint8_t C8;
+ __IO uint8_t C9;
+ __IO uint8_t C10;
+} MCG_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t CR;
+} OSC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SAR;
+ __IO uint32_t DAR;
+ __IO uint32_t DSR_BCR;
+ __IO uint32_t DCR;
+} DMAChannel_TypeDef;
+
+typedef struct
+{
+ DMAChannel_TypeDef ch[4];
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t CHCFG[4];
+} DMAMUX_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SC;
+ __IO uint32_t CNT;
+ __IO uint32_t MOD;
+ __IO uint32_t C0SC;
+ __IO uint32_t C0V;
+ __IO uint32_t C1SC;
+ __IO uint32_t C1V;
+ __IO uint32_t C2SC;
+ __IO uint32_t C2V;
+ __IO uint32_t C3SC;
+ __IO uint32_t C3V;
+ __IO uint32_t C4SC;
+ __IO uint32_t C4V;
+ __IO uint32_t C5SC;
+ __IO uint32_t C5V;
+ uint32_t RESERVED0[5];
+ __IO uint32_t STATUS;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CONF;
+} TPM_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SC1A; // offset: 0x00
+ __IO uint32_t SC1B; // offset: 0x04
+ __IO uint32_t CFG1; // offset: 0x08
+ __IO uint32_t CFG2; // offset: 0x0C
+ __I uint32_t RA; // offset: 0x10
+ __I uint32_t RB; // offset: 0x14
+ __IO uint32_t CV1; // offset: 0x18
+ __IO uint32_t CV2; // offset: 0x1C
+ __IO uint32_t SC2; // offset: 0x20
+ __IO uint32_t SC3; // offset: 0x24
+ __IO uint32_t OFS; // offset: 0x28
+ __IO uint32_t PG; // offset: 0x2C
+ __IO uint32_t MG; // offset: 0x30
+ __IO uint32_t CLPD; // offset: 0x34
+ __IO uint32_t CLPS; // offset: 0x38
+ __IO uint32_t CLP4; // offset: 0x3C
+ __IO uint32_t CLP3; // offset: 0x40
+ __IO uint32_t CLP2; // offset: 0x44
+ __IO uint32_t CLP1; // offset: 0x48
+ __IO uint32_t CLP0; // offset: 0x4C
+ uint32_t RESERVED0[1]; // offset: 0x50
+ __IO uint32_t CLMD; // offset: 0x54
+ __IO uint32_t CLMS; // offset: 0x58
+ __IO uint32_t CLM4; // offset: 0x5C
+ __IO uint32_t CLM3; // offset: 0x60
+ __IO uint32_t CLM2; // offset: 0x64
+ __IO uint32_t CLM1; // offset: 0x68
+ __IO uint32_t CLM0; // offset: 0x6C
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR;
+ __IO uint32_t PSR;
+ __IO uint32_t CMR;
+ __I uint32_t CNR;
+} LPTMR_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t GENCS;
+ __IO uint32_t DATA;
+ __IO uint32_t TSHD;
+} TSI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t PDOR;
+ __IO uint32_t PSOR;
+ __IO uint32_t PCOR;
+ __IO uint32_t PTOR;
+ __IO uint32_t PDIR;
+ __IO uint32_t PDDR;
+} GPIO_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t C1;
+ __IO uint8_t C2;
+ __IO uint8_t BR;
+ __IO uint8_t S;
+ uint8_t RESERVED0[1];
+ __IO uint8_t D;
+ uint8_t RESERVED1[1];
+ __IO uint8_t M;
+} SPI_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t A1;
+ __IO uint8_t F;
+ __IO uint8_t C1;
+ __IO uint8_t S;
+ __IO uint8_t D;
+ __IO uint8_t C2;
+ __IO uint8_t FLT;
+ __IO uint8_t RA;
+ __IO uint8_t SMB;
+ __IO uint8_t A2;
+ __IO uint8_t SLTH;
+ __IO uint8_t SLTL;
+} I2C_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t BDH;
+ __IO uint8_t BDL;
+ __IO uint8_t C1;
+ __IO uint8_t C2;
+ __IO uint8_t S1;
+ __IO uint8_t S2;
+ __IO uint8_t C3;
+ __IO uint8_t D;
+ __IO uint8_t C4;
+} UART_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t BDH;
+ __IO uint8_t BDL;
+ __IO uint8_t C1;
+ __IO uint8_t C2;
+ __IO uint8_t S1;
+ __IO uint8_t S2;
+ __IO uint8_t C3;
+ __IO uint8_t D;
+ __IO uint8_t MA1;
+ __IO uint8_t MA2;
+ __IO uint8_t C4;
+ __IO uint8_t C5;
+} UARTLP_TypeDef;
+
+/****************************************************************/
+/* Peripheral memory map */
+/****************************************************************/
+#define DMA_BASE ((uint32_t)0x40008100)
+#define DMAMUX_BASE ((uint32_t)0x40021000)
+#define TPM0_BASE ((uint32_t)0x40038000)
+#define TPM1_BASE ((uint32_t)0x40039000)
+#define TPM2_BASE ((uint32_t)0x4003A000)
+#define ADC0_BASE ((uint32_t)0x4003B000)
+#define LPTMR0_BASE ((uint32_t)0x40040000)
+#define TSI0_BASE ((uint32_t)0x40045000)
+#define SIM_BASE ((uint32_t)0x40047000)
+#define PORTA_BASE ((uint32_t)0x40049000)
+#define PORTB_BASE ((uint32_t)0x4004A000)
+#define PORTC_BASE ((uint32_t)0x4004B000)
+#define PORTD_BASE ((uint32_t)0x4004C000)
+#define PORTE_BASE ((uint32_t)0x4004D000)
+#define MCG_BASE ((uint32_t)0x40064000)
+#define OSC0_BASE ((uint32_t)0x40065000)
+#define I2C0_BASE ((uint32_t)0x40066000)
+#define I2C1_BASE ((uint32_t)0x40067000)
+#define UART0_BASE ((uint32_t)0x4006A000)
+#define UART1_BASE ((uint32_t)0x4006B000)
+#define UART2_BASE ((uint32_t)0x4006C000)
+#define SPI0_BASE ((uint32_t)0x40076000)
+#define SPI1_BASE ((uint32_t)0x40077000)
+#define LLWU_BASE ((uint32_t)0x4007C000)
+#define GPIOA_BASE ((uint32_t)0x400FF000)
+#define GPIOB_BASE ((uint32_t)0x400FF040)
+#define GPIOC_BASE ((uint32_t)0x400FF080)
+#define GPIOD_BASE ((uint32_t)0x400FF0C0)
+#define GPIOE_BASE ((uint32_t)0x400FF100)
+
+/****************************************************************/
+/* Peripheral declaration */
+/****************************************************************/
+#define DMA ((DMA_TypeDef *) DMA_BASE)
+#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE)
+#define TPM0 ((TPM_TypeDef *) TPM0_BASE)
+#define TPM1 ((TPM_TypeDef *) TPM1_BASE)
+#define TPM2 ((TPM_TypeDef *) TPM2_BASE)
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
+#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE)
+#define TSI0 ((TSI_TypeDef *) TSI0_BASE)
+#define SIM ((SIM_TypeDef *) SIM_BASE)
+#define LLWU ((LLWU_TypeDef *) LLWU_BASE)
+#define PORTA ((PORT_TypeDef *) PORTA_BASE)
+#define PORTB ((PORT_TypeDef *) PORTB_BASE)
+#define PORTC ((PORT_TypeDef *) PORTC_BASE)
+#define PORTD ((PORT_TypeDef *) PORTD_BASE)
+#define PORTE ((PORT_TypeDef *) PORTE_BASE)
+#define MCG ((MCG_TypeDef *) MCG_BASE)
+#define OSC0 ((OSC_TypeDef *) OSC0_BASE)
+#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define UART0 ((UARTLP_TypeDef *) UART0_BASE)
+#define UART1 ((UART_TypeDef *) UART1_BASE)
+#define UART2 ((UART_TypeDef *) UART2_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+
+/****************************************************************/
+/* Peripheral Registers Bits Definition */
+/****************************************************************/
+
+/****************************************************************/
+/* */
+/* System Integration Module (SIM) */
+/* */
+/****************************************************************/
+/********* Bits definition for SIM_SOPT1 register *************/
+#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */
+#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */
+#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */
+#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */
+#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */
+
+/******* Bits definition for SIM_SOPT1CFG register ************/
+#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */
+#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */
+#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */
+
+/******* Bits definition for SIM_SOPT2 register ************/
+#define SIM_SOPT2_UART0SRC_SHIFT 26 /*!< UART0 clock source select (shift) */
+#define SIM_SOPT2_UART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_UART0SRC_SHIFT)) /*!< UART0 clock source select (mask) */
+#define SIM_SOPT2_UART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_UART0SRC_SHIFT) & SIM_SOPT2_UART0SRC_MASK)) /*!< UART0 clock source select */
+#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */
+#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */
+#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */
+#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */
+#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */
+#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */
+#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */
+#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */
+
+/******* Bits definition for SIM_SCGC4 register ************/
+#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */
+#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */
+#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */
+#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */
+#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */
+#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */
+#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */
+#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */
+#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */
+
+/******* Bits definition for SIM_SCGC5 register ************/
+#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */
+#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */
+#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */
+#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */
+#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */
+#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */
+#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */
+
+/****** Bits definition for SIM_CLKDIV1 register ***********/
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */
+#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */
+#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */
+#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */
+#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */
+
+/****************************************************************/
+/* */
+/* Low-Leakage Wakeup Unit (LLWU) */
+/* */
+/****************************************************************/
+/********** Bits definition for LLWU_PE1 register *************/
+#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */
+#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */
+#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */
+#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */
+#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */
+#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */
+#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */
+#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */
+#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */
+#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */
+#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */
+#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */
+
+/********** Bits definition for LLWU_PE2 register *************/
+#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */
+#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */
+#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */
+#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */
+#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */
+#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */
+#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */
+#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */
+#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */
+#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */
+#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */
+#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */
+
+/********** Bits definition for LLWU_PE3 register *************/
+#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */
+#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */
+#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */
+#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */
+#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */
+#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */
+#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */
+#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */
+#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */
+#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */
+#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */
+#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */
+
+/********** Bits definition for LLWU_PE4 register *************/
+#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */
+#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */
+#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */
+#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */
+#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */
+#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */
+#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */
+#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */
+#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */
+#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */
+#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */
+#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */
+
+/********** Bits definition for LLWU_ME register *************/
+#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */
+#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */
+#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */
+#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */
+#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */
+#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */
+#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */
+#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */
+
+/********** Bits definition for LLWU_F1 register *************/
+#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */
+#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */
+#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */
+#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */
+#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */
+#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */
+#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */
+#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */
+
+/********** Bits definition for LLWU_F2 register *************/
+#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */
+#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */
+#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */
+#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */
+#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */
+#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */
+#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */
+#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */
+
+/********** Bits definition for LLWU_F3 register *************/
+#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */
+#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */
+#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */
+#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */
+#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */
+#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */
+#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */
+#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */
+
+/********** Bits definition for LLWU_FILT1 register *************/
+#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */
+#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */
+#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */
+#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */
+#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */
+#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */
+#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */
+#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */
+#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */
+#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */
+#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */
+
+/********** Bits definition for LLWU_FILT2 register *************/
+#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */
+#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */
+#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */
+#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */
+#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */
+#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */
+#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */
+#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */
+#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */
+#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */
+#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */
+
+/****************************************************************/
+/* */
+/* Port Control and interrupts (PORT) */
+/* */
+/****************************************************************/
+/******** Bits definition for PORTx_PCRn register *************/
+#define PORTx_PCRn_ISR ((uint32_t)0x01000000) /*!< Interrupt Status Flag */
+#define PORTx_PCRn_IRQC ((uint32_t)0x000F0000) /*!< Interrupt Configuration */
+#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */
+#define PORTx_PCRn_MUX_MASK ((uint32_t)0x00000700) /*!< Pin Mux Control (mask) */
+#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */
+#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */
+#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */
+#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */
+#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */
+#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */
+
+/****************************************************************/
+/* */
+/* Oscillator (OSC) */
+/* */
+/****************************************************************/
+/*********** Bits definition for OSC_CR register **************/
+#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */
+#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */
+#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */
+#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */
+#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */
+#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */
+
+/****************************************************************/
+/* */
+/* Direct Memory Access (DMA) */
+/* */
+/****************************************************************/
+/*********** Bits definition for DMA_BCRn register ************/
+#define DMA_DSR_BCRn_CE ((uint32_t)((uint32_t)1 << 30)) /*!< Configuration Error */
+#define DMA_DSR_BCRn_BES ((uint32_t)((uint32_t)1 << 29)) /*!< Bus Error on Source */
+#define DMA_DSR_BCRn_BED ((uint32_t)((uint32_t)1 << 28)) /*!< Bus Error on Destination */
+#define DMA_DSR_BCRn_REQ ((uint32_t)((uint32_t)1 << 26)) /*!< Request */
+#define DMA_DSR_BCRn_BSY ((uint32_t)((uint32_t)1 << 25)) /*!< Busy */
+#define DMA_DSR_BCRn_DONE ((uint32_t)((uint32_t)1 << 24)) /*!< Transactions done */
+#define DMA_DSR_BCRn_BCR_SHIFT 0 /*!< Bytes yet to be transferred for block (shift) */
+#define DMA_DSR_BCRn_BCR_MASK ((uint32_t)((uint32_t)0x00FFFFFF << DMA_DSR_BCRn_BCR_SHIFT)) /*!< Bytes yet to be transferred for block (mask) */
+#define DMA_DSR_BCRn_BCR(x) ((uint32_t)(((uint32_t)(x) << DMA_DSR_BCRn_BCR_SHIFT) & DMA_DSR_BCRn_BCR_MASK)) /*!< Bytes yet to be transferred for block */
+
+/*********** Bits definition for DMA_DCRn register ************/
+#define DMA_DCRn_EINT ((uint32_t)((uint32_t)1 << 31)) /*!< Enable interrupt on completion of transfer */
+#define DMA_DCRn_ERQ ((uint32_t)((uint32_t)1 << 30)) /*!< Enable peripheral request */
+#define DMA_DCRn_CS ((uint32_t)((uint32_t)1 << 29)) /*!< Cycle steal */
+#define DMA_DCRn_AA ((uint32_t)((uint32_t)1 << 28)) /*!< Auto-align */
+#define DMA_DCRn_EADREQ ((uint32_t)((uint32_t)1 << 23)) /*!< Enable asynchronous DMA requests */
+#define DMA_DCRn_SINC ((uint32_t)((uint32_t)1 << 22)) /*!< Source increment */
+#define DMA_DCRn_SSIZE_SHIFT 20 /*!< Source size (shift) */
+#define DMA_DCRn_SSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_SSIZE_SHIFT)) /*!< Source size (mask) */
+#define DMA_DCRn_SSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SSIZE_SHIFT) & DMA_DCRn_SSIZE_MASK)) /*!< Source size */
+#define DMA_DCRn_DINC ((uint32_t)((uint32_t)1 << 19)) /*!< Destination increment */
+#define DMA_DCRn_DSIZE_SHIFT 17 /*!< Destination size (shift) */
+#define DMA_DCRn_DSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_DSIZE_SHIFT)) /*!< Destination size (mask) */
+#define DMA_DCRn_DSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DSIZE_SHIFT) & DMA_DCRn_DSIZE_MASK)) /*!< Destination size */
+#define DMA_DCRn_START ((uint32_t)((uint32_t)1 << 16)) /*!< Start transfer */
+#define DMA_DCRn_SMOD_SHIFT 12 /*!< Source address modulo (shift) */
+#define DMA_DCRn_SMOD_MASK ((uint32_t)((uint32_t)0x0F << DMA_DCRn_SMOD_SHIFT)) /*!< Source address modulo (mask) */
+#define DMA_DCRn_SMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SMOD_SHIFT) & DMA_DCRn_SMOD_MASK)) /*!< Source address modulo */
+#define DMA_DCRn_DMOD_SHIFT 8 /*!< Destination address modulo (shift) */
+#define DMA_DCRn_DMOD_MASK ((uint32_t)0x0F << DMA_DCRn_DMOD_SHIFT) /*!< Destination address modulo (mask) */
+#define DMA_DCRn_DMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DMOD_SHIFT) & DMA_DCRn_DMOD_MASK)) /*!< Destination address modulo */
+#define DMA_DCRn_D_REQ ((uint32_t)((uint32_t)1 << 7)) /*!< Disable request */
+#define DMA_DCRn_LINKCC_SHIFT 4 /*!< Link channel control (shift) */
+#define DMA_DCRn_LINKCC_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LINKCC_SHIFT)) /*!< Link channel control (mask) */
+#define DMA_DCRn_LINKCC(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LINKCC_SHIFT) & DMA_DCRn_LINKCC_MASK)) /*!< Link channel control */
+#define DMA_DCRn_LCH1_SHIFT 2 /*!< Link channel 1 (shift) */
+#define DMA_DCRn_LCH1_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH1_SHIFT)) /*!< Link channel 1 (mask) */
+#define DMA_DCRn_LCH1(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH1_SHIFT) & DMA_DCRn_LCH1_MASK)) /*!< Link channel 1 */
+#define DMA_DCRn_LCH2_SHIFT 0 /*!< Link channel 2 (shift) */
+#define DMA_DCRn_LCH2_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH2_SHIFT)) /*!< Link channel 2 (mask) */
+#define DMA_DCRn_LCH2(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH2_SHIFT) & DMA_DCRn_LCH2_MASK)) /*!< Link channel 2 */
+
+/****************************************************************/
+/* */
+/* Direct Memory Access Multiplexer (DMAMUX) */
+/* */
+/****************************************************************/
+/******** Bits definition for DMAMUX_CHCFGn register **********/
+#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */
+#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */
+#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */
+#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */
+#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */
+
+/****************************************************************/
+/* */
+/* Analog-to-Digital Converter (ADC) */
+/* */
+/****************************************************************/
+/*********** Bits definition for ADCx_SC1n register ***********/
+#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */
+#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */
+#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */
+#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */
+#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */
+#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */
+
+/*********** Bits definition for ADCx_CFG1 register ***********/
+#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */
+#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */
+#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */
+#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */
+#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */
+#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */
+#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */
+#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */
+#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */
+#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */
+#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */
+
+/*********** Bits definition for ADCx_CFG2 register ***********/
+#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */
+#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */
+#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */
+#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */
+#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */
+#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */
+
+/*********** Bits definition for ADCx_SC2 register ***********/
+#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */
+#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */
+#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */
+#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */
+#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */
+#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */
+#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */
+#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */
+#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */
+
+/*********** Bits definition for ADCx_SC3 register ***********/
+#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */
+#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */
+#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */
+#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */
+#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */
+#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */
+#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */
+
+/****************************************************************/
+/* */
+/* Low-Power Timer (LPTMR) */
+/* */
+/****************************************************************/
+/********** Bits definition for LPTMRx_CSR register ***********/
+#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */
+#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */
+#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */
+#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */
+#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */
+#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */
+#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */
+#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */
+#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */
+
+/********** Bits definition for LPTMRx_PSR register ***********/
+#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */
+#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */
+#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */
+#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */
+#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */
+#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */
+#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */
+
+/********** Bits definition for LPTMRx_CMR register ***********/
+#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */
+#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */
+#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */
+
+/********** Bits definition for LPTMRx_CNR register ***********/
+#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */
+#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */
+#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */
+
+/****************************************************************/
+/* */
+/* Touch Sensing Input (TSI) */
+/* */
+/****************************************************************/
+/********** Bits definition for TSIx_GENCS register ***********/
+#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */
+#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */
+#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */
+#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */
+#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */
+#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */
+#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */
+#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */
+#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */
+#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */
+#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */
+#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */
+#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */
+#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */
+#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */
+#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */
+#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */
+#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */
+#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */
+#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */
+#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */
+#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */
+#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */
+#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */
+#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */
+#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */
+#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */
+
+/********** Bits definition for TSIx_DATA register ************/
+#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */
+#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */
+#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */
+#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */
+#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */
+#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */
+#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */
+#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */
+
+/********** Bits definition for TSIx_TSHD register ************/
+#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */
+#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */
+#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */
+#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */
+#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */
+#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */
+
+/****************************************************************/
+/* */
+/* Multipurpose Clock Generator (MCG) */
+/* */
+/****************************************************************/
+/*********** Bits definition for MCG_C1 register **************/
+#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */
+#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */
+#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */
+#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */
+#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */
+#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */
+#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */
+#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */
+#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */
+#define MCG_C1_IREFS ((uint8_t)((uint8_t)1 << 2)) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */
+#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */
+#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */
+
+/*********** Bits definition for MCG_C2 register **************/
+#define MCG_C2_LOCRE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Clock Reset Enable */
+#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */
+#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */
+#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */
+#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */
+#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */
+#define MCG_C2_LP ((uint8_t)((uint8_t)1 << 1)) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */
+#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */
+
+/*********** Bits definition for MCG_C3 register **************/
+#define MCG_C3_SCTRIM_SHIFT 0 /*!< Slow Internal Reference Clock Trim Setting (shift) */
+#define MCG_C3_SCTRIM_MASK ((uint8_t)((uint8_t)0xFF << MCG_C3_SCTRIM_SHIFT)) /*!< Slow Internal Reference Clock Trim Setting (mask) */
+#define MCG_C3_SCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C3_SCTRIM_SHIFT) & MCG_C3_SCTRIM_MASK)) /*!< Slow Internal Reference Clock Trim Setting */
+
+/*********** Bits definition for MCG_C4 register **************/
+#define MCG_C4_DMX32 ((uint8_t)((uint8_t)1 << 7)) /*!< DCO Maximum Frequency with 32.768 kHz Reference */
+#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */
+#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */
+#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */
+#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */
+#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0x0F << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */
+#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */
+#define MCG_C4_SCFTRIM ((uint8_t)((uint8_t)1 << 0)) /*!< Slow Internal Reference Clock Fine Trim */
+
+/*********** Bits definition for MCG_C5 register **************/
+#define MCG_C5_PLLCLKEN0 ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Clock Enable */
+#define MCG_C5_PLLSTEN0 ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Stop Enable */
+#define MCG_C5_PRDIV0_SHIFT 0 /*!< PLL External Reference Divider (shift) */
+#define MCG_C5_PRDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C5_PRDIV0_SHIFT)) /*!< PLL External Reference Divider (mask) */
+#define MCG_C5_PRDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C5_PRDIV0_SHIFT) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */
+
+/*********** Bits definition for MCG_C6 register **************/
+#define MCG_C6_LOLIE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Interrupt Enable */
+#define MCG_C6_PLLS ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Select */
+#define MCG_C6_CME0 ((uint8_t)((uint8_t)1 << 5)) /*!< Clock Monitor Enable */
+#define MCG_C6_VDIV0_SHIFT 0 /*!< VCO 0 Divider (shift) */
+#define MCG_C6_VDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C6_VDIV0_SHIFT)) /*!< VCO 0 Divider (mask) */
+#define MCG_C6_VDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C6_VDIV0_SHIFT) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */
+
+/************ Bits definition for MCG_S register **************/
+#define MCG_S_LOLS ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Status */
+#define MCG_S_LOCK0 ((uint8_t)((uint8_t)1 << 6)) /*!< Lock Status */
+#define MCG_S_PLLST ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Select Status */
+#define MCG_S_IREFST ((uint8_t)((uint8_t)1 << 4)) /*!< Internal Reference Status */
+#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */
+#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */
+#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */
+#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */
+#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */
+#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */
+#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */
+#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */
+#define MCG_S_IRCST ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Status */
+
+/************ Bits definition for MCG_SC register **************/
+#define MCG_SC_ATME ((uint8_t)((uint8_t)1 << 7)) /*!< Automatic Trim Machine Enable */
+#define MCG_SC_ATMS ((uint8_t)((uint8_t)1 << 6)) /*!< Automatic Trim Machine Select */
+#define MCG_SC_ATMF ((uint8_t)((uint8_t)1 << 5)) /*!< Automatic Trim Machine Fail Flag */
+#define MCG_SC_FLTPRSRV ((uint8_t)((uint8_t)1 << 4) /*!< FLL Filter Preserve Enable */
+#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */
+#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */
+#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */
+#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */
+#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */
+#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */
+#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */
+#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */
+#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */
+#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */
+#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */
+#define MCG_SC_LOCS0 ((uint8_t)((uint8_t)1 << 0) /*!< OSC0 Loss of Clock Status */
+
+/*********** Bits definition for MCG_ATCVH register ************/
+#define MCG_ATCVH_ATCVH_SHIFT 0 /*!< MCG Auto Trim Compare Value High Register (shift) */
+#define MCG_ATCVH_ATCVH_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVH_ATCVH_SHIFT)) /*!< MCG Auto Trim Compare Value High Register (mask) */
+#define MCG_ATCVH_ATCVH(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVH_ATCVH_SHIFT) & MCG_ATCVH_ATCVH_MASK)) /*!< MCG Auto Trim Compare Value High Register */
+
+/*********** Bits definition for MCG_ATCVL register ************/
+#define MCG_ATCVL_ATCVL_SHIFT 0 /*!< MCG Auto Trim Compare Value Low Register (shift) */
+#define MCG_ATCVL_ATCVL_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVL_ATCVL_SHIFT)) /*!< MCG Auto Trim Compare Value Low Register (mask) */
+#define MCG_ATCVL_ATCVL(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVL_ATCVL_SHIFT) & MCG_ATCVL_ATCVL_MASK)) /*!< MCG Auto Trim Compare Value Low Register */
+
+/************ Bits definition for MCG_C7 register **************/
+/* All MCG_C7 bits are reserved on the KL25Z. */
+
+/************ Bits definition for MCG_C8 register **************/
+#define MCG_C8_LOLRE ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Loss of Lock Reset Enable */
+
+/************ Bits definition for MCG_C9 register **************/
+/* All MCG_C9 bits are reserved on the KL25Z. */
+
+/************ Bits definition for MCG_C10 register *************/
+/* All MCG_C10 bits are reserved on the KL25Z. */
+
+
+/****************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/****************************************************************/
+/*********** Bits definition for SPIx_C1 register *************/
+#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */
+#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */
+#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */
+#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */
+#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */
+#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */
+#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */
+#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */
+
+/*********** Bits definition for SPIx_C2 register *************/
+#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */
+#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */
+#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */
+#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */
+#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */
+#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */
+#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */
+
+/*********** Bits definition for SPIx_BR register *************/
+#define SPIx_BR_SPPR ((uint8_t)0x70) /*!< SPI Baud rate Prescaler Divisor */
+#define SPIx_BR_SPR ((uint8_t)0x0F) /*!< SPI Baud rate Divisor */
+
+#define SPIx_BR_SPPR_SHIFT 4
+
+/*********** Bits definition for SPIx_S register **************/
+#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */
+#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */
+#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */
+#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */
+
+/*********** Bits definition for SPIx_D register **************/
+#define SPIx_D_DATA ((uint8_t)0xFF) /*!< Data */
+
+/*********** Bits definition for SPIx_M register **************/
+#define SPIx_M_DATA ((uint8_t)0xFF) /*!< SPI HW Compare value for Match */
+
+/****************************************************************/
+/* */
+/* Inter-Integrated Circuit (I2C) */
+/* */
+/****************************************************************/
+/*********** Bits definition for I2Cx_A1 register *************/
+#define I2Cx_A1_AD ((uint8_t)0xFE) /*!< Address [7:1] */
+
+#define I2Cx_A1_AD_SHIT 1
+
+/*********** Bits definition for I2Cx_F register **************/
+#define I2Cx_F_MULT ((uint8_t)0xC0) /*!< Multiplier factor */
+#define I2Cx_F_ICR ((uint8_t)0x3F) /*!< Clock rate */
+
+#define I2Cx_F_MULT_SHIFT 5
+
+/*********** Bits definition for I2Cx_C1 register *************/
+#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */
+#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */
+#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */
+#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */
+#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */
+#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */
+#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */
+#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */
+
+/*********** Bits definition for I2Cx_S register **************/
+#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */
+#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */
+#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */
+#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */
+#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */
+#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */
+#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */
+#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */
+
+/*********** Bits definition for I2Cx_D register **************/
+#define I2Cx_D_DATA ((uint8_t)0xFF) /*!< Data */
+
+/*********** Bits definition for I2Cx_C2 register *************/
+#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */
+#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */
+#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */
+#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */
+#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */
+#define I2Cx_C2_AD_10_8 ((uint8_t)0x03) /*!< Slave Address [10:8] */
+
+/*********** Bits definition for I2Cx_FLT register ************/
+#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */
+#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */
+#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */
+#define I2Cx_FLT_FLT ((uint8_t)0x1F) /*!< I2C Programmable Filter Factor */
+
+/*********** Bits definition for I2Cx_RA register *************/
+#define I2Cx_RA_RAD ((uint8_t)0xFE) /*!< Range Slave Address */
+
+#define I2Cx_RA_RAD_SHIFT 1
+
+/*********** Bits definition for I2Cx_SMB register ************/
+#define I2Cx_SMB_FACK ((uint8_t)0x00) /*!< Fast NACK/ACK Enable */
+#define I2Cx_SMB_ALERTEN ((uint8_t)0x00) /*!< SMBus Alert Response Address Enable */
+#define I2Cx_SMB_SIICAEN ((uint8_t)0x00) /*!< Second I2C Address Enable */
+#define I2Cx_SMB_TCKSEL ((uint8_t)0x00) /*!< Timeout Counter Clock Select */
+#define I2Cx_SMB_SLTF ((uint8_t)0x00) /*!< SCL Low Timeout Flag */
+#define I2Cx_SMB_SHTF1 ((uint8_t)0x00) /*!< SCL High Timeout Flag 1 */
+#define I2Cx_SMB_SHTF2 ((uint8_t)0x00) /*!< SCL High Timeout Flag 2 */
+#define I2Cx_SMB_SHTF2IE ((uint8_t)0x00) /*!< SHTF2 Interrupt Enable */
+
+/*********** Bits definition for I2Cx_A2 register *************/
+#define I2Cx_A2_SAD ((uint8_t)0xFE) /*!< SMBus Address */
+
+#define I2Cx_A2_SAD_SHIFT 1
+
+/*********** Bits definition for I2Cx_SLTH register ***********/
+#define I2Cx_SLTH_SSLT ((uint8_t)0xFF) /*!< MSB of SCL low timeout value */
+
+/*********** Bits definition for I2Cx_SLTL register ***********/
+#define I2Cx_SLTL_SSLT ((uint8_t)0xFF) /*!< LSB of SCL low timeout value */
+
+/****************************************************************/
+/* */
+/* Universal Asynchronous Receiver/Transmitter (UART) */
+/* */
+/****************************************************************/
+/********* Bits definition for UARTx_BDH register *************/
+#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */
+#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */
+#define UARTx_BDH_SBNS ((uint8_t)0x20) /*!< Stop Bit Number Select */
+#define UARTx_BDH_SBR ((uint8_t)0x1F) /*!< Baud Rate Modulo Divisor */
+
+/********* Bits definition for UARTx_BDL register *************/
+#define UARTx_BDL_SBR ((uint8_t)0xFF) /*!< Baud Rate Modulo Divisor */
+
+/********* Bits definition for UARTx_C1 register **************/
+#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */
+#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */
+#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */
+#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */
+#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */
+#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */
+#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */
+#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */
+#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */
+
+/********* Bits definition for UARTx_C2 register **************/
+#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */
+#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */
+#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */
+#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */
+#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */
+#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */
+#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */
+#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */
+
+/********* Bits definition for UARTx_S1 register **************/
+#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */
+#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */
+#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */
+#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */
+#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */
+#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */
+#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */
+#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */
+
+/********* Bits definition for UARTx_S2 register **************/
+#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */
+#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */
+#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */
+#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */
+#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */
+#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */
+#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */
+#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */
+
+/********* Bits definition for UARTx_C3 register **************/
+#define UARTx_C3_R8T9 ((uint8_t)0x80) /*!< Receive Bit 8 / Transmit Bit 9 */
+#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */
+#define UARTx_C3_R9T8 ((uint8_t)0x40) /*!< Receive Bit 9 / Transmit Bit 8 */
+#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */
+#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */
+#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */
+#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */
+#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */
+#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */
+#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */
+
+/********* Bits definition for UARTx_D register ***************/
+#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */
+#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */
+#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */
+#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */
+#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */
+#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */
+#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */
+#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */
+
+/********* Bits definition for UARTx_MA1 register *************/
+#define UARTx_MA1_MA ((uint8_t)0xFF) /*!< Match Address */
+
+/********* Bits definition for UARTx_MA2 register *************/
+#define UARTx_MA2_MA ((uint8_t)0xFF) /*!< Match Address */
+
+/********* Bits definition for UARTx_C4 register **************/
+#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */
+#define UARTx_C4_TDMAS ((uint8_t)0x80) /*!< Transmitter DMA Select */
+#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */
+#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */
+#define UARTx_C4_RDMAS ((uint8_t)0x80) /*!< Receiver Full DMA Select */
+#define UARTx_C4_OSR ((uint8_t)0x1F) /*!< Over Sampling Ratio */
+
+/********* Bits definition for UARTx_C5 register **************/
+#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */
+#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */
+#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */
+#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */
+
+#endif
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
new file mode 100644
index 000000000..6ae313515
--- /dev/null
+++ b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
@@ -0,0 +1,128 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ .port = IOPORT1, // PORTA
+ .pads = {
+ /* PTA0*/ PAL_MODE_ALTERNATIVE_7, /* PTA1*/ PAL_MODE_ALTERNATIVE_2, /* PTA2*/ PAL_MODE_ALTERNATIVE_2,
+ /* PTA3*/ PAL_MODE_ALTERNATIVE_7, /* PTA4*/ PAL_MODE_INPUT_ANALOG, /* PTA5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTA6*/ PAL_MODE_UNCONNECTED, /* PTA7*/ PAL_MODE_UNCONNECTED, /* PTA8*/ PAL_MODE_UNCONNECTED,
+ /* PTA9*/ PAL_MODE_UNCONNECTED, /*PTA10*/ PAL_MODE_UNCONNECTED, /*PTA11*/ PAL_MODE_UNCONNECTED,
+ /*PTA12*/ PAL_MODE_INPUT_ANALOG, /*PTA13*/ PAL_MODE_INPUT_ANALOG, /*PTA14*/ PAL_MODE_INPUT_ANALOG,
+ /*PTA15*/ PAL_MODE_INPUT_ANALOG, /*PTA16*/ PAL_MODE_INPUT_ANALOG, /*PTA17*/ PAL_MODE_INPUT_ANALOG,
+ /*PTA18*/ PAL_MODE_INPUT_ANALOG, /*PTA19*/ PAL_MODE_INPUT_ANALOG, /*PTA20*/ PAL_MODE_ALTERNATIVE_7,
+ /*PTA21*/ PAL_MODE_UNCONNECTED, /*PTA22*/ PAL_MODE_UNCONNECTED, /*PTA23*/ PAL_MODE_UNCONNECTED,
+ /*PTA24*/ PAL_MODE_UNCONNECTED, /*PTA25*/ PAL_MODE_UNCONNECTED, /*PTA26*/ PAL_MODE_UNCONNECTED,
+ /*PTA27*/ PAL_MODE_UNCONNECTED, /*PTA28*/ PAL_MODE_UNCONNECTED, /*PTA29*/ PAL_MODE_UNCONNECTED,
+ /*PTA30*/ PAL_MODE_UNCONNECTED, /*PTA31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT2, // PORTB
+ .pads = {
+ /* PTB0*/ PAL_MODE_INPUT_ANALOG, /* PTB1*/ PAL_MODE_INPUT_ANALOG, /* PTB2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTB3*/ PAL_MODE_INPUT_ANALOG, /* PTB4*/ PAL_MODE_UNCONNECTED, /* PTB5*/ PAL_MODE_UNCONNECTED,
+ /* PTB6*/ PAL_MODE_UNCONNECTED, /* PTB7*/ PAL_MODE_UNCONNECTED, /* PTB8*/ PAL_MODE_INPUT_ANALOG,
+ /* PTB9*/ PAL_MODE_INPUT_ANALOG, /*PTB10*/ PAL_MODE_INPUT_ANALOG, /*PTB11*/ PAL_MODE_INPUT_ANALOG,
+ /*PTB12*/ PAL_MODE_UNCONNECTED, /*PTB13*/ PAL_MODE_UNCONNECTED, /*PTB14*/ PAL_MODE_UNCONNECTED,
+ /*PTB15*/ PAL_MODE_UNCONNECTED, /*PTB16*/ PAL_MODE_INPUT_ANALOG, /*PTB17*/ PAL_MODE_INPUT_ANALOG,
+ /*PTB18*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB19*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB20*/ PAL_MODE_UNCONNECTED,
+ /*PTB21*/ PAL_MODE_UNCONNECTED, /*PTB22*/ PAL_MODE_UNCONNECTED, /*PTB23*/ PAL_MODE_UNCONNECTED,
+ /*PTB24*/ PAL_MODE_UNCONNECTED, /*PTB25*/ PAL_MODE_UNCONNECTED, /*PTB26*/ PAL_MODE_UNCONNECTED,
+ /*PTB27*/ PAL_MODE_UNCONNECTED, /*PTB28*/ PAL_MODE_UNCONNECTED, /*PTB29*/ PAL_MODE_UNCONNECTED,
+ /*PTB30*/ PAL_MODE_UNCONNECTED, /*PTB31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT3, // PORTC
+ .pads = {
+ /* PTC0*/ PAL_MODE_INPUT_ANALOG, /* PTC1*/ PAL_MODE_INPUT_ANALOG, /* PTC2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTC3*/ PAL_MODE_INPUT_ANALOG, /* PTC4*/ PAL_MODE_INPUT_ANALOG, /* PTC5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTC6*/ PAL_MODE_INPUT_ANALOG, /* PTC7*/ PAL_MODE_INPUT_ANALOG, /* PTC8*/ PAL_MODE_INPUT_ANALOG,
+ /* PTC9*/ PAL_MODE_INPUT_ANALOG, /*PTC10*/ PAL_MODE_INPUT_ANALOG, /*PTC11*/ PAL_MODE_INPUT_ANALOG,
+ /*PTC12*/ PAL_MODE_INPUT_ANALOG, /*PTC13*/ PAL_MODE_INPUT_ANALOG, /*PTC14*/ PAL_MODE_INPUT_ANALOG,
+ /*PTC15*/ PAL_MODE_INPUT_ANALOG, /*PTC16*/ PAL_MODE_INPUT_ANALOG, /*PTC17*/ PAL_MODE_INPUT_ANALOG,
+ /*PTC18*/ PAL_MODE_UNCONNECTED, /*PTC19*/ PAL_MODE_UNCONNECTED, /*PTC20*/ PAL_MODE_UNCONNECTED,
+ /*PTC21*/ PAL_MODE_UNCONNECTED, /*PTC22*/ PAL_MODE_UNCONNECTED, /*PTC23*/ PAL_MODE_UNCONNECTED,
+ /*PTC24*/ PAL_MODE_UNCONNECTED, /*PTC25*/ PAL_MODE_UNCONNECTED, /*PTC26*/ PAL_MODE_UNCONNECTED,
+ /*PTC27*/ PAL_MODE_UNCONNECTED, /*PTC28*/ PAL_MODE_UNCONNECTED, /*PTC29*/ PAL_MODE_UNCONNECTED,
+ /*PTC30*/ PAL_MODE_UNCONNECTED, /*PTC31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT4, // PORTD
+ .pads = {
+ /* PTD0*/ PAL_MODE_INPUT_ANALOG, /* PTD1*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTD2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTD3*/ PAL_MODE_INPUT_ANALOG, /* PTD4*/ PAL_MODE_INPUT_ANALOG, /* PTD5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTD6*/ PAL_MODE_INPUT_ANALOG, /* PTD7*/ PAL_MODE_INPUT_ANALOG, /* PTD8*/ PAL_MODE_INPUT_ANALOG,
+ /* PTD9*/ PAL_MODE_UNCONNECTED, /*PTD10*/ PAL_MODE_UNCONNECTED, /*PTD11*/ PAL_MODE_UNCONNECTED,
+ /*PTD12*/ PAL_MODE_UNCONNECTED, /*PTD13*/ PAL_MODE_UNCONNECTED, /*PTD14*/ PAL_MODE_UNCONNECTED,
+ /*PTD15*/ PAL_MODE_UNCONNECTED, /*PTD16*/ PAL_MODE_UNCONNECTED, /*PTD17*/ PAL_MODE_UNCONNECTED,
+ /*PTD18*/ PAL_MODE_UNCONNECTED, /*PTD19*/ PAL_MODE_UNCONNECTED, /*PTD20*/ PAL_MODE_UNCONNECTED,
+ /*PTD21*/ PAL_MODE_UNCONNECTED, /*PTD22*/ PAL_MODE_UNCONNECTED, /*PTD23*/ PAL_MODE_UNCONNECTED,
+ /*PTD24*/ PAL_MODE_UNCONNECTED, /*PTD25*/ PAL_MODE_UNCONNECTED, /*PTD26*/ PAL_MODE_UNCONNECTED,
+ /*PTD27*/ PAL_MODE_UNCONNECTED, /*PTD28*/ PAL_MODE_UNCONNECTED, /*PTD29*/ PAL_MODE_UNCONNECTED,
+ /*PTD30*/ PAL_MODE_UNCONNECTED, /*PTD31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT5, // PORTE
+ .pads = {
+ /* PTE0*/ PAL_MODE_INPUT_ANALOG, /* PTE1*/ PAL_MODE_INPUT_ANALOG, /* PTE2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTE3*/ PAL_MODE_INPUT_ANALOG, /* PTE4*/ PAL_MODE_INPUT_ANALOG, /* PTE5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTE6*/ PAL_MODE_UNCONNECTED, /* PTE7*/ PAL_MODE_UNCONNECTED, /* PTE8*/ PAL_MODE_UNCONNECTED,
+ /* PTE9*/ PAL_MODE_UNCONNECTED, /*PTE10*/ PAL_MODE_UNCONNECTED, /*PTE11*/ PAL_MODE_UNCONNECTED,
+ /*PTE12*/ PAL_MODE_UNCONNECTED, /*PTE13*/ PAL_MODE_UNCONNECTED, /*PTE14*/ PAL_MODE_UNCONNECTED,
+ /*PTE15*/ PAL_MODE_UNCONNECTED, /*PTE16*/ PAL_MODE_UNCONNECTED, /*PTE17*/ PAL_MODE_UNCONNECTED,
+ /*PTE18*/ PAL_MODE_UNCONNECTED, /*PTE19*/ PAL_MODE_UNCONNECTED, /*PTE20*/ PAL_MODE_INPUT_ANALOG,
+ /*PTE21*/ PAL_MODE_INPUT_ANALOG, /*PTE22*/ PAL_MODE_INPUT_ANALOG, /*PTE23*/ PAL_MODE_INPUT_ANALOG,
+ /*PTE24*/ PAL_MODE_ALTERNATIVE_5, /*PTE25*/ PAL_MODE_ALTERNATIVE_5, /*PTE26*/ PAL_MODE_UNCONNECTED,
+ /*PTE27*/ PAL_MODE_UNCONNECTED, /*PTE28*/ PAL_MODE_UNCONNECTED, /*PTE29*/ PAL_MODE_INPUT_ANALOG,
+ /*PTE30*/ PAL_MODE_INPUT_ANALOG, /*PTE31*/ PAL_MODE_INPUT_ANALOG,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ kl2x_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h
new file mode 100644
index 000000000..c1ec60aea
--- /dev/null
+++ b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h
@@ -0,0 +1,44 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Freescale Freedom KL25Z board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_FREESCALE_FREEDOM_KL25Z
+#define BOARD_NAME "Freescale Freedom KL25Z"
+
+/* External 8 MHz crystal with PLL for 48 MHz core/system clock. */
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
new file mode 100644
index 000000000..9ae0f5eeb
--- /dev/null
+++ b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_KL25Z
diff --git a/os/hal/ports/KINETIS/KL2x/hal_lld.c b/os/hal/ports/KINETIS/KL2x/hal_lld.c
new file mode 100644
index 000000000..eabadc9e0
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/hal_lld.c
@@ -0,0 +1,282 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/hal_lld.c
+ * @brief Kinetis KL2x HAL Driver subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+}
+
+/**
+ * @brief KL2x clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void kl2x_clock_init(void) {
+#if !KINETIS_NO_INIT
+ /* Disable COP watchdog */
+ SIM->COPC = 0;
+
+ /* Enable PORTA */
+ SIM->SCGC5 |= SIM_SCGC5_PORTA;
+
+ /* --- MCG mode: FEI (default out of reset) ---
+ f_MCGOUTCLK = f_int * F
+ F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits.
+ Typical f_MCGOUTCLK = 21 MHz immediately after reset.
+ C4[DMX32]=0 and C4[DRST_DRS]=00 => FLL factor=640.
+ C3[SCTRIM] and C4[SCFTRIM] factory trim values apply to f_int. */
+
+ /* System oscillator drives 32 kHz clock (OSC32KSEL=0) */
+ SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
+
+ #if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+ /* This is the default mode at reset. */
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock) */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 24 MHz */
+ SIM_CLKDIV1_OUTDIV4(0); /* OUTDIV4 = divide-by-1 => 24 MHz */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEE
+ /*
+ * FLL Enabled External (FEE) MCG Mode
+ * 24 MHz core, 12 MHz bus - using 32.768 kHz crystal with FLL.
+ * f_MCGOUTCLK = (f_ext / FLL_R) * F
+ * = (32.768 kHz ) *
+ * FLL_R is the reference divider selected by C1[FRDIV]
+ * F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32].
+ *
+ * Then the core/system and bus/flash clocks are divided:
+ * f_SYS = f_MCGOUTCLK / OUTDIV1 = 48 MHz / 1 = 48 MHz
+ * f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = MHz / 4 = 24 MHz
+ */
+
+ SIM->SOPT2 =
+ SIM_SOPT2_TPMSRC(1); /* MCGFLLCLK clock or MCGPLLCLK/2 */
+ /* PLLFLLSEL=0 -> MCGFLLCLK */
+
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock) */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(KINETIS_MCG_FLL_OUTDIV1 - 1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_MCG_FLL_OUTDIV4 - 1);
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
+ PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+
+ OSC0->CR = 0;
+
+ /* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
+ /* To change from FEI mode to FEE mode: */
+ /* (1) Select the external clock source in C2 register.
+ Use low-power OSC mode (HGO0=0) which enables internal feedback
+ resistor, for 32.768 kHz crystal configuration. */
+ MCG->C2 =
+ MCG_C2_RANGE0(0) | /* low frequency range (<= 40 kHz) */
+ MCG_C2_EREFS0; /* external reference (using a crystal) */
+ /* (2) Write to C1 to select the clock mode. */
+ MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
+ MCG_C1_CLKS_FLLPLL | /* Use FLL for system clock, MCGCLKOUT. */
+ MCG_C1_FRDIV(0); /* Don't divide 32kHz ERCLK FLL reference. */
+ MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
+
+ /* Loop until S[OSCINIT0] is 1, indicating the
+ crystal selected by C2[EREFS0] has been initialized. */
+ while ((MCG->S & MCG_S_OSCINIT0) == 0)
+ ;
+ /* Loop until S[IREFST] is 0, indicating the
+ external reference is the current reference clock source. */
+ while ((MCG->S & MCG_S_IREFST) != 0)
+ ; /* Wait until external reference clock is FLL reference. */
+ /* (1)(e) Loop until S[CLKST] indicates FLL feeds MCGOUTCLK. */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_FLL)
+ ; /* Wait until FLL has been selected. */
+
+ /* --- MCG mode: FEE --- */
+ /* Set frequency range for DCO output (MCGFLLCLK). */
+ MCG->C4 = (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0) |
+ MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS);
+
+ /* Wait for the FLL lock time; t[fll_acquire][max] = 1 ms */
+ /* TODO - not implemented - is it required? Freescale example code
+ seems to omit it. */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+ /*
+ * PLL Enabled External (PEE) MCG Mode
+ * 48 MHz core, 24 MHz bus - using 8 MHz crystal with PLL.
+ * f_MCGOUTCLK = (OSCCLK / PLL_R) * M
+ * = 8 MHz / 2 * 24 = 96 MHz
+ * PLL_R is the reference divider selected by C5[PRDIV0]
+ * M is the multiplier selected by C6[VDIV0]
+ *
+ * Then the core/system and bus/flash clocks are divided:
+ * f_SYS = f_MCGOUTCLK / OUTDIV1 = 96 MHz / 2 = 48 MHz
+ * f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = 96 MHz / 4 = 24 MHz
+ */
+
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock) */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 48 MHz */
+ SIM_CLKDIV1_OUTDIV4(1); /* OUTDIV4 = divide-by-2 => 24 MHz */
+
+ SIM->SOPT2 =
+ SIM_SOPT2_TPMSRC(1) | /* MCGFLLCLK clock or MCGPLLCLK/2 */
+ SIM_SOPT2_PLLFLLSEL; /* PLLFLLSEL=MCGPLLCLK/2 */
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
+ PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+
+ OSC0->CR = 0;
+
+ /* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
+ /* To change from FEI mode to FBE mode: */
+ /* (1) Select the external clock source in C2 register.
+ Use low-power OSC mode (HGO0=0) which enables internal feedback
+ resistor since FRDM-KL25Z has feedback resistor R25 unpopulated.
+ Use high-gain mode by setting C2[HGO0] instead if external
+ feedback resistor Rf is installed. */
+ MCG->C2 =
+ MCG_C2_RANGE0(2) | /* very high frequency range */
+ MCG_C2_EREFS0; /* external reference (using a crystal) */
+ /* (2) Write to C1 to select the clock mode. */
+ MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
+ MCG_C1_CLKS_ERCLK | /* Use ERCLK for system clock, MCGCLKOUT. */
+ MCG_C1_FRDIV(3); /* Divide ERCLK / 256 for FLL reference. */
+ /* Note: FLL reference frequency must be 31.25 kHz to 39.0625 kHz.
+ 8 MHz / 256 = 31.25 kHz. */
+ MCG->C4 &= ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_MASK);
+ MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
+
+ /* (3) Once configuration is set, wait for MCG mode change. */
+
+ /* From KL25P80M48SF0RM section 24.5.31: */
+ /* (1)(c) Loop until S[OSCINIT0] is 1, indicating the
+ crystal selected by C2[EREFS0] has been initialized. */
+ while ((MCG->S & MCG_S_OSCINIT0) == 0)
+ ;
+ /* (1)(d) Loop until S[IREFST] is 0, indicating the
+ external reference is the current reference clock source. */
+ while ((MCG->S & MCG_S_IREFST) != 0)
+ ; /* Wait until external reference clock is FLL reference. */
+ /* (1)(e) Loop until S[CLKST] is 2'b10, indicating
+ the external reference clock is selected to feed MCGOUTCLK. */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_ERCLK)
+ ; /* Wait until external reference clock has been selected. */
+
+ /* --- MCG mode: FBE (FLL bypassed, external crystal) ---
+ Now the MCG is in FBE mode.
+ Although the FLL is bypassed, it is still on. */
+
+ /* (2) Then configure C5[PRDIV0] to generate the
+ correct PLL reference frequency. */
+ MCG->C5 = MCG_C5_PRDIV0(1); /* PLL External Reference Divide by 2 */
+ /* (3) Then from FBE transition to PBE mode. */
+ /* (3)(b) C6[PLLS]=1 to select PLL. */
+ /* (3)(b) C6[VDIV0]=5'b0000 (x24) 2 MHz * 24 = 48 MHz. */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+ /* (3)(d) Loop until S[PLLST], indicating PLL
+ is the PLLS clock source. */
+ while ((MCG->S & MCG_S_PLLST) == 0)
+ ; /* wait until PLL is the PLLS clock source. */
+ /* (3)(e) Loop until S[LOCK0] is set, indicating the PLL has acquired lock. */
+ /* PLL selected as MCG source. VDIV0=00000 (Multiply=24). */
+ while ((MCG->S & MCG_S_LOCK0) == 0)
+ ; /* wait until PLL locked */
+
+ /* --- MCG mode: PBE (PLL bypassed, external crystal) --- */
+
+ /* (4) Transition from PBE mode to PEE mode. */
+ /* (4)(a) C1[CLKS] = 2'b00 to select PLL output as system clock source. */
+ // Switch to PEE mode
+ // Select PLL output (CLKS=0)
+ // FLL external reference divider (FRDIV=3)
+ // External reference clock for FLL (IREFS=0)
+ MCG->C1 = MCG_C1_CLKS(0) |
+ MCG_C1_FRDIV(3);
+ /* (4)(b) Loop until S[CLKST] are 2'b11, indicating the PLL output is selected for MCGOUTCLK. */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL)
+ ; /* wait until clock switched to PLL output */
+
+ /* --- MCG mode: PEE (PLL enabled, external crystal) --- */
+
+#else /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
+
+#endif /* !KINETIS_NO_INIT */
+}
+
+/**
+ * @brief Platform early initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function is meant to be invoked early during the system
+ * initialization, it is usually invoked from the file
+ * @p board.c.
+ *
+ * @special
+ */
+void platform_early_init(void) {
+
+}
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/hal_lld.h b/os/hal/ports/KINETIS/KL2x/hal_lld.h
new file mode 100644
index 000000000..a55283c8f
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/hal_lld.h
@@ -0,0 +1,268 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/hal_lld.h
+ * @brief Kinetis KL2x HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "kl25z.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "Kinetis"
+/** @} */
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 48000000
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 24000000
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
+#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
+/** @} */
+
+#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
+#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
+#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
+#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
+#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
+#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
+#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
+#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the MCG/system clock initialization in the HAL.
+ */
+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
+#define KINETIS_NO_INIT FALSE
+#endif
+
+/**
+ * @brief MCG mode selection.
+ */
+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#endif
+
+/**
+ * @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
+ * @note The allowed range is 1...16.
+ * @note The default value is calculated for a 48 MHz system clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_MCG_FLL_OUTDIV1) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_OUTDIV1 2
+#endif
+
+/**
+ * @brief Additional clock divider bus/flash clocks (OUTDIV4).
+ * @note The allowed range is 1...8.
+ * @note This divider is on top of the OUTDIV1 divider.
+ * @note The default value is calculated for 24 MHz bus/flash clocks
+ * from a 96 MHz PLL output and 48 MHz core/system clock.
+ */
+#if !defined(KINETIS_MCG_FLL_OUTDIV4) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_OUTDIV4 2
+#endif
+
+/**
+ * @brief FLL DCO tuning enable for 32.768 kHz reference.
+ * @note Set to 1 for fine-tuning DCO for maximum frequency with
+ * a 32.768 kHz reference.
+ * @note The default value is for a 32.768 kHz external crystal.
+ */
+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DMX32 1
+#endif
+
+/**
+ * @brief FLL DCO range selection.
+ * @note The allowed range is 0...3.
+ * @note The default value is calculated for 48 MHz FLL output
+ * from a 32.768 kHz external crystal.
+ * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
+ *
+ */
+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DRS 2
+#endif
+
+/**
+ * @brief MCU system/core clock frequency.
+ */
+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/**
+ * @brief MCU bus/flash clock frequency.
+ */
+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#endif
+
+/**
+ * @brief UART0 clock frequency.
+ * @note The default value is based on 96 MHz PLL/2 source.
+ * If you use a different source, such as the FLL,
+ * you must set this properly.
+ */
+#if !defined(KINETIS_UART0_CLOCK_FREQ) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_FREQ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+/**
+ * @brief UART0 clock source.
+ * @note The default value is to use PLL/2 or FLL source.
+ */
+#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_SRC 1
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SYSCLK_FREQUENCY)
+#error KINETIS_SYSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
+#error KINETIS_SYSCLK_FREQUENCY out of range
+#endif
+
+#if !defined(KINETIS_BUSCLK_FREQUENCY)
+#error KINETIS_BUSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
+#error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if !(defined(KINETIS_MCG_FLL_OUTDIV1) && \
+ KINETIS_MCG_FLL_OUTDIV1 >= 1 && KINETIS_MCG_FLL_OUTDIV1 <= 16)
+#error KINETIS_MCG_FLL_OUTDIV1 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_MCG_FLL_OUTDIV4) && \
+ KINETIS_MCG_FLL_OUTDIV4 >= 1 && KINETIS_MCG_FLL_OUTDIV4 <= 8)
+#error KINETIS_MCG_FLL_OUTDIV4 must be 1 through 8
+#endif
+
+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
+#endif
+
+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * DWT_CYCCNT register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_value() 0
+
+/**
+ * @brief Realtime counter frequency.
+ * @note The DWT_CYCCNT register is incremented directly by the system
+ * clock so this function returns STM32_HCLK.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() 0
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void kl2x_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/kl25z.h b/os/hal/ports/KINETIS/KL2x/kl25z.h
new file mode 100644
index 000000000..5fa678f0b
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/kl25z.h
@@ -0,0 +1,1147 @@
+/*
+ * Copyright © 2013 Fabio Utzig, http://fabioutzig.com
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the “Software”),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _KL25Z_H_
+#define _KL25Z_H_
+
+/*
+ * ==============================================================
+ * ---------- Interrupt Number Definition -----------------------
+ * ==============================================================
+ */
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ****************/
+ Reset_IRQn = -15,
+ NonMaskableInt_IRQn = -14,
+ HardFault_IRQn = -13,
+ SVCall_IRQn = -5,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+
+/****** KL2x Specific Interrupt Numbers ***********************/
+ DMA0_IRQn = 0,
+ DMA1_IRQn = 1,
+ DMA2_IRQn = 2,
+ DMA3_IRQn = 3,
+ Reserved0_IRQn = 4,
+ FTFA_IRQn = 5,
+ PMC_IRQn = 6,
+ LLWU_IRQn = 7,
+ I2C0_IRQn = 8,
+ I2C1_IRQn = 9,
+ SPI0_IRQn = 10,
+ SPI1_IRQn = 11,
+ UART0_IRQn = 12,
+ UART1_IRQn = 13,
+ UART2_IRQn = 14,
+ ADC0_IRQn = 15,
+ CMP0_IRQn = 16,
+ TMP0_IRQn = 17,
+ TMP1_IRQn = 18,
+ TMP2_IRQn = 19,
+ RTC0_IRQn = 20,
+ RTC1_IRQn = 21,
+ PIT_IRQn = 22,
+ Reserved1_IRQn = 23,
+ USB_OTG_IRQn = 24,
+ DAC0_IRQn = 25,
+ TSI0_IRQn = 26,
+ MCG_IRQn = 27,
+ LPTMR0_IRQn = 28,
+ Reserved2_IRQn = 29,
+ PINA_IRQn = 30,
+ PIND_IRQn = 31,
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/**
+ * @brief STM32F0xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+
+typedef struct
+{
+ __IO uint32_t SOPT1;
+ __IO uint32_t SOPT1CFG;
+ uint32_t RESERVED0[1023];
+ __IO uint32_t SOPT2;
+ __I uint32_t RESERVED1[1];
+ __IO uint32_t SOPT4;
+ __IO uint32_t SOPT5;
+ uint32_t RESERVED2[1];
+ __IO uint32_t SOPT7;
+ uint32_t RESERVED3[2];
+ __IO uint32_t SDID;
+ uint32_t RESERVED4[3];
+ __IO uint32_t SCGC4;
+ __IO uint32_t SCGC5;
+ __IO uint32_t SCGC6;
+ __IO uint32_t SCGC7;
+ __IO uint32_t CLKDIV1;
+ uint32_t RESERVED5[1];
+ __IO uint32_t FCFG1;
+ __IO uint32_t FCFG2;
+ uint32_t RESERVED6[1];
+ __IO uint32_t UIDMH;
+ __IO uint32_t UIDML;
+ __IO uint32_t UIDL;
+ uint32_t RESERVED7[39];
+ __IO uint32_t COPC;
+ __IO uint32_t SRVCOP;
+} SIM_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t PE1;
+ __IO uint8_t PE2;
+ __IO uint8_t PE3;
+ __IO uint8_t PE4;
+ __IO uint8_t ME;
+ __IO uint8_t F1;
+ __IO uint8_t F2;
+ __I uint8_t F3;
+ __IO uint8_t FILT1;
+ __IO uint8_t FILT2;
+} LLWU_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t PCR[32];
+ __IO uint32_t GPCLR;
+ __IO uint32_t GPCHR;
+ uint32_t RESERVED0[6];
+ __IO uint32_t ISFR;
+} PORT_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t C1;
+ __IO uint8_t C2;
+ __IO uint8_t C3;
+ __IO uint8_t C4;
+ __IO uint8_t C5;
+ __IO uint8_t C6;
+ __IO uint8_t S;
+ uint8_t RESERVED0[1];
+ __IO uint8_t SC;
+ uint8_t RESERVED1[1];
+ __IO uint8_t ATCVH;
+ __IO uint8_t ATCVL;
+ __IO uint8_t C7;
+ __IO uint8_t C8;
+ __IO uint8_t C9;
+ __IO uint8_t C10;
+} MCG_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t CR;
+} OSC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SAR;
+ __IO uint32_t DAR;
+ __IO uint32_t DSR_BCR;
+ __IO uint32_t DCR;
+} DMAChannel_TypeDef;
+
+typedef struct
+{
+ DMAChannel_TypeDef ch[4];
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t CHCFG[4];
+} DMAMUX_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SC;
+ __IO uint32_t CNT;
+ __IO uint32_t MOD;
+ __IO uint32_t C0SC;
+ __IO uint32_t C0V;
+ __IO uint32_t C1SC;
+ __IO uint32_t C1V;
+ __IO uint32_t C2SC;
+ __IO uint32_t C2V;
+ __IO uint32_t C3SC;
+ __IO uint32_t C3V;
+ __IO uint32_t C4SC;
+ __IO uint32_t C4V;
+ __IO uint32_t C5SC;
+ __IO uint32_t C5V;
+ uint32_t RESERVED0[5];
+ __IO uint32_t STATUS;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CONF;
+} TPM_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SC1A; // offset: 0x00
+ __IO uint32_t SC1B; // offset: 0x04
+ __IO uint32_t CFG1; // offset: 0x08
+ __IO uint32_t CFG2; // offset: 0x0C
+ __I uint32_t RA; // offset: 0x10
+ __I uint32_t RB; // offset: 0x14
+ __IO uint32_t CV1; // offset: 0x18
+ __IO uint32_t CV2; // offset: 0x1C
+ __IO uint32_t SC2; // offset: 0x20
+ __IO uint32_t SC3; // offset: 0x24
+ __IO uint32_t OFS; // offset: 0x28
+ __IO uint32_t PG; // offset: 0x2C
+ __IO uint32_t MG; // offset: 0x30
+ __IO uint32_t CLPD; // offset: 0x34
+ __IO uint32_t CLPS; // offset: 0x38
+ __IO uint32_t CLP4; // offset: 0x3C
+ __IO uint32_t CLP3; // offset: 0x40
+ __IO uint32_t CLP2; // offset: 0x44
+ __IO uint32_t CLP1; // offset: 0x48
+ __IO uint32_t CLP0; // offset: 0x4C
+ uint32_t RESERVED0[1]; // offset: 0x50
+ __IO uint32_t CLMD; // offset: 0x54
+ __IO uint32_t CLMS; // offset: 0x58
+ __IO uint32_t CLM4; // offset: 0x5C
+ __IO uint32_t CLM3; // offset: 0x60
+ __IO uint32_t CLM2; // offset: 0x64
+ __IO uint32_t CLM1; // offset: 0x68
+ __IO uint32_t CLM0; // offset: 0x6C
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR;
+ __IO uint32_t PSR;
+ __IO uint32_t CMR;
+ __I uint32_t CNR;
+} LPTMR_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t GENCS;
+ __IO uint32_t DATA;
+ __IO uint32_t TSHD;
+} TSI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t PDOR;
+ __IO uint32_t PSOR;
+ __IO uint32_t PCOR;
+ __IO uint32_t PTOR;
+ __IO uint32_t PDIR;
+ __IO uint32_t PDDR;
+} GPIO_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t C1;
+ __IO uint8_t C2;
+ __IO uint8_t BR;
+ __IO uint8_t S;
+ uint8_t RESERVED0[1];
+ __IO uint8_t D;
+ uint8_t RESERVED1[1];
+ __IO uint8_t M;
+} SPI_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t A1;
+ __IO uint8_t F;
+ __IO uint8_t C1;
+ __IO uint8_t S;
+ __IO uint8_t D;
+ __IO uint8_t C2;
+ __IO uint8_t FLT;
+ __IO uint8_t RA;
+ __IO uint8_t SMB;
+ __IO uint8_t A2;
+ __IO uint8_t SLTH;
+ __IO uint8_t SLTL;
+} I2C_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t BDH;
+ __IO uint8_t BDL;
+ __IO uint8_t C1;
+ __IO uint8_t C2;
+ __IO uint8_t S1;
+ __IO uint8_t S2;
+ __IO uint8_t C3;
+ __IO uint8_t D;
+ __IO uint8_t C4;
+} UART_TypeDef;
+
+typedef struct
+{
+ __IO uint8_t BDH;
+ __IO uint8_t BDL;
+ __IO uint8_t C1;
+ __IO uint8_t C2;
+ __IO uint8_t S1;
+ __IO uint8_t S2;
+ __IO uint8_t C3;
+ __IO uint8_t D;
+ __IO uint8_t MA1;
+ __IO uint8_t MA2;
+ __IO uint8_t C4;
+ __IO uint8_t C5;
+} UARTLP_TypeDef;
+
+/****************************************************************/
+/* Peripheral memory map */
+/****************************************************************/
+#define DMA_BASE ((uint32_t)0x40008100)
+#define DMAMUX_BASE ((uint32_t)0x40021000)
+#define TPM0_BASE ((uint32_t)0x40038000)
+#define TPM1_BASE ((uint32_t)0x40039000)
+#define TPM2_BASE ((uint32_t)0x4003A000)
+#define ADC0_BASE ((uint32_t)0x4003B000)
+#define LPTMR0_BASE ((uint32_t)0x40040000)
+#define TSI0_BASE ((uint32_t)0x40045000)
+#define SIM_BASE ((uint32_t)0x40047000)
+#define PORTA_BASE ((uint32_t)0x40049000)
+#define PORTB_BASE ((uint32_t)0x4004A000)
+#define PORTC_BASE ((uint32_t)0x4004B000)
+#define PORTD_BASE ((uint32_t)0x4004C000)
+#define PORTE_BASE ((uint32_t)0x4004D000)
+#define MCG_BASE ((uint32_t)0x40064000)
+#define OSC0_BASE ((uint32_t)0x40065000)
+#define I2C0_BASE ((uint32_t)0x40066000)
+#define I2C1_BASE ((uint32_t)0x40067000)
+#define UART0_BASE ((uint32_t)0x4006A000)
+#define UART1_BASE ((uint32_t)0x4006B000)
+#define UART2_BASE ((uint32_t)0x4006C000)
+#define SPI0_BASE ((uint32_t)0x40076000)
+#define SPI1_BASE ((uint32_t)0x40077000)
+#define LLWU_BASE ((uint32_t)0x4007C000)
+#define GPIOA_BASE ((uint32_t)0x400FF000)
+#define GPIOB_BASE ((uint32_t)0x400FF040)
+#define GPIOC_BASE ((uint32_t)0x400FF080)
+#define GPIOD_BASE ((uint32_t)0x400FF0C0)
+#define GPIOE_BASE ((uint32_t)0x400FF100)
+
+/****************************************************************/
+/* Peripheral declaration */
+/****************************************************************/
+#define DMA ((DMA_TypeDef *) DMA_BASE)
+#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE)
+#define TPM0 ((TPM_TypeDef *) TPM0_BASE)
+#define TPM1 ((TPM_TypeDef *) TPM1_BASE)
+#define TPM2 ((TPM_TypeDef *) TPM2_BASE)
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
+#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE)
+#define TSI0 ((TSI_TypeDef *) TSI0_BASE)
+#define SIM ((SIM_TypeDef *) SIM_BASE)
+#define LLWU ((LLWU_TypeDef *) LLWU_BASE)
+#define PORTA ((PORT_TypeDef *) PORTA_BASE)
+#define PORTB ((PORT_TypeDef *) PORTB_BASE)
+#define PORTC ((PORT_TypeDef *) PORTC_BASE)
+#define PORTD ((PORT_TypeDef *) PORTD_BASE)
+#define PORTE ((PORT_TypeDef *) PORTE_BASE)
+#define MCG ((MCG_TypeDef *) MCG_BASE)
+#define OSC0 ((OSC_TypeDef *) OSC0_BASE)
+#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define UART0 ((UARTLP_TypeDef *) UART0_BASE)
+#define UART1 ((UART_TypeDef *) UART1_BASE)
+#define UART2 ((UART_TypeDef *) UART2_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+
+/****************************************************************/
+/* Peripheral Registers Bits Definition */
+/****************************************************************/
+
+/****************************************************************/
+/* */
+/* System Integration Module (SIM) */
+/* */
+/****************************************************************/
+/********* Bits definition for SIM_SOPT1 register *************/
+#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */
+#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */
+#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */
+#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */
+#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */
+
+/******* Bits definition for SIM_SOPT1CFG register ************/
+#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */
+#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */
+#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */
+
+/******* Bits definition for SIM_SOPT2 register ************/
+#define SIM_SOPT2_UART0SRC_SHIFT 26 /*!< UART0 clock source select (shift) */
+#define SIM_SOPT2_UART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_UART0SRC_SHIFT)) /*!< UART0 clock source select (mask) */
+#define SIM_SOPT2_UART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_UART0SRC_SHIFT) & SIM_SOPT2_UART0SRC_MASK)) /*!< UART0 clock source select */
+#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */
+#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */
+#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */
+#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */
+#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */
+#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */
+#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */
+#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */
+
+/******* Bits definition for SIM_SCGC4 register ************/
+#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */
+#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */
+#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */
+#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */
+#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */
+#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */
+#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */
+#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */
+#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */
+
+/******* Bits definition for SIM_SCGC5 register ************/
+#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */
+#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */
+#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */
+#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */
+#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */
+#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */
+#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */
+
+/****** Bits definition for SIM_CLKDIV1 register ***********/
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */
+#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */
+#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */
+#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */
+#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */
+
+/****************************************************************/
+/* */
+/* Low-Leakage Wakeup Unit (LLWU) */
+/* */
+/****************************************************************/
+/********** Bits definition for LLWU_PE1 register *************/
+#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */
+#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */
+#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */
+#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */
+#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */
+#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */
+#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */
+#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */
+#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */
+#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */
+#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */
+#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */
+
+/********** Bits definition for LLWU_PE2 register *************/
+#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */
+#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */
+#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */
+#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */
+#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */
+#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */
+#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */
+#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */
+#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */
+#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */
+#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */
+#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */
+
+/********** Bits definition for LLWU_PE3 register *************/
+#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */
+#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */
+#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */
+#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */
+#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */
+#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */
+#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */
+#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */
+#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */
+#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */
+#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */
+#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */
+
+/********** Bits definition for LLWU_PE4 register *************/
+#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */
+#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */
+#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */
+#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */
+#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */
+#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */
+#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */
+#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */
+#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */
+#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */
+#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */
+#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */
+
+/********** Bits definition for LLWU_ME register *************/
+#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */
+#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */
+#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */
+#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */
+#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */
+#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */
+#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */
+#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */
+
+/********** Bits definition for LLWU_F1 register *************/
+#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */
+#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */
+#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */
+#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */
+#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */
+#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */
+#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */
+#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */
+
+/********** Bits definition for LLWU_F2 register *************/
+#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */
+#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */
+#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */
+#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */
+#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */
+#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */
+#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */
+#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */
+
+/********** Bits definition for LLWU_F3 register *************/
+#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */
+#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */
+#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */
+#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */
+#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */
+#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */
+#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */
+#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */
+
+/********** Bits definition for LLWU_FILT1 register *************/
+#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */
+#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */
+#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */
+#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */
+#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */
+#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */
+#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */
+#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */
+#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */
+#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */
+#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */
+
+/********** Bits definition for LLWU_FILT2 register *************/
+#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */
+#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */
+#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */
+#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */
+#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */
+#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */
+#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */
+#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */
+#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */
+#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */
+#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */
+
+/****************************************************************/
+/* */
+/* Port Control and interrupts (PORT) */
+/* */
+/****************************************************************/
+/******** Bits definition for PORTx_PCRn register *************/
+#define PORTx_PCRn_ISR ((uint32_t)0x01000000) /*!< Interrupt Status Flag */
+#define PORTx_PCRn_IRQC ((uint32_t)0x000F0000) /*!< Interrupt Configuration */
+#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */
+#define PORTx_PCRn_MUX_MASK ((uint32_t)0x00000700) /*!< Pin Mux Control (mask) */
+#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */
+#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */
+#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */
+#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */
+#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */
+#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */
+
+/****************************************************************/
+/* */
+/* Oscillator (OSC) */
+/* */
+/****************************************************************/
+/*********** Bits definition for OSC_CR register **************/
+#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */
+#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */
+#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */
+#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */
+#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */
+#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */
+
+/****************************************************************/
+/* */
+/* Direct Memory Access (DMA) */
+/* */
+/****************************************************************/
+/*********** Bits definition for DMA_BCRn register ************/
+#define DMA_DSR_BCRn_CE ((uint32_t)((uint32_t)1 << 30)) /*!< Configuration Error */
+#define DMA_DSR_BCRn_BES ((uint32_t)((uint32_t)1 << 29)) /*!< Bus Error on Source */
+#define DMA_DSR_BCRn_BED ((uint32_t)((uint32_t)1 << 28)) /*!< Bus Error on Destination */
+#define DMA_DSR_BCRn_REQ ((uint32_t)((uint32_t)1 << 26)) /*!< Request */
+#define DMA_DSR_BCRn_BSY ((uint32_t)((uint32_t)1 << 25)) /*!< Busy */
+#define DMA_DSR_BCRn_DONE ((uint32_t)((uint32_t)1 << 24)) /*!< Transactions done */
+#define DMA_DSR_BCRn_BCR_SHIFT 0 /*!< Bytes yet to be transferred for block (shift) */
+#define DMA_DSR_BCRn_BCR_MASK ((uint32_t)((uint32_t)0x00FFFFFF << DMA_DSR_BCRn_BCR_SHIFT)) /*!< Bytes yet to be transferred for block (mask) */
+#define DMA_DSR_BCRn_BCR(x) ((uint32_t)(((uint32_t)(x) << DMA_DSR_BCRn_BCR_SHIFT) & DMA_DSR_BCRn_BCR_MASK)) /*!< Bytes yet to be transferred for block */
+
+/*********** Bits definition for DMA_DCRn register ************/
+#define DMA_DCRn_EINT ((uint32_t)((uint32_t)1 << 31)) /*!< Enable interrupt on completion of transfer */
+#define DMA_DCRn_ERQ ((uint32_t)((uint32_t)1 << 30)) /*!< Enable peripheral request */
+#define DMA_DCRn_CS ((uint32_t)((uint32_t)1 << 29)) /*!< Cycle steal */
+#define DMA_DCRn_AA ((uint32_t)((uint32_t)1 << 28)) /*!< Auto-align */
+#define DMA_DCRn_EADREQ ((uint32_t)((uint32_t)1 << 23)) /*!< Enable asynchronous DMA requests */
+#define DMA_DCRn_SINC ((uint32_t)((uint32_t)1 << 22)) /*!< Source increment */
+#define DMA_DCRn_SSIZE_SHIFT 20 /*!< Source size (shift) */
+#define DMA_DCRn_SSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_SSIZE_SHIFT)) /*!< Source size (mask) */
+#define DMA_DCRn_SSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SSIZE_SHIFT) & DMA_DCRn_SSIZE_MASK)) /*!< Source size */
+#define DMA_DCRn_DINC ((uint32_t)((uint32_t)1 << 19)) /*!< Destination increment */
+#define DMA_DCRn_DSIZE_SHIFT 17 /*!< Destination size (shift) */
+#define DMA_DCRn_DSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_DSIZE_SHIFT)) /*!< Destination size (mask) */
+#define DMA_DCRn_DSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DSIZE_SHIFT) & DMA_DCRn_DSIZE_MASK)) /*!< Destination size */
+#define DMA_DCRn_START ((uint32_t)((uint32_t)1 << 16)) /*!< Start transfer */
+#define DMA_DCRn_SMOD_SHIFT 12 /*!< Source address modulo (shift) */
+#define DMA_DCRn_SMOD_MASK ((uint32_t)((uint32_t)0x0F << DMA_DCRn_SMOD_SHIFT)) /*!< Source address modulo (mask) */
+#define DMA_DCRn_SMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SMOD_SHIFT) & DMA_DCRn_SMOD_MASK)) /*!< Source address modulo */
+#define DMA_DCRn_DMOD_SHIFT 8 /*!< Destination address modulo (shift) */
+#define DMA_DCRn_DMOD_MASK ((uint32_t)0x0F << DMA_DCRn_DMOD_SHIFT) /*!< Destination address modulo (mask) */
+#define DMA_DCRn_DMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DMOD_SHIFT) & DMA_DCRn_DMOD_MASK)) /*!< Destination address modulo */
+#define DMA_DCRn_D_REQ ((uint32_t)((uint32_t)1 << 7)) /*!< Disable request */
+#define DMA_DCRn_LINKCC_SHIFT 4 /*!< Link channel control (shift) */
+#define DMA_DCRn_LINKCC_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LINKCC_SHIFT)) /*!< Link channel control (mask) */
+#define DMA_DCRn_LINKCC(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LINKCC_SHIFT) & DMA_DCRn_LINKCC_MASK)) /*!< Link channel control */
+#define DMA_DCRn_LCH1_SHIFT 2 /*!< Link channel 1 (shift) */
+#define DMA_DCRn_LCH1_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH1_SHIFT)) /*!< Link channel 1 (mask) */
+#define DMA_DCRn_LCH1(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH1_SHIFT) & DMA_DCRn_LCH1_MASK)) /*!< Link channel 1 */
+#define DMA_DCRn_LCH2_SHIFT 0 /*!< Link channel 2 (shift) */
+#define DMA_DCRn_LCH2_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH2_SHIFT)) /*!< Link channel 2 (mask) */
+#define DMA_DCRn_LCH2(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH2_SHIFT) & DMA_DCRn_LCH2_MASK)) /*!< Link channel 2 */
+
+/****************************************************************/
+/* */
+/* Direct Memory Access Multiplexer (DMAMUX) */
+/* */
+/****************************************************************/
+/******** Bits definition for DMAMUX_CHCFGn register **********/
+#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */
+#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */
+#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */
+#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */
+#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */
+
+/****************************************************************/
+/* */
+/* Analog-to-Digital Converter (ADC) */
+/* */
+/****************************************************************/
+/*********** Bits definition for ADCx_SC1n register ***********/
+#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */
+#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */
+#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */
+#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */
+#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */
+#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */
+
+/*********** Bits definition for ADCx_CFG1 register ***********/
+#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */
+#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */
+#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */
+#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */
+#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */
+#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */
+#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */
+#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */
+#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */
+#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */
+#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */
+
+/*********** Bits definition for ADCx_CFG2 register ***********/
+#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */
+#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */
+#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */
+#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */
+#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */
+#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */
+
+/*********** Bits definition for ADCx_SC2 register ***********/
+#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */
+#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */
+#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */
+#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */
+#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */
+#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */
+#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */
+#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */
+#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */
+
+/*********** Bits definition for ADCx_SC3 register ***********/
+#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */
+#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */
+#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */
+#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */
+#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */
+#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */
+#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */
+
+/****************************************************************/
+/* */
+/* Low-Power Timer (LPTMR) */
+/* */
+/****************************************************************/
+/********** Bits definition for LPTMRx_CSR register ***********/
+#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */
+#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */
+#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */
+#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */
+#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */
+#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */
+#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */
+#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */
+#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */
+
+/********** Bits definition for LPTMRx_PSR register ***********/
+#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */
+#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */
+#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */
+#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */
+#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */
+#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */
+#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */
+
+/********** Bits definition for LPTMRx_CMR register ***********/
+#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */
+#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */
+#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */
+
+/********** Bits definition for LPTMRx_CNR register ***********/
+#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */
+#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */
+#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */
+
+/****************************************************************/
+/* */
+/* Touch Sensing Input (TSI) */
+/* */
+/****************************************************************/
+/********** Bits definition for TSIx_GENCS register ***********/
+#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */
+#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */
+#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */
+#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */
+#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */
+#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */
+#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */
+#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */
+#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */
+#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */
+#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */
+#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */
+#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */
+#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */
+#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */
+#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */
+#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */
+#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */
+#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */
+#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */
+#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */
+#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */
+#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */
+#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */
+#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */
+#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */
+#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */
+
+/********** Bits definition for TSIx_DATA register ************/
+#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */
+#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */
+#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */
+#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */
+#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */
+#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */
+#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */
+#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */
+
+/********** Bits definition for TSIx_TSHD register ************/
+#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */
+#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */
+#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */
+#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */
+#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */
+#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */
+
+/****************************************************************/
+/* */
+/* Multipurpose Clock Generator (MCG) */
+/* */
+/****************************************************************/
+/*********** Bits definition for MCG_C1 register **************/
+#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */
+#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */
+#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */
+#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */
+#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */
+#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */
+#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */
+#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */
+#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */
+#define MCG_C1_IREFS ((uint8_t)((uint8_t)1 << 2)) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */
+#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */
+#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */
+
+/*********** Bits definition for MCG_C2 register **************/
+#define MCG_C2_LOCRE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Clock Reset Enable */
+#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */
+#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */
+#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */
+#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */
+#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */
+#define MCG_C2_LP ((uint8_t)((uint8_t)1 << 1)) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */
+#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */
+
+/*********** Bits definition for MCG_C3 register **************/
+#define MCG_C3_SCTRIM_SHIFT 0 /*!< Slow Internal Reference Clock Trim Setting (shift) */
+#define MCG_C3_SCTRIM_MASK ((uint8_t)((uint8_t)0xFF << MCG_C3_SCTRIM_SHIFT)) /*!< Slow Internal Reference Clock Trim Setting (mask) */
+#define MCG_C3_SCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C3_SCTRIM_SHIFT) & MCG_C3_SCTRIM_MASK)) /*!< Slow Internal Reference Clock Trim Setting */
+
+/*********** Bits definition for MCG_C4 register **************/
+#define MCG_C4_DMX32 ((uint8_t)((uint8_t)1 << 7)) /*!< DCO Maximum Frequency with 32.768 kHz Reference */
+#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */
+#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */
+#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */
+#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */
+#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0x0F << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */
+#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */
+#define MCG_C4_SCFTRIM ((uint8_t)((uint8_t)1 << 0)) /*!< Slow Internal Reference Clock Fine Trim */
+
+/*********** Bits definition for MCG_C5 register **************/
+#define MCG_C5_PLLCLKEN0 ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Clock Enable */
+#define MCG_C5_PLLSTEN0 ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Stop Enable */
+#define MCG_C5_PRDIV0_SHIFT 0 /*!< PLL External Reference Divider (shift) */
+#define MCG_C5_PRDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C5_PRDIV0_SHIFT)) /*!< PLL External Reference Divider (mask) */
+#define MCG_C5_PRDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C5_PRDIV0_SHIFT) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */
+
+/*********** Bits definition for MCG_C6 register **************/
+#define MCG_C6_LOLIE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Interrupt Enable */
+#define MCG_C6_PLLS ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Select */
+#define MCG_C6_CME0 ((uint8_t)((uint8_t)1 << 5)) /*!< Clock Monitor Enable */
+#define MCG_C6_VDIV0_SHIFT 0 /*!< VCO 0 Divider (shift) */
+#define MCG_C6_VDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C6_VDIV0_SHIFT)) /*!< VCO 0 Divider (mask) */
+#define MCG_C6_VDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C6_VDIV0_SHIFT) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */
+
+/************ Bits definition for MCG_S register **************/
+#define MCG_S_LOLS ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Status */
+#define MCG_S_LOCK0 ((uint8_t)((uint8_t)1 << 6)) /*!< Lock Status */
+#define MCG_S_PLLST ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Select Status */
+#define MCG_S_IREFST ((uint8_t)((uint8_t)1 << 4)) /*!< Internal Reference Status */
+#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */
+#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */
+#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */
+#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */
+#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */
+#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */
+#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */
+#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */
+#define MCG_S_IRCST ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Status */
+
+/************ Bits definition for MCG_SC register **************/
+#define MCG_SC_ATME ((uint8_t)((uint8_t)1 << 7)) /*!< Automatic Trim Machine Enable */
+#define MCG_SC_ATMS ((uint8_t)((uint8_t)1 << 6)) /*!< Automatic Trim Machine Select */
+#define MCG_SC_ATMF ((uint8_t)((uint8_t)1 << 5)) /*!< Automatic Trim Machine Fail Flag */
+#define MCG_SC_FLTPRSRV ((uint8_t)((uint8_t)1 << 4) /*!< FLL Filter Preserve Enable */
+#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */
+#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */
+#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */
+#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */
+#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */
+#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */
+#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */
+#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */
+#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */
+#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */
+#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */
+#define MCG_SC_LOCS0 ((uint8_t)((uint8_t)1 << 0) /*!< OSC0 Loss of Clock Status */
+
+/*********** Bits definition for MCG_ATCVH register ************/
+#define MCG_ATCVH_ATCVH_SHIFT 0 /*!< MCG Auto Trim Compare Value High Register (shift) */
+#define MCG_ATCVH_ATCVH_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVH_ATCVH_SHIFT)) /*!< MCG Auto Trim Compare Value High Register (mask) */
+#define MCG_ATCVH_ATCVH(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVH_ATCVH_SHIFT) & MCG_ATCVH_ATCVH_MASK)) /*!< MCG Auto Trim Compare Value High Register */
+
+/*********** Bits definition for MCG_ATCVL register ************/
+#define MCG_ATCVL_ATCVL_SHIFT 0 /*!< MCG Auto Trim Compare Value Low Register (shift) */
+#define MCG_ATCVL_ATCVL_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVL_ATCVL_SHIFT)) /*!< MCG Auto Trim Compare Value Low Register (mask) */
+#define MCG_ATCVL_ATCVL(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVL_ATCVL_SHIFT) & MCG_ATCVL_ATCVL_MASK)) /*!< MCG Auto Trim Compare Value Low Register */
+
+/************ Bits definition for MCG_C7 register **************/
+/* All MCG_C7 bits are reserved on the KL25Z. */
+
+/************ Bits definition for MCG_C8 register **************/
+#define MCG_C8_LOLRE ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Loss of Lock Reset Enable */
+
+/************ Bits definition for MCG_C9 register **************/
+/* All MCG_C9 bits are reserved on the KL25Z. */
+
+/************ Bits definition for MCG_C10 register *************/
+/* All MCG_C10 bits are reserved on the KL25Z. */
+
+
+/****************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/****************************************************************/
+/*********** Bits definition for SPIx_C1 register *************/
+#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */
+#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */
+#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */
+#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */
+#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */
+#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */
+#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */
+#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */
+
+/*********** Bits definition for SPIx_C2 register *************/
+#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */
+#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */
+#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */
+#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */
+#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */
+#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */
+#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */
+
+/*********** Bits definition for SPIx_BR register *************/
+#define SPIx_BR_SPPR ((uint8_t)0x70) /*!< SPI Baud rate Prescaler Divisor */
+#define SPIx_BR_SPR ((uint8_t)0x0F) /*!< SPI Baud rate Divisor */
+
+#define SPIx_BR_SPPR_SHIFT 4
+
+/*********** Bits definition for SPIx_S register **************/
+#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */
+#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */
+#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */
+#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */
+
+/*********** Bits definition for SPIx_D register **************/
+#define SPIx_D_DATA ((uint8_t)0xFF) /*!< Data */
+
+/*********** Bits definition for SPIx_M register **************/
+#define SPIx_M_DATA ((uint8_t)0xFF) /*!< SPI HW Compare value for Match */
+
+/****************************************************************/
+/* */
+/* Inter-Integrated Circuit (I2C) */
+/* */
+/****************************************************************/
+/*********** Bits definition for I2Cx_A1 register *************/
+#define I2Cx_A1_AD ((uint8_t)0xFE) /*!< Address [7:1] */
+
+#define I2Cx_A1_AD_SHIT 1
+
+/*********** Bits definition for I2Cx_F register **************/
+#define I2Cx_F_MULT ((uint8_t)0xC0) /*!< Multiplier factor */
+#define I2Cx_F_ICR ((uint8_t)0x3F) /*!< Clock rate */
+
+#define I2Cx_F_MULT_SHIFT 5
+
+/*********** Bits definition for I2Cx_C1 register *************/
+#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */
+#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */
+#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */
+#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */
+#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */
+#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */
+#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */
+#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */
+
+/*********** Bits definition for I2Cx_S register **************/
+#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */
+#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */
+#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */
+#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */
+#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */
+#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */
+#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */
+#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */
+
+/*********** Bits definition for I2Cx_D register **************/
+#define I2Cx_D_DATA ((uint8_t)0xFF) /*!< Data */
+
+/*********** Bits definition for I2Cx_C2 register *************/
+#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */
+#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */
+#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */
+#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */
+#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */
+#define I2Cx_C2_AD_10_8 ((uint8_t)0x03) /*!< Slave Address [10:8] */
+
+/*********** Bits definition for I2Cx_FLT register ************/
+#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */
+#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */
+#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */
+#define I2Cx_FLT_FLT ((uint8_t)0x1F) /*!< I2C Programmable Filter Factor */
+
+/*********** Bits definition for I2Cx_RA register *************/
+#define I2Cx_RA_RAD ((uint8_t)0xFE) /*!< Range Slave Address */
+
+#define I2Cx_RA_RAD_SHIFT 1
+
+/*********** Bits definition for I2Cx_SMB register ************/
+#define I2Cx_SMB_FACK ((uint8_t)0x00) /*!< Fast NACK/ACK Enable */
+#define I2Cx_SMB_ALERTEN ((uint8_t)0x00) /*!< SMBus Alert Response Address Enable */
+#define I2Cx_SMB_SIICAEN ((uint8_t)0x00) /*!< Second I2C Address Enable */
+#define I2Cx_SMB_TCKSEL ((uint8_t)0x00) /*!< Timeout Counter Clock Select */
+#define I2Cx_SMB_SLTF ((uint8_t)0x00) /*!< SCL Low Timeout Flag */
+#define I2Cx_SMB_SHTF1 ((uint8_t)0x00) /*!< SCL High Timeout Flag 1 */
+#define I2Cx_SMB_SHTF2 ((uint8_t)0x00) /*!< SCL High Timeout Flag 2 */
+#define I2Cx_SMB_SHTF2IE ((uint8_t)0x00) /*!< SHTF2 Interrupt Enable */
+
+/*********** Bits definition for I2Cx_A2 register *************/
+#define I2Cx_A2_SAD ((uint8_t)0xFE) /*!< SMBus Address */
+
+#define I2Cx_A2_SAD_SHIFT 1
+
+/*********** Bits definition for I2Cx_SLTH register ***********/
+#define I2Cx_SLTH_SSLT ((uint8_t)0xFF) /*!< MSB of SCL low timeout value */
+
+/*********** Bits definition for I2Cx_SLTL register ***********/
+#define I2Cx_SLTL_SSLT ((uint8_t)0xFF) /*!< LSB of SCL low timeout value */
+
+/****************************************************************/
+/* */
+/* Universal Asynchronous Receiver/Transmitter (UART) */
+/* */
+/****************************************************************/
+/********* Bits definition for UARTx_BDH register *************/
+#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */
+#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */
+#define UARTx_BDH_SBNS ((uint8_t)0x20) /*!< Stop Bit Number Select */
+#define UARTx_BDH_SBR ((uint8_t)0x1F) /*!< Baud Rate Modulo Divisor */
+
+/********* Bits definition for UARTx_BDL register *************/
+#define UARTx_BDL_SBR ((uint8_t)0xFF) /*!< Baud Rate Modulo Divisor */
+
+/********* Bits definition for UARTx_C1 register **************/
+#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */
+#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */
+#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */
+#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */
+#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */
+#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */
+#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */
+#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */
+#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */
+
+/********* Bits definition for UARTx_C2 register **************/
+#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */
+#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */
+#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */
+#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */
+#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */
+#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */
+#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */
+#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */
+
+/********* Bits definition for UARTx_S1 register **************/
+#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */
+#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */
+#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */
+#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */
+#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */
+#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */
+#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */
+#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */
+
+/********* Bits definition for UARTx_S2 register **************/
+#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */
+#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */
+#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */
+#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */
+#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */
+#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */
+#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */
+#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */
+
+/********* Bits definition for UARTx_C3 register **************/
+#define UARTx_C3_R8T9 ((uint8_t)0x80) /*!< Receive Bit 8 / Transmit Bit 9 */
+#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */
+#define UARTx_C3_R9T8 ((uint8_t)0x40) /*!< Receive Bit 9 / Transmit Bit 8 */
+#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */
+#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */
+#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */
+#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */
+#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */
+#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */
+#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */
+
+/********* Bits definition for UARTx_D register ***************/
+#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */
+#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */
+#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */
+#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */
+#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */
+#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */
+#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */
+#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */
+
+/********* Bits definition for UARTx_MA1 register *************/
+#define UARTx_MA1_MA ((uint8_t)0xFF) /*!< Match Address */
+
+/********* Bits definition for UARTx_MA2 register *************/
+#define UARTx_MA2_MA ((uint8_t)0xFF) /*!< Match Address */
+
+/********* Bits definition for UARTx_C4 register **************/
+#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */
+#define UARTx_C4_TDMAS ((uint8_t)0x80) /*!< Transmitter DMA Select */
+#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */
+#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */
+#define UARTx_C4_RDMAS ((uint8_t)0x80) /*!< Receiver Full DMA Select */
+#define UARTx_C4_OSR ((uint8_t)0x1F) /*!< Over Sampling Ratio */
+
+/********* Bits definition for UARTx_C5 register **************/
+#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */
+#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */
+#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */
+#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */
+
+#endif
diff --git a/os/hal/ports/KINETIS/KL2x/pal_lld.c b/os/hal/ports/KINETIS/KL2x/pal_lld.c
new file mode 100644
index 000000000..70dde64f9
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/pal_lld.c
@@ -0,0 +1,225 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/pal_lld.c
+ * @brief Kinetis KL2x PAL subsystem low level driver.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief STM32 I/O ports configuration.
+ * @details Ports A-D(E, F, G, H) clocks enabled.
+ *
+ * @param[in] config the STM32 ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config) {
+
+ int i, j;
+
+ /* Enable clocking of all Ports */
+ SIM->SCGC5 |= SIM_SCGC5_PORTA |
+ SIM_SCGC5_PORTB |
+ SIM_SCGC5_PORTC |
+ SIM_SCGC5_PORTD |
+ SIM_SCGC5_PORTE;
+
+ for (i = 0; i < TOTAL_PORTS; i++) {
+ for (j = 0; j < PADS_PER_PORT; j++) {
+ pal_lld_setpadmode(config->ports[i].port,
+ j,
+ config->ports[i].pads[j]);
+ }
+ }
+}
+
+/**
+ * @brief Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ *
+ * @param[in] port the port identifier
+ * @param[in] mask the group mask
+ * @param[in] mode the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode) {
+
+ (void)port;
+ (void)mask;
+ (void)mode;
+
+}
+
+/**
+ * @brief Reads a logical state from an I/O pad.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @return The logical state.
+ * @retval PAL_LOW low logical state.
+ * @retval PAL_HIGH high logical state.
+ *
+ * @notapi
+ */
+uint8_t pal_lld_readpad(ioportid_t port, uint8_t pad)
+{
+ return (port->PDIR & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW;
+}
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+void pal_lld_writepad(ioportid_t port, uint8_t pad, uint8_t bit)
+{
+ if (bit == PAL_HIGH)
+ port->PDOR |= ((uint32_t) 1 << pad);
+ else
+ port->PDOR &= ~((uint32_t) 1 << pad);
+}
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+void pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
+{
+ PORT_TypeDef *portcfg = NULL;
+
+ osalDbgAssert(pad <= 31, "pal_lld_setpadmode() - invalid pad");
+
+ if (mode == PAL_MODE_OUTPUT_PUSHPULL)
+ port->PDDR |= ((uint32_t) 1 << pad);
+ else
+ port->PDDR &= ~((uint32_t) 1 << pad);
+
+ if (port == IOPORT1)
+ portcfg = PORTA;
+ else if (port == IOPORT2)
+ portcfg = PORTB;
+ else if (port == IOPORT3)
+ portcfg = PORTC;
+ else if (port == IOPORT4)
+ portcfg = PORTD;
+ else if (port == IOPORT5)
+ portcfg = PORTE;
+
+ osalDbgAssert(portcfg != NULL, "pal_lld_setpadmode() - invalid port");
+
+ switch (mode) {
+ case PAL_MODE_RESET:
+ case PAL_MODE_INPUT:
+ case PAL_MODE_OUTPUT_PUSHPULL:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(1);
+ break;
+ case PAL_MODE_INPUT_PULLUP:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(1) | PORTx_PCRn_PE | PORTx_PCRn_PS;
+ break;
+ case PAL_MODE_INPUT_PULLDOWN:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(1) | PORTx_PCRn_PE;
+ break;
+ case PAL_MODE_UNCONNECTED:
+ case PAL_MODE_INPUT_ANALOG:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(0);
+ break;
+ case PAL_MODE_ALTERNATIVE_1:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(1);
+ break;
+ case PAL_MODE_ALTERNATIVE_2:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(2);
+ break;
+ case PAL_MODE_ALTERNATIVE_3:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(3);
+ break;
+ case PAL_MODE_ALTERNATIVE_4:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(4);
+ break;
+ case PAL_MODE_ALTERNATIVE_5:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(5);
+ break;
+ case PAL_MODE_ALTERNATIVE_6:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(6);
+ break;
+ case PAL_MODE_ALTERNATIVE_7:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(7);
+ break;
+ }
+}
+
+#endif /* HAL_USE_PAL */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/pal_lld.h b/os/hal/ports/KINETIS/KL2x/pal_lld.h
new file mode 100644
index 000000000..e59940e23
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/pal_lld.h
@@ -0,0 +1,309 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/pal_lld.h
+ * @brief Kinetis KL2x PAL subsystem low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef _PAL_LLD_H_
+#define _PAL_LLD_H_
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes */
+/*===========================================================================*/
+
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+
+#define PAL_MODE_ALTERNATIVE_1 0x10
+#define PAL_MODE_ALTERNATIVE_2 0x11
+#define PAL_MODE_ALTERNATIVE_3 0x12
+#define PAL_MODE_ALTERNATIVE_4 0x13
+#define PAL_MODE_ALTERNATIVE_5 0x14
+#define PAL_MODE_ALTERNATIVE_6 0x15
+#define PAL_MODE_ALTERNATIVE_7 0x16
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+#define TOTAL_PORTS 5
+#define PADS_PER_PORT 32
+
+/**
+ * @brief Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief Digital I/O modes.
+ */
+typedef uint8_t iomode_t;
+
+/**
+ * @brief Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ * any assumption about it, use the provided macros when populating
+ * variables of this type.
+ */
+typedef GPIO_TypeDef * ioportid_t;
+
+typedef struct {
+ ioportid_t port;
+ iomode_t pads[PADS_PER_PORT];
+} PortConfig;
+
+/**
+ * @brief Generic I/O ports static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ * system startup time in order to initialized the digital I/O
+ * subsystem. This represents only the initial setup, specific pads
+ * or whole ports can be reprogrammed at later time.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct
+{
+ PortConfig ports[TOTAL_PORTS];
+} PALConfig;
+
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 32
+
+/**
+ * @brief Whole port mask.
+ * @brief This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
+
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/*===========================================================================*/
+
+/**
+ * @brief First I/O port identifier.
+ * @details Low level drivers can define multiple ports, it is suggested to
+ * use this naming convention.
+ */
+#define IOPORT1 GPIOA
+#define IOPORT2 GPIOB
+#define IOPORT3 GPIOC
+#define IOPORT4 GPIOD
+#define IOPORT5 GPIOE
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PAL subsystem initialization.
+ *
+ * @param[in] config architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief Reads the physical I/O port states.
+ *
+ * @param[in] port port identifier
+ * @return The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) \
+ (port)->PDIR
+
+/**
+ * @brief Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ * value.
+ *
+ * @param[in] port port identifier
+ * @return The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) 0
+
+/**
+ * @brief Writes a bits mask on a I/O port.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits)
+
+/**
+ * @brief Sets a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits)
+
+/**
+ * @brief Clears a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits)
+
+/**
+ * @brief Toggles a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be XORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_toggleport(port, bits)
+
+/**
+ * @brief Reads a group of bits.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @return The group logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readgroup(port, mask, offset) 0
+
+/**
+ * @brief Writes a group of bits.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group width
+ * are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
+
+/**
+ * @brief Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] mode group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode) \
+ _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief Sets a pad logical state to @p PAL_HIGH.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad) (port)->PSOR |= ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Clears a pad logical state to @p PAL_LOW.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) (port)->PCOR |= ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Toggles a pad logical state.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_togglepad(port, pad) (port)->PTOR |= ((uint32_t) 1 << (pad))
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _pal_lld_init(const PALConfig *config);
+ void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode);
+ void pal_lld_setpadmode(ioportid_t port,
+ uint8_t pad,
+ iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* _PAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/platform.mk b/os/hal/ports/KINETIS/KL2x/platform.mk
new file mode 100644
index 000000000..456bc706a
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/platform.mk
@@ -0,0 +1,10 @@
+# List of all platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x/pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x/serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x/st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x
diff --git a/os/hal/ports/KINETIS/KL2x/serial_lld.c b/os/hal/ports/KINETIS/KL2x/serial_lld.c
new file mode 100644
index 000000000..e780eb8d8
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/serial_lld.c
@@ -0,0 +1,353 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/serial_lld.c
+ * @brief Kinetis KL2x Serial Driver subsystem low level driver source.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+#include "kl25z.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SD1 driver identifier.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig default_config = {
+ 38400
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] u pointer to an UART I/O block
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+ UARTLP_TypeDef *u = sdp->uart;
+
+ if (u->S1 & UARTx_S1_RDRF) {
+ osalSysLockFromISR();
+ if (chIQIsEmptyI(&sdp->iqueue))
+ chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
+ if (chIQPutI(&sdp->iqueue, u->D) < Q_OK)
+ chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
+ osalSysUnlockFromISR();
+ }
+
+ if (u->S1 & UARTx_S1_TDRE) {
+ msg_t b;
+
+ osalSysLockFromISR();
+ b = chOQGetI(&sdp->oqueue);
+ osalSysUnlockFromISR();
+
+ if (b < Q_OK) {
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ osalSysUnlockFromISR();
+ u->C2 &= ~UARTx_C2_TIE;
+ } else {
+ u->D = b;
+ }
+ }
+
+ if (u->S1 & UARTx_S1_IDLE)
+ u->S1 = UARTx_S1_IDLE; // Clear IDLE (S1 bits are write-1-to-clear).
+
+ if (u->S1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ // FIXME: need to add set_error()
+ // Clear flags (S1 bits are write-1-to-clear).
+ u->S1 = UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
+ }
+}
+
+/**
+ * @brief Attempts a TX preload
+ */
+static void preload(SerialDriver *sdp) {
+ UARTLP_TypeDef *u = sdp->uart;
+
+ if (u->S1 & UARTx_S1_TDRE) {
+ msg_t b = chOQGetI(&sdp->oqueue);
+ if (b < Q_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ return;
+ }
+ u->D = b;
+ u->C2 |= UARTx_C2_TIE;
+ }
+}
+
+/**
+ * @brief Driver output notification.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+static void notify1(GenericQueue *qp)
+{
+ (void)qp;
+ preload(&SD1);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+static void notify2(GenericQueue *qp)
+{
+ (void)qp;
+ preload(&SD2);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+static void notify3(GenericQueue *qp)
+{
+ (void)qp;
+ preload(&SD3);
+}
+#endif
+
+/**
+ * @brief Common UART configuration.
+ *
+ */
+static void configure_uart(UARTLP_TypeDef *uart, const SerialConfig *config)
+{
+ uint32_t uart_clock;
+
+ uart->C1 = 0;
+ uart->C3 = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
+ uart->S1 = UARTx_S1_IDLE | UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
+ while (uart->S1 & UARTx_S1_RDRF) {
+ (void)uart->D;
+ }
+
+#if KINETIS_SERIAL_USE_UART0
+ if (uart == UART0) {
+ /* UART0 can be clocked from several sources. */
+ uart_clock = KINETIS_UART0_CLOCK_FREQ;
+ }
+#endif
+#if KINETIS_SERIAL_USE_UART1
+ if (uart == UART1) {
+ uart_clock = KINETIS_BUSCLK_FREQUENCY;
+ }
+#endif
+#if KINETIS_SERIAL_USE_UART2
+ if (uart == UART2) {
+ uart_clock = KINETIS_BUSCLK_FREQUENCY;
+ }
+#endif
+
+ /* FIXME: change fixed OSR = 16 to dynamic value based on baud */
+ uint16_t divisor = (uart_clock / 16) / config->sc_speed;
+ uart->C4 = UARTx_C4_OSR & (16 - 1);
+ uart->BDH = (divisor >> 8) & UARTx_BDH_SBR;
+ uart->BDL = (divisor & UARTx_BDL_SBR);
+
+ uart->C2 = UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(Vector70) {
+
+ CH_IRQ_PROLOGUE();
+ serve_interrupt(&SD1);
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(Vector74) {
+
+ CH_IRQ_PROLOGUE();
+ serve_interrupt(&SD2);
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(Vector78) {
+
+ CH_IRQ_PROLOGUE();
+ serve_interrupt(&SD3);
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if KINETIS_SERIAL_USE_UART0
+ /* Driver initialization.*/
+ sdObjectInit(&SD1, NULL, notify1);
+ SD1.uart = UART0;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1
+ /* Driver initialization.*/
+ sdObjectInit(&SD2, NULL, notify2);
+ SD2.uart = UART1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2
+ /* Driver initialization.*/
+ sdObjectInit(&SD3, NULL, notify3);
+ SD3.uart = UART2;
+#endif
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL)
+ config = &default_config;
+
+ if (sdp->state == SD_STOP) {
+ /* Enables the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ SIM->SCGC4 |= SIM_SCGC4_UART0;
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_UART0SRC_MASK) |
+ SIM_SOPT2_UART0SRC(KINETIS_UART0_CLOCK_SRC);
+ configure_uart(sdp->uart, config);
+ nvicEnableVector(UART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+ SIM->SCGC4 |= SIM_SCGC4_UART1;
+ configure_uart(sdp->uart, config);
+ nvicEnableVector(UART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+ SIM->SCGC4 |= SIM_SCGC4_UART2;
+ configure_uart(sdp->uart, config);
+ nvicEnableVector(UART2_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART2 */
+
+ }
+ /* Configures the peripheral.*/
+
+}
+
+/**
+ * @brief Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ * interrupt vector.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+ /* TODO: Resets the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ nvicDisableVector(UART0_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART0;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+ nvicDisableVector(UART1_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART1;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+ nvicDisableVector(UART2_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART2;
+ }
+#endif
+ }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/serial_lld.h b/os/hal/ports/KINETIS/KL2x/serial_lld.h
new file mode 100644
index 000000000..6ac450aab
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/serial_lld.h
@@ -0,0 +1,163 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/serial_lld.h
+ * @brief Kinetis KL2x Serial Driver subsystem low level driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SD1 driver enable switch.
+ * @details If set to @p TRUE the support for SD1 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART0) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART0 FALSE
+#endif
+/**
+ * @brief SD2 driver enable switch.
+ * @details If set to @p TRUE the support for SD2 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART1) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART1 FALSE
+#endif
+/**
+ * @brief SD3 driver enable switch.
+ * @details If set to @p TRUE the support for SD3 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART2 FALSE
+#endif
+
+/**
+ * @brief UART0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART0_PRIORITY 12
+#endif
+
+/**
+ * @brief UART1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART1_PRIORITY 12
+#endif
+
+/**
+ * @brief UART2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART2_PRIORITY 12
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Generic Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ * in order to configure and start a serial driver operations.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ /**
+ * @brief Bit rate.
+ */
+ uint32_t sc_speed;
+ /* End of the mandatory fields.*/
+} SerialConfig;
+
+/**
+ * @brief @p SerialDriver specific data.
+ */
+#define _serial_driver_data \
+ _base_asynchronous_channel_data \
+ /* Driver state.*/ \
+ sdstate_t state; \
+ /* Input queue.*/ \
+ InputQueue iqueue; \
+ /* Output queue.*/ \
+ OutputQueue oqueue; \
+ /* Input circular buffer.*/ \
+ uint8_t ib[SERIAL_BUFFERS_SIZE]; \
+ /* Output circular buffer.*/ \
+ uint8_t ob[SERIAL_BUFFERS_SIZE]; \
+ /* End of the mandatory fields.*/ \
+ /* Pointer to the UART registers block.*/ \
+ UARTLP_TypeDef *uart;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sd_lld_init(void);
+ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+ void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/st_lld.c b/os/hal/ports/KINETIS/KL2x/st_lld.c
new file mode 100644
index 000000000..b0b731b99
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/st_lld.c
@@ -0,0 +1,98 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/KL2x/st_lld.c
+ * @brief ST Driver subsystem low level driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
+/**
+ * @brief System Timer vector.
+ * @details This interrupt is used for system tick in periodic mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SysTick_Handler) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void) {
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+ /* Periodic systick mode, the Cortex-Mx internal systick timer is used
+ in this mode.*/
+ SysTick->LOAD = (KINETIS_SYSCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk |
+ SysTick_CTRL_TICKINT_Msk;
+
+ /* IRQ enabled.*/
+ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, KINETIS_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/st_lld.h b/os/hal/ports/KINETIS/KL2x/st_lld.h
new file mode 100644
index 000000000..9c548a343
--- /dev/null
+++ b/os/hal/ports/KINETIS/KL2x/st_lld.h
@@ -0,0 +1,156 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/st_lld.h
+ * @brief ST Driver subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ * include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef _ST_LLD_H_
+#define _ST_LLD_H_
+
+#include "mcuconf.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SysTick timer IRQ priority.
+ */
+#if !defined(KINETIS_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_ST_IRQ_PRIORITY 8
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the time counter value.
+ *
+ * @return The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Determines if the alarm is active.
+ *
+ * @return The alarm status.
+ * @retval false if the alarm is not active.
+ * @retval true is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+ return false;
+}
+
+#endif /* _ST_LLD_H_ */
+
+/** @} */
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